1 //
2 // Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer/long registers
173 reg_class all_reg(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all int registers
191 reg_class all_int_reg(RAX
192 RDX,
193 RBP,
194 RDI,
195 RSI,
196 RCX,
197 RBX,
198 R8,
199 R9,
200 R10,
201 R11,
202 R12,
203 R13,
204 R14);
205
206 // Class for all pointer registers
207 reg_class any_reg %{
208 return _ANY_REG_mask;
209 %}
210
211 // Class for all pointer registers (excluding RSP)
212 reg_class ptr_reg %{
213 return _PTR_REG_mask;
214 %}
215
216 // Class for all pointer registers (excluding RSP and RBP)
217 reg_class ptr_reg_no_rbp %{
218 return _PTR_REG_NO_RBP_mask;
219 %}
220
221 // Class for all pointer registers (excluding RAX and RSP)
222 reg_class ptr_no_rax_reg %{
223 return _PTR_NO_RAX_REG_mask;
224 %}
225
226 // Class for all pointer registers (excluding RAX, RBX, and RSP)
227 reg_class ptr_no_rax_rbx_reg %{
228 return _PTR_NO_RAX_RBX_REG_mask;
229 %}
230
231 // Class for all long registers (excluding RSP)
232 reg_class long_reg %{
233 return _LONG_REG_mask;
234 %}
235
236 // Class for all long registers (excluding RAX, RDX and RSP)
237 reg_class long_no_rax_rdx_reg %{
238 return _LONG_NO_RAX_RDX_REG_mask;
239 %}
240
241 // Class for all long registers (excluding RCX and RSP)
242 reg_class long_no_rcx_reg %{
243 return _LONG_NO_RCX_REG_mask;
244 %}
245
246 // Class for all int registers (excluding RSP)
247 reg_class int_reg %{
248 return _INT_REG_mask;
249 %}
250
251 // Class for all int registers (excluding RAX, RDX, and RSP)
252 reg_class int_no_rax_rdx_reg %{
253 return _INT_NO_RAX_RDX_REG_mask;
254 %}
255
256 // Class for all int registers (excluding RCX and RSP)
257 reg_class int_no_rcx_reg %{
258 return _INT_NO_RCX_REG_mask;
259 %}
260
261 // Singleton class for RAX pointer register
262 reg_class ptr_rax_reg(RAX, RAX_H);
263
264 // Singleton class for RBX pointer register
265 reg_class ptr_rbx_reg(RBX, RBX_H);
266
267 // Singleton class for RSI pointer register
268 reg_class ptr_rsi_reg(RSI, RSI_H);
269
270 // Singleton class for RDI pointer register
271 reg_class ptr_rdi_reg(RDI, RDI_H);
272
273 // Singleton class for stack pointer
274 reg_class ptr_rsp_reg(RSP, RSP_H);
275
276 // Singleton class for TLS pointer
277 reg_class ptr_r15_reg(R15, R15_H);
278
279 // Singleton class for RAX long register
280 reg_class long_rax_reg(RAX, RAX_H);
281
282 // Singleton class for RCX long register
283 reg_class long_rcx_reg(RCX, RCX_H);
284
285 // Singleton class for RDX long register
286 reg_class long_rdx_reg(RDX, RDX_H);
287
288 // Singleton class for RAX int register
289 reg_class int_rax_reg(RAX);
290
291 // Singleton class for RBX int register
292 reg_class int_rbx_reg(RBX);
293
294 // Singleton class for RCX int register
295 reg_class int_rcx_reg(RCX);
296
297 // Singleton class for RCX int register
298 reg_class int_rdx_reg(RDX);
299
300 // Singleton class for RCX int register
301 reg_class int_rdi_reg(RDI);
302
303 // Singleton class for instruction pointer
304 // reg_class ip_reg(RIP);
305
306 %}
307
308 //----------SOURCE BLOCK-------------------------------------------------------
309 // This is a block of C++ code which provides values, functions, and
310 // definitions necessary in the rest of the architecture description
311 source_hpp %{
312
313 extern RegMask _ANY_REG_mask;
314 extern RegMask _PTR_REG_mask;
315 extern RegMask _PTR_REG_NO_RBP_mask;
316 extern RegMask _PTR_NO_RAX_REG_mask;
317 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
318 extern RegMask _LONG_REG_mask;
319 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
320 extern RegMask _LONG_NO_RCX_REG_mask;
321 extern RegMask _INT_REG_mask;
322 extern RegMask _INT_NO_RAX_RDX_REG_mask;
323 extern RegMask _INT_NO_RCX_REG_mask;
324
325 extern RegMask _STACK_OR_PTR_REG_mask;
326 extern RegMask _STACK_OR_LONG_REG_mask;
327 extern RegMask _STACK_OR_INT_REG_mask;
328
329 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
330 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
331 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
332
333 %}
334
335 source %{
336 #define RELOC_IMM64 Assembler::imm_operand
337 #define RELOC_DISP32 Assembler::disp32_operand
338
339 #define __ _masm.
340
341 RegMask _ANY_REG_mask;
342 RegMask _PTR_REG_mask;
343 RegMask _PTR_REG_NO_RBP_mask;
344 RegMask _PTR_NO_RAX_REG_mask;
345 RegMask _PTR_NO_RAX_RBX_REG_mask;
346 RegMask _LONG_REG_mask;
347 RegMask _LONG_NO_RAX_RDX_REG_mask;
348 RegMask _LONG_NO_RCX_REG_mask;
349 RegMask _INT_REG_mask;
350 RegMask _INT_NO_RAX_RDX_REG_mask;
351 RegMask _INT_NO_RCX_REG_mask;
352 RegMask _STACK_OR_PTR_REG_mask;
353 RegMask _STACK_OR_LONG_REG_mask;
354 RegMask _STACK_OR_INT_REG_mask;
355
356 static bool need_r12_heapbase() {
357 return UseCompressedOops || UseCompressedClassPointers;
358 }
359
360 void reg_mask_init() {
361 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
362 // We derive a number of subsets from it.
363 _ANY_REG_mask = _ALL_REG_mask;
364
365 if (PreserveFramePointer) {
366 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
367 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
368 }
369 if (need_r12_heapbase()) {
370 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
371 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
372 }
373
374 _PTR_REG_mask = _ANY_REG_mask;
375 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
376 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
377 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
378 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
379
380 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
381 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
382
383 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
384 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
385 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
386
387 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
388 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
389 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
390
391 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
392 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
393 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
394
395 _LONG_REG_mask = _PTR_REG_mask;
396 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
397 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
398
399 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
400 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
401 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
402 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
403 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
404
405 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
406 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
407 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
408
409 _INT_REG_mask = _ALL_INT_REG_mask;
410 if (PreserveFramePointer) {
411 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
412 }
413 if (need_r12_heapbase()) {
414 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
415 }
416
417 _STACK_OR_INT_REG_mask = _INT_REG_mask;
418 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
419
420 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
421 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
422 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
423
424 _INT_NO_RCX_REG_mask = _INT_REG_mask;
425 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
426 }
427
428 static bool generate_vzeroupper(Compile* C) {
429 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
430 }
431
432 static int clear_avx_size() {
433 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
434 }
435
436 // !!!!! Special hack to get all types of calls to specify the byte offset
437 // from the start of the call to the point where the return address
438 // will point.
439 int MachCallStaticJavaNode::ret_addr_offset()
440 {
441 int offset = 5; // 5 bytes from start of call to where return address points
442 offset += clear_avx_size();
443 return offset;
444 }
445
446 int MachCallDynamicJavaNode::ret_addr_offset()
447 {
448 int offset = 15; // 15 bytes from start of call to where return address points
449 offset += clear_avx_size();
450 return offset;
451 }
452
453 int MachCallRuntimeNode::ret_addr_offset() {
454 int offset = 13; // movq r10,#addr; callq (r10)
455 offset += clear_avx_size();
456 return offset;
457 }
458
459 // Indicate if the safepoint node needs the polling page as an input,
460 // it does if the polling page is more than disp32 away.
461 bool SafePointNode::needs_polling_address_input()
462 {
463 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
464 }
465
466 //
467 // Compute padding required for nodes which need alignment
468 //
469
470 // The address of the call instruction needs to be 4-byte aligned to
471 // ensure that it does not span a cache line so that it can be patched.
472 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
473 {
474 current_offset += clear_avx_size(); // skip vzeroupper
475 current_offset += 1; // skip call opcode byte
476 return align_up(current_offset, alignment_required()) - current_offset;
477 }
478
479 // The address of the call instruction needs to be 4-byte aligned to
480 // ensure that it does not span a cache line so that it can be patched.
481 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
482 {
483 current_offset += clear_avx_size(); // skip vzeroupper
484 current_offset += 11; // skip movq instruction + call opcode byte
485 return align_up(current_offset, alignment_required()) - current_offset;
486 }
487
488 // EMIT_RM()
489 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
490 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
491 cbuf.insts()->emit_int8(c);
492 }
493
494 // EMIT_CC()
495 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
496 unsigned char c = (unsigned char) (f1 | f2);
497 cbuf.insts()->emit_int8(c);
498 }
499
500 // EMIT_OPCODE()
501 void emit_opcode(CodeBuffer &cbuf, int code) {
502 cbuf.insts()->emit_int8((unsigned char) code);
503 }
504
505 // EMIT_OPCODE() w/ relocation information
506 void emit_opcode(CodeBuffer &cbuf,
507 int code, relocInfo::relocType reloc, int offset, int format)
508 {
509 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
510 emit_opcode(cbuf, code);
511 }
512
513 // EMIT_D8()
514 void emit_d8(CodeBuffer &cbuf, int d8) {
515 cbuf.insts()->emit_int8((unsigned char) d8);
516 }
517
518 // EMIT_D16()
519 void emit_d16(CodeBuffer &cbuf, int d16) {
520 cbuf.insts()->emit_int16(d16);
521 }
522
523 // EMIT_D32()
524 void emit_d32(CodeBuffer &cbuf, int d32) {
525 cbuf.insts()->emit_int32(d32);
526 }
527
528 // EMIT_D64()
529 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
530 cbuf.insts()->emit_int64(d64);
531 }
532
533 // emit 32 bit value and construct relocation entry from relocInfo::relocType
534 void emit_d32_reloc(CodeBuffer& cbuf,
535 int d32,
536 relocInfo::relocType reloc,
537 int format)
538 {
539 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
540 cbuf.relocate(cbuf.insts_mark(), reloc, format);
541 cbuf.insts()->emit_int32(d32);
542 }
543
544 // emit 32 bit value and construct relocation entry from RelocationHolder
545 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
546 #ifdef ASSERT
547 if (rspec.reloc()->type() == relocInfo::oop_type &&
548 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
549 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
550 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
551 }
552 #endif
553 cbuf.relocate(cbuf.insts_mark(), rspec, format);
554 cbuf.insts()->emit_int32(d32);
555 }
556
557 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
558 address next_ip = cbuf.insts_end() + 4;
559 emit_d32_reloc(cbuf, (int) (addr - next_ip),
560 external_word_Relocation::spec(addr),
561 RELOC_DISP32);
562 }
563
564
565 // emit 64 bit value and construct relocation entry from relocInfo::relocType
566 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
567 cbuf.relocate(cbuf.insts_mark(), reloc, format);
568 cbuf.insts()->emit_int64(d64);
569 }
570
571 // emit 64 bit value and construct relocation entry from RelocationHolder
572 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
573 #ifdef ASSERT
574 if (rspec.reloc()->type() == relocInfo::oop_type &&
575 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
576 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
577 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
578 }
579 #endif
580 cbuf.relocate(cbuf.insts_mark(), rspec, format);
581 cbuf.insts()->emit_int64(d64);
582 }
583
584 // Access stack slot for load or store
585 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
586 {
587 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
588 if (-0x80 <= disp && disp < 0x80) {
589 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
590 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
591 emit_d8(cbuf, disp); // Displacement // R/M byte
592 } else {
593 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
594 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
595 emit_d32(cbuf, disp); // Displacement // R/M byte
596 }
597 }
598
599 // rRegI ereg, memory mem) %{ // emit_reg_mem
600 void encode_RegMem(CodeBuffer &cbuf,
601 int reg,
602 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
603 {
604 assert(disp_reloc == relocInfo::none, "cannot have disp");
605 int regenc = reg & 7;
606 int baseenc = base & 7;
607 int indexenc = index & 7;
608
609 // There is no index & no scale, use form without SIB byte
610 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
611 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
612 if (disp == 0 && base != RBP_enc && base != R13_enc) {
613 emit_rm(cbuf, 0x0, regenc, baseenc); // *
614 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
615 // If 8-bit displacement, mode 0x1
616 emit_rm(cbuf, 0x1, regenc, baseenc); // *
617 emit_d8(cbuf, disp);
618 } else {
619 // If 32-bit displacement
620 if (base == -1) { // Special flag for absolute address
621 emit_rm(cbuf, 0x0, regenc, 0x5); // *
622 if (disp_reloc != relocInfo::none) {
623 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
624 } else {
625 emit_d32(cbuf, disp);
626 }
627 } else {
628 // Normal base + offset
629 emit_rm(cbuf, 0x2, regenc, baseenc); // *
630 if (disp_reloc != relocInfo::none) {
631 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
632 } else {
633 emit_d32(cbuf, disp);
634 }
635 }
636 }
637 } else {
638 // Else, encode with the SIB byte
639 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
640 if (disp == 0 && base != RBP_enc && base != R13_enc) {
641 // If no displacement
642 emit_rm(cbuf, 0x0, regenc, 0x4); // *
643 emit_rm(cbuf, scale, indexenc, baseenc);
644 } else {
645 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
646 // If 8-bit displacement, mode 0x1
647 emit_rm(cbuf, 0x1, regenc, 0x4); // *
648 emit_rm(cbuf, scale, indexenc, baseenc);
649 emit_d8(cbuf, disp);
650 } else {
651 // If 32-bit displacement
652 if (base == 0x04 ) {
653 emit_rm(cbuf, 0x2, regenc, 0x4);
654 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
655 } else {
656 emit_rm(cbuf, 0x2, regenc, 0x4);
657 emit_rm(cbuf, scale, indexenc, baseenc); // *
658 }
659 if (disp_reloc != relocInfo::none) {
660 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
661 } else {
662 emit_d32(cbuf, disp);
663 }
664 }
665 }
666 }
667 }
668
669 // This could be in MacroAssembler but it's fairly C2 specific
670 void emit_cmpfp_fixup(MacroAssembler& _masm) {
671 Label exit;
672 __ jccb(Assembler::noParity, exit);
673 __ pushf();
674 //
675 // comiss/ucomiss instructions set ZF,PF,CF flags and
676 // zero OF,AF,SF for NaN values.
677 // Fixup flags by zeroing ZF,PF so that compare of NaN
678 // values returns 'less than' result (CF is set).
679 // Leave the rest of flags unchanged.
680 //
681 // 7 6 5 4 3 2 1 0
682 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
683 // 0 0 1 0 1 0 1 1 (0x2B)
684 //
685 __ andq(Address(rsp, 0), 0xffffff2b);
686 __ popf();
687 __ bind(exit);
688 }
689
690 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
691 Label done;
692 __ movl(dst, -1);
693 __ jcc(Assembler::parity, done);
694 __ jcc(Assembler::below, done);
695 __ setb(Assembler::notEqual, dst);
696 __ movzbl(dst, dst);
697 __ bind(done);
698 }
699
700 // Math.min() # Math.max()
701 // --------------------------
702 // ucomis[s/d] #
703 // ja -> b # a
704 // jp -> NaN # NaN
705 // jb -> a # b
706 // je #
707 // |-jz -> a | b # a & b
708 // | -> a #
709 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
710 XMMRegister a, XMMRegister b,
711 XMMRegister xmmt, Register rt,
712 bool min, bool single) {
713
714 Label nan, zero, below, above, done;
715
716 if (single)
717 __ ucomiss(a, b);
718 else
719 __ ucomisd(a, b);
720
721 if (dst->encoding() != (min ? b : a)->encoding())
722 __ jccb(Assembler::above, above); // CF=0 & ZF=0
723 else
724 __ jccb(Assembler::above, done);
725
726 __ jccb(Assembler::parity, nan); // PF=1
727 __ jccb(Assembler::below, below); // CF=1
728
729 // equal
730 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
731 if (single) {
732 __ ucomiss(a, xmmt);
733 __ jccb(Assembler::equal, zero);
734
735 __ movflt(dst, a);
736 __ jmp(done);
737 }
738 else {
739 __ ucomisd(a, xmmt);
740 __ jccb(Assembler::equal, zero);
741
742 __ movdbl(dst, a);
743 __ jmp(done);
744 }
745
746 __ bind(zero);
747 if (min)
748 __ vpor(dst, a, b, Assembler::AVX_128bit);
749 else
750 __ vpand(dst, a, b, Assembler::AVX_128bit);
751
752 __ jmp(done);
753
754 __ bind(above);
755 if (single)
756 __ movflt(dst, min ? b : a);
757 else
758 __ movdbl(dst, min ? b : a);
759
760 __ jmp(done);
761
762 __ bind(nan);
763 if (single) {
764 __ movl(rt, 0x7fc00000); // Float.NaN
765 __ movdl(dst, rt);
766 }
767 else {
768 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
769 __ movdq(dst, rt);
770 }
771 __ jmp(done);
772
773 __ bind(below);
774 if (single)
775 __ movflt(dst, min ? a : b);
776 else
777 __ movdbl(dst, min ? a : b);
778
779 __ bind(done);
780 }
781
782 //=============================================================================
783 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
784
785 int Compile::ConstantTable::calculate_table_base_offset() const {
786 return 0; // absolute addressing, no offset
787 }
788
789 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
790 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
791 ShouldNotReachHere();
792 }
793
794 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
795 // Empty encoding
796 }
797
798 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
799 return 0;
800 }
801
802 #ifndef PRODUCT
803 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
804 st->print("# MachConstantBaseNode (empty encoding)");
805 }
806 #endif
807
808
809 //=============================================================================
810 #ifndef PRODUCT
811 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
812 Compile* C = ra_->C;
813
814 int framesize = C->frame_size_in_bytes();
815 int bangsize = C->bang_size_in_bytes();
816 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
817 // Remove wordSize for return addr which is already pushed.
818 framesize -= wordSize;
819
820 if (C->need_stack_bang(bangsize)) {
821 framesize -= wordSize;
822 st->print("# stack bang (%d bytes)", bangsize);
823 st->print("\n\t");
824 st->print("pushq rbp\t# Save rbp");
825 if (PreserveFramePointer) {
826 st->print("\n\t");
827 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
828 }
829 if (framesize) {
830 st->print("\n\t");
831 st->print("subq rsp, #%d\t# Create frame",framesize);
832 }
833 } else {
834 st->print("subq rsp, #%d\t# Create frame",framesize);
835 st->print("\n\t");
836 framesize -= wordSize;
837 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
838 if (PreserveFramePointer) {
839 st->print("\n\t");
840 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
841 if (framesize > 0) {
842 st->print("\n\t");
843 st->print("addq rbp, #%d", framesize);
844 }
845 }
846 }
847
848 if (VerifyStackAtCalls) {
849 st->print("\n\t");
850 framesize -= wordSize;
851 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
852 #ifdef ASSERT
853 st->print("\n\t");
854 st->print("# stack alignment check");
855 #endif
856 }
857 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
858 st->print("\n\t");
859 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
860 st->print("\n\t");
861 st->print("je fast_entry\t");
862 st->print("\n\t");
863 st->print("call #nmethod_entry_barrier_stub\t");
864 st->print("\n\tfast_entry:");
865 }
866 st->cr();
867 }
868 #endif
869
870 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
871 Compile* C = ra_->C;
872 MacroAssembler _masm(&cbuf);
873
874 int framesize = C->frame_size_in_bytes();
875 int bangsize = C->bang_size_in_bytes();
876
877 if (C->clinit_barrier_on_entry()) {
878 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
879 assert(C->method()->holder()->is_being_initialized() || C->method()->holder()->is_initialized(),
880 "initialization should have been started");
881
882 Label L_skip_barrier;
883 Register klass = rscratch1;
884
885 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
886 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
887
888 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
889
890 __ bind(L_skip_barrier);
891 }
892
893 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
894
895 C->set_frame_complete(cbuf.insts_size());
896
897 if (C->has_mach_constant_base_node()) {
898 // NOTE: We set the table base offset here because users might be
899 // emitted before MachConstantBaseNode.
900 Compile::ConstantTable& constant_table = C->constant_table();
901 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
902 }
903 }
904
905 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
906 {
907 return MachNode::size(ra_); // too many variables; just compute it
908 // the hard way
909 }
910
911 int MachPrologNode::reloc() const
912 {
913 return 0; // a large enough number
914 }
915
916 //=============================================================================
917 #ifndef PRODUCT
918 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
919 {
920 Compile* C = ra_->C;
921 if (generate_vzeroupper(C)) {
922 st->print("vzeroupper");
923 st->cr(); st->print("\t");
924 }
925
926 int framesize = C->frame_size_in_bytes();
927 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
928 // Remove word for return adr already pushed
929 // and RBP
930 framesize -= 2*wordSize;
931
932 if (framesize) {
933 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
934 st->print("\t");
935 }
936
937 st->print_cr("popq rbp");
938 if (do_polling() && C->is_method_compilation()) {
939 st->print("\t");
940 if (SafepointMechanism::uses_thread_local_poll()) {
941 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
942 "testl rax, [rscratch1]\t"
943 "# Safepoint: poll for GC");
944 } else if (Assembler::is_polling_page_far()) {
945 st->print_cr("movq rscratch1, #polling_page_address\n\t"
946 "testl rax, [rscratch1]\t"
947 "# Safepoint: poll for GC");
948 } else {
949 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
950 "# Safepoint: poll for GC");
951 }
952 }
953 }
954 #endif
955
956 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
957 {
958 Compile* C = ra_->C;
959 MacroAssembler _masm(&cbuf);
960
961 if (generate_vzeroupper(C)) {
962 // Clear upper bits of YMM registers when current compiled code uses
963 // wide vectors to avoid AVX <-> SSE transition penalty during call.
964 __ vzeroupper();
965 }
966
967 int framesize = C->frame_size_in_bytes();
968 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
969 // Remove word for return adr already pushed
970 // and RBP
971 framesize -= 2*wordSize;
972
973 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
974
975 if (framesize) {
976 emit_opcode(cbuf, Assembler::REX_W);
977 if (framesize < 0x80) {
978 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
979 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
980 emit_d8(cbuf, framesize);
981 } else {
982 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
983 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
984 emit_d32(cbuf, framesize);
985 }
986 }
987
988 // popq rbp
989 emit_opcode(cbuf, 0x58 | RBP_enc);
990
991 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
992 __ reserved_stack_check();
993 }
994
995 if (do_polling() && C->is_method_compilation()) {
996 MacroAssembler _masm(&cbuf);
997 if (SafepointMechanism::uses_thread_local_poll()) {
998 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
999 __ relocate(relocInfo::poll_return_type);
1000 __ testl(rax, Address(rscratch1, 0));
1001 } else {
1002 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1003 if (Assembler::is_polling_page_far()) {
1004 __ lea(rscratch1, polling_page);
1005 __ relocate(relocInfo::poll_return_type);
1006 __ testl(rax, Address(rscratch1, 0));
1007 } else {
1008 __ testl(rax, polling_page);
1009 }
1010 }
1011 }
1012 }
1013
1014 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1015 {
1016 return MachNode::size(ra_); // too many variables; just compute it
1017 // the hard way
1018 }
1019
1020 int MachEpilogNode::reloc() const
1021 {
1022 return 2; // a large enough number
1023 }
1024
1025 const Pipeline* MachEpilogNode::pipeline() const
1026 {
1027 return MachNode::pipeline_class();
1028 }
1029
1030 int MachEpilogNode::safepoint_offset() const
1031 {
1032 return 0;
1033 }
1034
1035 //=============================================================================
1036
1037 enum RC {
1038 rc_bad,
1039 rc_int,
1040 rc_float,
1041 rc_stack
1042 };
1043
1044 static enum RC rc_class(OptoReg::Name reg)
1045 {
1046 if( !OptoReg::is_valid(reg) ) return rc_bad;
1047
1048 if (OptoReg::is_stack(reg)) return rc_stack;
1049
1050 VMReg r = OptoReg::as_VMReg(reg);
1051
1052 if (r->is_Register()) return rc_int;
1053
1054 assert(r->is_XMMRegister(), "must be");
1055 return rc_float;
1056 }
1057
1058 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1059 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1060 int src_hi, int dst_hi, uint ireg, outputStream* st);
1061
1062 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1063 int stack_offset, int reg, uint ireg, outputStream* st);
1064
1065 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1066 int dst_offset, uint ireg, outputStream* st) {
1067 if (cbuf) {
1068 MacroAssembler _masm(cbuf);
1069 switch (ireg) {
1070 case Op_VecS:
1071 __ movq(Address(rsp, -8), rax);
1072 __ movl(rax, Address(rsp, src_offset));
1073 __ movl(Address(rsp, dst_offset), rax);
1074 __ movq(rax, Address(rsp, -8));
1075 break;
1076 case Op_VecD:
1077 __ pushq(Address(rsp, src_offset));
1078 __ popq (Address(rsp, dst_offset));
1079 break;
1080 case Op_VecX:
1081 __ pushq(Address(rsp, src_offset));
1082 __ popq (Address(rsp, dst_offset));
1083 __ pushq(Address(rsp, src_offset+8));
1084 __ popq (Address(rsp, dst_offset+8));
1085 break;
1086 case Op_VecY:
1087 __ vmovdqu(Address(rsp, -32), xmm0);
1088 __ vmovdqu(xmm0, Address(rsp, src_offset));
1089 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1090 __ vmovdqu(xmm0, Address(rsp, -32));
1091 break;
1092 case Op_VecZ:
1093 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1094 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1095 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1096 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1097 break;
1098 default:
1099 ShouldNotReachHere();
1100 }
1101 #ifndef PRODUCT
1102 } else {
1103 switch (ireg) {
1104 case Op_VecS:
1105 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1106 "movl rax, [rsp + #%d]\n\t"
1107 "movl [rsp + #%d], rax\n\t"
1108 "movq rax, [rsp - #8]",
1109 src_offset, dst_offset);
1110 break;
1111 case Op_VecD:
1112 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1113 "popq [rsp + #%d]",
1114 src_offset, dst_offset);
1115 break;
1116 case Op_VecX:
1117 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1118 "popq [rsp + #%d]\n\t"
1119 "pushq [rsp + #%d]\n\t"
1120 "popq [rsp + #%d]",
1121 src_offset, dst_offset, src_offset+8, dst_offset+8);
1122 break;
1123 case Op_VecY:
1124 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1125 "vmovdqu xmm0, [rsp + #%d]\n\t"
1126 "vmovdqu [rsp + #%d], xmm0\n\t"
1127 "vmovdqu xmm0, [rsp - #32]",
1128 src_offset, dst_offset);
1129 break;
1130 case Op_VecZ:
1131 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1132 "vmovdqu xmm0, [rsp + #%d]\n\t"
1133 "vmovdqu [rsp + #%d], xmm0\n\t"
1134 "vmovdqu xmm0, [rsp - #64]",
1135 src_offset, dst_offset);
1136 break;
1137 default:
1138 ShouldNotReachHere();
1139 }
1140 #endif
1141 }
1142 }
1143
1144 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1145 PhaseRegAlloc* ra_,
1146 bool do_size,
1147 outputStream* st) const {
1148 assert(cbuf != NULL || st != NULL, "sanity");
1149 // Get registers to move
1150 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1151 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1152 OptoReg::Name dst_second = ra_->get_reg_second(this);
1153 OptoReg::Name dst_first = ra_->get_reg_first(this);
1154
1155 enum RC src_second_rc = rc_class(src_second);
1156 enum RC src_first_rc = rc_class(src_first);
1157 enum RC dst_second_rc = rc_class(dst_second);
1158 enum RC dst_first_rc = rc_class(dst_first);
1159
1160 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1161 "must move at least 1 register" );
1162
1163 if (src_first == dst_first && src_second == dst_second) {
1164 // Self copy, no move
1165 return 0;
1166 }
1167 if (bottom_type()->isa_vect() != NULL) {
1168 uint ireg = ideal_reg();
1169 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1170 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1171 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1172 // mem -> mem
1173 int src_offset = ra_->reg2offset(src_first);
1174 int dst_offset = ra_->reg2offset(dst_first);
1175 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1176 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1177 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1178 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1179 int stack_offset = ra_->reg2offset(dst_first);
1180 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1181 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1182 int stack_offset = ra_->reg2offset(src_first);
1183 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1184 } else {
1185 ShouldNotReachHere();
1186 }
1187 return 0;
1188 }
1189 if (src_first_rc == rc_stack) {
1190 // mem ->
1191 if (dst_first_rc == rc_stack) {
1192 // mem -> mem
1193 assert(src_second != dst_first, "overlap");
1194 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1195 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1196 // 64-bit
1197 int src_offset = ra_->reg2offset(src_first);
1198 int dst_offset = ra_->reg2offset(dst_first);
1199 if (cbuf) {
1200 MacroAssembler _masm(cbuf);
1201 __ pushq(Address(rsp, src_offset));
1202 __ popq (Address(rsp, dst_offset));
1203 #ifndef PRODUCT
1204 } else {
1205 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1206 "popq [rsp + #%d]",
1207 src_offset, dst_offset);
1208 #endif
1209 }
1210 } else {
1211 // 32-bit
1212 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1213 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1214 // No pushl/popl, so:
1215 int src_offset = ra_->reg2offset(src_first);
1216 int dst_offset = ra_->reg2offset(dst_first);
1217 if (cbuf) {
1218 MacroAssembler _masm(cbuf);
1219 __ movq(Address(rsp, -8), rax);
1220 __ movl(rax, Address(rsp, src_offset));
1221 __ movl(Address(rsp, dst_offset), rax);
1222 __ movq(rax, Address(rsp, -8));
1223 #ifndef PRODUCT
1224 } else {
1225 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1226 "movl rax, [rsp + #%d]\n\t"
1227 "movl [rsp + #%d], rax\n\t"
1228 "movq rax, [rsp - #8]",
1229 src_offset, dst_offset);
1230 #endif
1231 }
1232 }
1233 return 0;
1234 } else if (dst_first_rc == rc_int) {
1235 // mem -> gpr
1236 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1237 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1238 // 64-bit
1239 int offset = ra_->reg2offset(src_first);
1240 if (cbuf) {
1241 MacroAssembler _masm(cbuf);
1242 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1243 #ifndef PRODUCT
1244 } else {
1245 st->print("movq %s, [rsp + #%d]\t# spill",
1246 Matcher::regName[dst_first],
1247 offset);
1248 #endif
1249 }
1250 } else {
1251 // 32-bit
1252 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1253 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1254 int offset = ra_->reg2offset(src_first);
1255 if (cbuf) {
1256 MacroAssembler _masm(cbuf);
1257 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1258 #ifndef PRODUCT
1259 } else {
1260 st->print("movl %s, [rsp + #%d]\t# spill",
1261 Matcher::regName[dst_first],
1262 offset);
1263 #endif
1264 }
1265 }
1266 return 0;
1267 } else if (dst_first_rc == rc_float) {
1268 // mem-> xmm
1269 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1270 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1271 // 64-bit
1272 int offset = ra_->reg2offset(src_first);
1273 if (cbuf) {
1274 MacroAssembler _masm(cbuf);
1275 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1276 #ifndef PRODUCT
1277 } else {
1278 st->print("%s %s, [rsp + #%d]\t# spill",
1279 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1280 Matcher::regName[dst_first],
1281 offset);
1282 #endif
1283 }
1284 } else {
1285 // 32-bit
1286 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1287 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1288 int offset = ra_->reg2offset(src_first);
1289 if (cbuf) {
1290 MacroAssembler _masm(cbuf);
1291 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1292 #ifndef PRODUCT
1293 } else {
1294 st->print("movss %s, [rsp + #%d]\t# spill",
1295 Matcher::regName[dst_first],
1296 offset);
1297 #endif
1298 }
1299 }
1300 return 0;
1301 }
1302 } else if (src_first_rc == rc_int) {
1303 // gpr ->
1304 if (dst_first_rc == rc_stack) {
1305 // gpr -> mem
1306 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1307 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1308 // 64-bit
1309 int offset = ra_->reg2offset(dst_first);
1310 if (cbuf) {
1311 MacroAssembler _masm(cbuf);
1312 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1313 #ifndef PRODUCT
1314 } else {
1315 st->print("movq [rsp + #%d], %s\t# spill",
1316 offset,
1317 Matcher::regName[src_first]);
1318 #endif
1319 }
1320 } else {
1321 // 32-bit
1322 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1323 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1324 int offset = ra_->reg2offset(dst_first);
1325 if (cbuf) {
1326 MacroAssembler _masm(cbuf);
1327 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1328 #ifndef PRODUCT
1329 } else {
1330 st->print("movl [rsp + #%d], %s\t# spill",
1331 offset,
1332 Matcher::regName[src_first]);
1333 #endif
1334 }
1335 }
1336 return 0;
1337 } else if (dst_first_rc == rc_int) {
1338 // gpr -> gpr
1339 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1340 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1341 // 64-bit
1342 if (cbuf) {
1343 MacroAssembler _masm(cbuf);
1344 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1345 as_Register(Matcher::_regEncode[src_first]));
1346 #ifndef PRODUCT
1347 } else {
1348 st->print("movq %s, %s\t# spill",
1349 Matcher::regName[dst_first],
1350 Matcher::regName[src_first]);
1351 #endif
1352 }
1353 return 0;
1354 } else {
1355 // 32-bit
1356 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1357 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1358 if (cbuf) {
1359 MacroAssembler _masm(cbuf);
1360 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1361 as_Register(Matcher::_regEncode[src_first]));
1362 #ifndef PRODUCT
1363 } else {
1364 st->print("movl %s, %s\t# spill",
1365 Matcher::regName[dst_first],
1366 Matcher::regName[src_first]);
1367 #endif
1368 }
1369 return 0;
1370 }
1371 } else if (dst_first_rc == rc_float) {
1372 // gpr -> xmm
1373 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1374 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1375 // 64-bit
1376 if (cbuf) {
1377 MacroAssembler _masm(cbuf);
1378 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1379 #ifndef PRODUCT
1380 } else {
1381 st->print("movdq %s, %s\t# spill",
1382 Matcher::regName[dst_first],
1383 Matcher::regName[src_first]);
1384 #endif
1385 }
1386 } else {
1387 // 32-bit
1388 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1389 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1390 if (cbuf) {
1391 MacroAssembler _masm(cbuf);
1392 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1393 #ifndef PRODUCT
1394 } else {
1395 st->print("movdl %s, %s\t# spill",
1396 Matcher::regName[dst_first],
1397 Matcher::regName[src_first]);
1398 #endif
1399 }
1400 }
1401 return 0;
1402 }
1403 } else if (src_first_rc == rc_float) {
1404 // xmm ->
1405 if (dst_first_rc == rc_stack) {
1406 // xmm -> mem
1407 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1408 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1409 // 64-bit
1410 int offset = ra_->reg2offset(dst_first);
1411 if (cbuf) {
1412 MacroAssembler _masm(cbuf);
1413 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1414 #ifndef PRODUCT
1415 } else {
1416 st->print("movsd [rsp + #%d], %s\t# spill",
1417 offset,
1418 Matcher::regName[src_first]);
1419 #endif
1420 }
1421 } else {
1422 // 32-bit
1423 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1424 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1425 int offset = ra_->reg2offset(dst_first);
1426 if (cbuf) {
1427 MacroAssembler _masm(cbuf);
1428 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1429 #ifndef PRODUCT
1430 } else {
1431 st->print("movss [rsp + #%d], %s\t# spill",
1432 offset,
1433 Matcher::regName[src_first]);
1434 #endif
1435 }
1436 }
1437 return 0;
1438 } else if (dst_first_rc == rc_int) {
1439 // xmm -> gpr
1440 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1441 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1442 // 64-bit
1443 if (cbuf) {
1444 MacroAssembler _masm(cbuf);
1445 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1446 #ifndef PRODUCT
1447 } else {
1448 st->print("movdq %s, %s\t# spill",
1449 Matcher::regName[dst_first],
1450 Matcher::regName[src_first]);
1451 #endif
1452 }
1453 } else {
1454 // 32-bit
1455 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1456 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1457 if (cbuf) {
1458 MacroAssembler _masm(cbuf);
1459 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1460 #ifndef PRODUCT
1461 } else {
1462 st->print("movdl %s, %s\t# spill",
1463 Matcher::regName[dst_first],
1464 Matcher::regName[src_first]);
1465 #endif
1466 }
1467 }
1468 return 0;
1469 } else if (dst_first_rc == rc_float) {
1470 // xmm -> xmm
1471 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1472 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1473 // 64-bit
1474 if (cbuf) {
1475 MacroAssembler _masm(cbuf);
1476 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1477 #ifndef PRODUCT
1478 } else {
1479 st->print("%s %s, %s\t# spill",
1480 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1481 Matcher::regName[dst_first],
1482 Matcher::regName[src_first]);
1483 #endif
1484 }
1485 } else {
1486 // 32-bit
1487 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1488 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1489 if (cbuf) {
1490 MacroAssembler _masm(cbuf);
1491 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1492 #ifndef PRODUCT
1493 } else {
1494 st->print("%s %s, %s\t# spill",
1495 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1496 Matcher::regName[dst_first],
1497 Matcher::regName[src_first]);
1498 #endif
1499 }
1500 }
1501 return 0;
1502 }
1503 }
1504
1505 assert(0," foo ");
1506 Unimplemented();
1507 return 0;
1508 }
1509
1510 #ifndef PRODUCT
1511 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1512 implementation(NULL, ra_, false, st);
1513 }
1514 #endif
1515
1516 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1517 implementation(&cbuf, ra_, false, NULL);
1518 }
1519
1520 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1521 return MachNode::size(ra_);
1522 }
1523
1524 //=============================================================================
1525 #ifndef PRODUCT
1526 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1527 {
1528 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1529 int reg = ra_->get_reg_first(this);
1530 st->print("leaq %s, [rsp + #%d]\t# box lock",
1531 Matcher::regName[reg], offset);
1532 }
1533 #endif
1534
1535 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1536 {
1537 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1538 int reg = ra_->get_encode(this);
1539 if (offset >= 0x80) {
1540 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1541 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1542 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1543 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1544 emit_d32(cbuf, offset);
1545 } else {
1546 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1547 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1548 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1549 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1550 emit_d8(cbuf, offset);
1551 }
1552 }
1553
1554 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1555 {
1556 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1557 return (offset < 0x80) ? 5 : 8; // REX
1558 }
1559
1560 //=============================================================================
1561 #ifndef PRODUCT
1562 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1563 {
1564 if (UseCompressedClassPointers) {
1565 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1566 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1567 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1568 } else {
1569 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1570 "# Inline cache check");
1571 }
1572 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1573 st->print_cr("\tnop\t# nops to align entry point");
1574 }
1575 #endif
1576
1577 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1578 {
1579 MacroAssembler masm(&cbuf);
1580 uint insts_size = cbuf.insts_size();
1581 if (UseCompressedClassPointers) {
1582 masm.load_klass(rscratch1, j_rarg0);
1583 masm.cmpptr(rax, rscratch1);
1584 } else {
1585 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1586 }
1587
1588 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1589
1590 /* WARNING these NOPs are critical so that verified entry point is properly
1591 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1592 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1593 if (OptoBreakpoint) {
1594 // Leave space for int3
1595 nops_cnt -= 1;
1596 }
1597 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1598 if (nops_cnt > 0)
1599 masm.nop(nops_cnt);
1600 }
1601
1602 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1603 {
1604 return MachNode::size(ra_); // too many variables; just compute it
1605 // the hard way
1606 }
1607
1608
1609 //=============================================================================
1610
1611 int Matcher::regnum_to_fpu_offset(int regnum)
1612 {
1613 return regnum - 32; // The FP registers are in the second chunk
1614 }
1615
1616 // This is UltraSparc specific, true just means we have fast l2f conversion
1617 const bool Matcher::convL2FSupported(void) {
1618 return true;
1619 }
1620
1621 // Is this branch offset short enough that a short branch can be used?
1622 //
1623 // NOTE: If the platform does not provide any short branch variants, then
1624 // this method should return false for offset 0.
1625 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1626 // The passed offset is relative to address of the branch.
1627 // On 86 a branch displacement is calculated relative to address
1628 // of a next instruction.
1629 offset -= br_size;
1630
1631 // the short version of jmpConUCF2 contains multiple branches,
1632 // making the reach slightly less
1633 if (rule == jmpConUCF2_rule)
1634 return (-126 <= offset && offset <= 125);
1635 return (-128 <= offset && offset <= 127);
1636 }
1637
1638 const bool Matcher::isSimpleConstant64(jlong value) {
1639 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1640 //return value == (int) value; // Cf. storeImmL and immL32.
1641
1642 // Probably always true, even if a temp register is required.
1643 return true;
1644 }
1645
1646 // The ecx parameter to rep stosq for the ClearArray node is in words.
1647 const bool Matcher::init_array_count_is_in_bytes = false;
1648
1649 // No additional cost for CMOVL.
1650 const int Matcher::long_cmove_cost() { return 0; }
1651
1652 // No CMOVF/CMOVD with SSE2
1653 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1654
1655 // Does the CPU require late expand (see block.cpp for description of late expand)?
1656 const bool Matcher::require_postalloc_expand = false;
1657
1658 // Do we need to mask the count passed to shift instructions or does
1659 // the cpu only look at the lower 5/6 bits anyway?
1660 const bool Matcher::need_masked_shift_count = false;
1661
1662 bool Matcher::narrow_oop_use_complex_address() {
1663 assert(UseCompressedOops, "only for compressed oops code");
1664 return (LogMinObjAlignmentInBytes <= 3);
1665 }
1666
1667 bool Matcher::narrow_klass_use_complex_address() {
1668 assert(UseCompressedClassPointers, "only for compressed klass code");
1669 return (LogKlassAlignmentInBytes <= 3);
1670 }
1671
1672 bool Matcher::const_oop_prefer_decode() {
1673 // Prefer ConN+DecodeN over ConP.
1674 return true;
1675 }
1676
1677 bool Matcher::const_klass_prefer_decode() {
1678 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1679 // or condisider the following:
1680 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1681 //return CompressedKlassPointers::base() == NULL;
1682 return true;
1683 }
1684
1685 // Is it better to copy float constants, or load them directly from
1686 // memory? Intel can load a float constant from a direct address,
1687 // requiring no extra registers. Most RISCs will have to materialize
1688 // an address into a register first, so they would do better to copy
1689 // the constant from stack.
1690 const bool Matcher::rematerialize_float_constants = true; // XXX
1691
1692 // If CPU can load and store mis-aligned doubles directly then no
1693 // fixup is needed. Else we split the double into 2 integer pieces
1694 // and move it piece-by-piece. Only happens when passing doubles into
1695 // C code as the Java calling convention forces doubles to be aligned.
1696 const bool Matcher::misaligned_doubles_ok = true;
1697
1698 // No-op on amd64
1699 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1700
1701 // Advertise here if the CPU requires explicit rounding operations to
1702 // implement the UseStrictFP mode.
1703 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1704
1705 // Are floats conerted to double when stored to stack during deoptimization?
1706 // On x64 it is stored without convertion so we can use normal access.
1707 bool Matcher::float_in_double() { return false; }
1708
1709 // Do ints take an entire long register or just half?
1710 const bool Matcher::int_in_long = true;
1711
1712 // Return whether or not this register is ever used as an argument.
1713 // This function is used on startup to build the trampoline stubs in
1714 // generateOptoStub. Registers not mentioned will be killed by the VM
1715 // call in the trampoline, and arguments in those registers not be
1716 // available to the callee.
1717 bool Matcher::can_be_java_arg(int reg)
1718 {
1719 return
1720 reg == RDI_num || reg == RDI_H_num ||
1721 reg == RSI_num || reg == RSI_H_num ||
1722 reg == RDX_num || reg == RDX_H_num ||
1723 reg == RCX_num || reg == RCX_H_num ||
1724 reg == R8_num || reg == R8_H_num ||
1725 reg == R9_num || reg == R9_H_num ||
1726 reg == R12_num || reg == R12_H_num ||
1727 reg == XMM0_num || reg == XMM0b_num ||
1728 reg == XMM1_num || reg == XMM1b_num ||
1729 reg == XMM2_num || reg == XMM2b_num ||
1730 reg == XMM3_num || reg == XMM3b_num ||
1731 reg == XMM4_num || reg == XMM4b_num ||
1732 reg == XMM5_num || reg == XMM5b_num ||
1733 reg == XMM6_num || reg == XMM6b_num ||
1734 reg == XMM7_num || reg == XMM7b_num;
1735 }
1736
1737 bool Matcher::is_spillable_arg(int reg)
1738 {
1739 return can_be_java_arg(reg);
1740 }
1741
1742 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1743 // In 64 bit mode a code which use multiply when
1744 // devisor is constant is faster than hardware
1745 // DIV instruction (it uses MulHiL).
1746 return false;
1747 }
1748
1749 // Register for DIVI projection of divmodI
1750 RegMask Matcher::divI_proj_mask() {
1751 return INT_RAX_REG_mask();
1752 }
1753
1754 // Register for MODI projection of divmodI
1755 RegMask Matcher::modI_proj_mask() {
1756 return INT_RDX_REG_mask();
1757 }
1758
1759 // Register for DIVL projection of divmodL
1760 RegMask Matcher::divL_proj_mask() {
1761 return LONG_RAX_REG_mask();
1762 }
1763
1764 // Register for MODL projection of divmodL
1765 RegMask Matcher::modL_proj_mask() {
1766 return LONG_RDX_REG_mask();
1767 }
1768
1769 // Register for saving SP into on method handle invokes. Not used on x86_64.
1770 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1771 return NO_REG_mask();
1772 }
1773
1774 %}
1775
1776 //----------ENCODING BLOCK-----------------------------------------------------
1777 // This block specifies the encoding classes used by the compiler to
1778 // output byte streams. Encoding classes are parameterized macros
1779 // used by Machine Instruction Nodes in order to generate the bit
1780 // encoding of the instruction. Operands specify their base encoding
1781 // interface with the interface keyword. There are currently
1782 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1783 // COND_INTER. REG_INTER causes an operand to generate a function
1784 // which returns its register number when queried. CONST_INTER causes
1785 // an operand to generate a function which returns the value of the
1786 // constant when queried. MEMORY_INTER causes an operand to generate
1787 // four functions which return the Base Register, the Index Register,
1788 // the Scale Value, and the Offset Value of the operand when queried.
1789 // COND_INTER causes an operand to generate six functions which return
1790 // the encoding code (ie - encoding bits for the instruction)
1791 // associated with each basic boolean condition for a conditional
1792 // instruction.
1793 //
1794 // Instructions specify two basic values for encoding. Again, a
1795 // function is available to check if the constant displacement is an
1796 // oop. They use the ins_encode keyword to specify their encoding
1797 // classes (which must be a sequence of enc_class names, and their
1798 // parameters, specified in the encoding block), and they use the
1799 // opcode keyword to specify, in order, their primary, secondary, and
1800 // tertiary opcode. Only the opcode sections which a particular
1801 // instruction needs for encoding need to be specified.
1802 encode %{
1803 // Build emit functions for each basic byte or larger field in the
1804 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1805 // from C++ code in the enc_class source block. Emit functions will
1806 // live in the main source block for now. In future, we can
1807 // generalize this by adding a syntax that specifies the sizes of
1808 // fields in an order, so that the adlc can build the emit functions
1809 // automagically
1810
1811 // Emit primary opcode
1812 enc_class OpcP
1813 %{
1814 emit_opcode(cbuf, $primary);
1815 %}
1816
1817 // Emit secondary opcode
1818 enc_class OpcS
1819 %{
1820 emit_opcode(cbuf, $secondary);
1821 %}
1822
1823 // Emit tertiary opcode
1824 enc_class OpcT
1825 %{
1826 emit_opcode(cbuf, $tertiary);
1827 %}
1828
1829 // Emit opcode directly
1830 enc_class Opcode(immI d8)
1831 %{
1832 emit_opcode(cbuf, $d8$$constant);
1833 %}
1834
1835 // Emit size prefix
1836 enc_class SizePrefix
1837 %{
1838 emit_opcode(cbuf, 0x66);
1839 %}
1840
1841 enc_class reg(rRegI reg)
1842 %{
1843 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1844 %}
1845
1846 enc_class reg_reg(rRegI dst, rRegI src)
1847 %{
1848 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1849 %}
1850
1851 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1852 %{
1853 emit_opcode(cbuf, $opcode$$constant);
1854 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1855 %}
1856
1857 enc_class cdql_enc(no_rax_rdx_RegI div)
1858 %{
1859 // Full implementation of Java idiv and irem; checks for
1860 // special case as described in JVM spec., p.243 & p.271.
1861 //
1862 // normal case special case
1863 //
1864 // input : rax: dividend min_int
1865 // reg: divisor -1
1866 //
1867 // output: rax: quotient (= rax idiv reg) min_int
1868 // rdx: remainder (= rax irem reg) 0
1869 //
1870 // Code sequnce:
1871 //
1872 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1873 // 5: 75 07/08 jne e <normal>
1874 // 7: 33 d2 xor %edx,%edx
1875 // [div >= 8 -> offset + 1]
1876 // [REX_B]
1877 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1878 // c: 74 03/04 je 11 <done>
1879 // 000000000000000e <normal>:
1880 // e: 99 cltd
1881 // [div >= 8 -> offset + 1]
1882 // [REX_B]
1883 // f: f7 f9 idiv $div
1884 // 0000000000000011 <done>:
1885
1886 // cmp $0x80000000,%eax
1887 emit_opcode(cbuf, 0x3d);
1888 emit_d8(cbuf, 0x00);
1889 emit_d8(cbuf, 0x00);
1890 emit_d8(cbuf, 0x00);
1891 emit_d8(cbuf, 0x80);
1892
1893 // jne e <normal>
1894 emit_opcode(cbuf, 0x75);
1895 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1896
1897 // xor %edx,%edx
1898 emit_opcode(cbuf, 0x33);
1899 emit_d8(cbuf, 0xD2);
1900
1901 // cmp $0xffffffffffffffff,%ecx
1902 if ($div$$reg >= 8) {
1903 emit_opcode(cbuf, Assembler::REX_B);
1904 }
1905 emit_opcode(cbuf, 0x83);
1906 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1907 emit_d8(cbuf, 0xFF);
1908
1909 // je 11 <done>
1910 emit_opcode(cbuf, 0x74);
1911 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1912
1913 // <normal>
1914 // cltd
1915 emit_opcode(cbuf, 0x99);
1916
1917 // idivl (note: must be emitted by the user of this rule)
1918 // <done>
1919 %}
1920
1921 enc_class cdqq_enc(no_rax_rdx_RegL div)
1922 %{
1923 // Full implementation of Java ldiv and lrem; checks for
1924 // special case as described in JVM spec., p.243 & p.271.
1925 //
1926 // normal case special case
1927 //
1928 // input : rax: dividend min_long
1929 // reg: divisor -1
1930 //
1931 // output: rax: quotient (= rax idiv reg) min_long
1932 // rdx: remainder (= rax irem reg) 0
1933 //
1934 // Code sequnce:
1935 //
1936 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1937 // 7: 00 00 80
1938 // a: 48 39 d0 cmp %rdx,%rax
1939 // d: 75 08 jne 17 <normal>
1940 // f: 33 d2 xor %edx,%edx
1941 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1942 // 15: 74 05 je 1c <done>
1943 // 0000000000000017 <normal>:
1944 // 17: 48 99 cqto
1945 // 19: 48 f7 f9 idiv $div
1946 // 000000000000001c <done>:
1947
1948 // mov $0x8000000000000000,%rdx
1949 emit_opcode(cbuf, Assembler::REX_W);
1950 emit_opcode(cbuf, 0xBA);
1951 emit_d8(cbuf, 0x00);
1952 emit_d8(cbuf, 0x00);
1953 emit_d8(cbuf, 0x00);
1954 emit_d8(cbuf, 0x00);
1955 emit_d8(cbuf, 0x00);
1956 emit_d8(cbuf, 0x00);
1957 emit_d8(cbuf, 0x00);
1958 emit_d8(cbuf, 0x80);
1959
1960 // cmp %rdx,%rax
1961 emit_opcode(cbuf, Assembler::REX_W);
1962 emit_opcode(cbuf, 0x39);
1963 emit_d8(cbuf, 0xD0);
1964
1965 // jne 17 <normal>
1966 emit_opcode(cbuf, 0x75);
1967 emit_d8(cbuf, 0x08);
1968
1969 // xor %edx,%edx
1970 emit_opcode(cbuf, 0x33);
1971 emit_d8(cbuf, 0xD2);
1972
1973 // cmp $0xffffffffffffffff,$div
1974 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1975 emit_opcode(cbuf, 0x83);
1976 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1977 emit_d8(cbuf, 0xFF);
1978
1979 // je 1e <done>
1980 emit_opcode(cbuf, 0x74);
1981 emit_d8(cbuf, 0x05);
1982
1983 // <normal>
1984 // cqto
1985 emit_opcode(cbuf, Assembler::REX_W);
1986 emit_opcode(cbuf, 0x99);
1987
1988 // idivq (note: must be emitted by the user of this rule)
1989 // <done>
1990 %}
1991
1992 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1993 enc_class OpcSE(immI imm)
1994 %{
1995 // Emit primary opcode and set sign-extend bit
1996 // Check for 8-bit immediate, and set sign extend bit in opcode
1997 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1998 emit_opcode(cbuf, $primary | 0x02);
1999 } else {
2000 // 32-bit immediate
2001 emit_opcode(cbuf, $primary);
2002 }
2003 %}
2004
2005 enc_class OpcSErm(rRegI dst, immI imm)
2006 %{
2007 // OpcSEr/m
2008 int dstenc = $dst$$reg;
2009 if (dstenc >= 8) {
2010 emit_opcode(cbuf, Assembler::REX_B);
2011 dstenc -= 8;
2012 }
2013 // Emit primary opcode and set sign-extend bit
2014 // Check for 8-bit immediate, and set sign extend bit in opcode
2015 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2016 emit_opcode(cbuf, $primary | 0x02);
2017 } else {
2018 // 32-bit immediate
2019 emit_opcode(cbuf, $primary);
2020 }
2021 // Emit r/m byte with secondary opcode, after primary opcode.
2022 emit_rm(cbuf, 0x3, $secondary, dstenc);
2023 %}
2024
2025 enc_class OpcSErm_wide(rRegL dst, immI imm)
2026 %{
2027 // OpcSEr/m
2028 int dstenc = $dst$$reg;
2029 if (dstenc < 8) {
2030 emit_opcode(cbuf, Assembler::REX_W);
2031 } else {
2032 emit_opcode(cbuf, Assembler::REX_WB);
2033 dstenc -= 8;
2034 }
2035 // Emit primary opcode and set sign-extend bit
2036 // Check for 8-bit immediate, and set sign extend bit in opcode
2037 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2038 emit_opcode(cbuf, $primary | 0x02);
2039 } else {
2040 // 32-bit immediate
2041 emit_opcode(cbuf, $primary);
2042 }
2043 // Emit r/m byte with secondary opcode, after primary opcode.
2044 emit_rm(cbuf, 0x3, $secondary, dstenc);
2045 %}
2046
2047 enc_class Con8or32(immI imm)
2048 %{
2049 // Check for 8-bit immediate, and set sign extend bit in opcode
2050 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2051 $$$emit8$imm$$constant;
2052 } else {
2053 // 32-bit immediate
2054 $$$emit32$imm$$constant;
2055 }
2056 %}
2057
2058 enc_class opc2_reg(rRegI dst)
2059 %{
2060 // BSWAP
2061 emit_cc(cbuf, $secondary, $dst$$reg);
2062 %}
2063
2064 enc_class opc3_reg(rRegI dst)
2065 %{
2066 // BSWAP
2067 emit_cc(cbuf, $tertiary, $dst$$reg);
2068 %}
2069
2070 enc_class reg_opc(rRegI div)
2071 %{
2072 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2073 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2074 %}
2075
2076 enc_class enc_cmov(cmpOp cop)
2077 %{
2078 // CMOV
2079 $$$emit8$primary;
2080 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2081 %}
2082
2083 enc_class enc_PartialSubtypeCheck()
2084 %{
2085 Register Rrdi = as_Register(RDI_enc); // result register
2086 Register Rrax = as_Register(RAX_enc); // super class
2087 Register Rrcx = as_Register(RCX_enc); // killed
2088 Register Rrsi = as_Register(RSI_enc); // sub class
2089 Label miss;
2090 const bool set_cond_codes = true;
2091
2092 MacroAssembler _masm(&cbuf);
2093 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2094 NULL, &miss,
2095 /*set_cond_codes:*/ true);
2096 if ($primary) {
2097 __ xorptr(Rrdi, Rrdi);
2098 }
2099 __ bind(miss);
2100 %}
2101
2102 enc_class clear_avx %{
2103 debug_only(int off0 = cbuf.insts_size());
2104 if (generate_vzeroupper(Compile::current())) {
2105 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2106 // Clear upper bits of YMM registers when current compiled code uses
2107 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2108 MacroAssembler _masm(&cbuf);
2109 __ vzeroupper();
2110 }
2111 debug_only(int off1 = cbuf.insts_size());
2112 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2113 %}
2114
2115 enc_class Java_To_Runtime(method meth) %{
2116 // No relocation needed
2117 MacroAssembler _masm(&cbuf);
2118 __ mov64(r10, (int64_t) $meth$$method);
2119 __ call(r10);
2120 %}
2121
2122 enc_class Java_To_Interpreter(method meth)
2123 %{
2124 // CALL Java_To_Interpreter
2125 // This is the instruction starting address for relocation info.
2126 cbuf.set_insts_mark();
2127 $$$emit8$primary;
2128 // CALL directly to the runtime
2129 emit_d32_reloc(cbuf,
2130 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2131 runtime_call_Relocation::spec(),
2132 RELOC_DISP32);
2133 %}
2134
2135 enc_class Java_Static_Call(method meth)
2136 %{
2137 // JAVA STATIC CALL
2138 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2139 // determine who we intended to call.
2140 cbuf.set_insts_mark();
2141 $$$emit8$primary;
2142
2143 if (!_method) {
2144 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2145 runtime_call_Relocation::spec(),
2146 RELOC_DISP32);
2147 } else {
2148 int method_index = resolved_method_index(cbuf);
2149 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2150 : static_call_Relocation::spec(method_index);
2151 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2152 rspec, RELOC_DISP32);
2153 // Emit stubs for static call.
2154 address mark = cbuf.insts_mark();
2155 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2156 if (stub == NULL) {
2157 ciEnv::current()->record_failure("CodeCache is full");
2158 return;
2159 }
2160 #if INCLUDE_AOT
2161 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2162 #endif
2163 }
2164 %}
2165
2166 enc_class Java_Dynamic_Call(method meth) %{
2167 MacroAssembler _masm(&cbuf);
2168 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2169 %}
2170
2171 enc_class Java_Compiled_Call(method meth)
2172 %{
2173 // JAVA COMPILED CALL
2174 int disp = in_bytes(Method:: from_compiled_offset());
2175
2176 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2177 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2178
2179 // callq *disp(%rax)
2180 cbuf.set_insts_mark();
2181 $$$emit8$primary;
2182 if (disp < 0x80) {
2183 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2184 emit_d8(cbuf, disp); // Displacement
2185 } else {
2186 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2187 emit_d32(cbuf, disp); // Displacement
2188 }
2189 %}
2190
2191 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2192 %{
2193 // SAL, SAR, SHR
2194 int dstenc = $dst$$reg;
2195 if (dstenc >= 8) {
2196 emit_opcode(cbuf, Assembler::REX_B);
2197 dstenc -= 8;
2198 }
2199 $$$emit8$primary;
2200 emit_rm(cbuf, 0x3, $secondary, dstenc);
2201 $$$emit8$shift$$constant;
2202 %}
2203
2204 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2205 %{
2206 // SAL, SAR, SHR
2207 int dstenc = $dst$$reg;
2208 if (dstenc < 8) {
2209 emit_opcode(cbuf, Assembler::REX_W);
2210 } else {
2211 emit_opcode(cbuf, Assembler::REX_WB);
2212 dstenc -= 8;
2213 }
2214 $$$emit8$primary;
2215 emit_rm(cbuf, 0x3, $secondary, dstenc);
2216 $$$emit8$shift$$constant;
2217 %}
2218
2219 enc_class load_immI(rRegI dst, immI src)
2220 %{
2221 int dstenc = $dst$$reg;
2222 if (dstenc >= 8) {
2223 emit_opcode(cbuf, Assembler::REX_B);
2224 dstenc -= 8;
2225 }
2226 emit_opcode(cbuf, 0xB8 | dstenc);
2227 $$$emit32$src$$constant;
2228 %}
2229
2230 enc_class load_immL(rRegL dst, immL src)
2231 %{
2232 int dstenc = $dst$$reg;
2233 if (dstenc < 8) {
2234 emit_opcode(cbuf, Assembler::REX_W);
2235 } else {
2236 emit_opcode(cbuf, Assembler::REX_WB);
2237 dstenc -= 8;
2238 }
2239 emit_opcode(cbuf, 0xB8 | dstenc);
2240 emit_d64(cbuf, $src$$constant);
2241 %}
2242
2243 enc_class load_immUL32(rRegL dst, immUL32 src)
2244 %{
2245 // same as load_immI, but this time we care about zeroes in the high word
2246 int dstenc = $dst$$reg;
2247 if (dstenc >= 8) {
2248 emit_opcode(cbuf, Assembler::REX_B);
2249 dstenc -= 8;
2250 }
2251 emit_opcode(cbuf, 0xB8 | dstenc);
2252 $$$emit32$src$$constant;
2253 %}
2254
2255 enc_class load_immL32(rRegL dst, immL32 src)
2256 %{
2257 int dstenc = $dst$$reg;
2258 if (dstenc < 8) {
2259 emit_opcode(cbuf, Assembler::REX_W);
2260 } else {
2261 emit_opcode(cbuf, Assembler::REX_WB);
2262 dstenc -= 8;
2263 }
2264 emit_opcode(cbuf, 0xC7);
2265 emit_rm(cbuf, 0x03, 0x00, dstenc);
2266 $$$emit32$src$$constant;
2267 %}
2268
2269 enc_class load_immP31(rRegP dst, immP32 src)
2270 %{
2271 // same as load_immI, but this time we care about zeroes in the high word
2272 int dstenc = $dst$$reg;
2273 if (dstenc >= 8) {
2274 emit_opcode(cbuf, Assembler::REX_B);
2275 dstenc -= 8;
2276 }
2277 emit_opcode(cbuf, 0xB8 | dstenc);
2278 $$$emit32$src$$constant;
2279 %}
2280
2281 enc_class load_immP(rRegP dst, immP src)
2282 %{
2283 int dstenc = $dst$$reg;
2284 if (dstenc < 8) {
2285 emit_opcode(cbuf, Assembler::REX_W);
2286 } else {
2287 emit_opcode(cbuf, Assembler::REX_WB);
2288 dstenc -= 8;
2289 }
2290 emit_opcode(cbuf, 0xB8 | dstenc);
2291 // This next line should be generated from ADLC
2292 if ($src->constant_reloc() != relocInfo::none) {
2293 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2294 } else {
2295 emit_d64(cbuf, $src$$constant);
2296 }
2297 %}
2298
2299 enc_class Con32(immI src)
2300 %{
2301 // Output immediate
2302 $$$emit32$src$$constant;
2303 %}
2304
2305 enc_class Con32F_as_bits(immF src)
2306 %{
2307 // Output Float immediate bits
2308 jfloat jf = $src$$constant;
2309 jint jf_as_bits = jint_cast(jf);
2310 emit_d32(cbuf, jf_as_bits);
2311 %}
2312
2313 enc_class Con16(immI src)
2314 %{
2315 // Output immediate
2316 $$$emit16$src$$constant;
2317 %}
2318
2319 // How is this different from Con32??? XXX
2320 enc_class Con_d32(immI src)
2321 %{
2322 emit_d32(cbuf,$src$$constant);
2323 %}
2324
2325 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2326 // Output immediate memory reference
2327 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2328 emit_d32(cbuf, 0x00);
2329 %}
2330
2331 enc_class lock_prefix()
2332 %{
2333 emit_opcode(cbuf, 0xF0); // lock
2334 %}
2335
2336 enc_class REX_mem(memory mem)
2337 %{
2338 if ($mem$$base >= 8) {
2339 if ($mem$$index < 8) {
2340 emit_opcode(cbuf, Assembler::REX_B);
2341 } else {
2342 emit_opcode(cbuf, Assembler::REX_XB);
2343 }
2344 } else {
2345 if ($mem$$index >= 8) {
2346 emit_opcode(cbuf, Assembler::REX_X);
2347 }
2348 }
2349 %}
2350
2351 enc_class REX_mem_wide(memory mem)
2352 %{
2353 if ($mem$$base >= 8) {
2354 if ($mem$$index < 8) {
2355 emit_opcode(cbuf, Assembler::REX_WB);
2356 } else {
2357 emit_opcode(cbuf, Assembler::REX_WXB);
2358 }
2359 } else {
2360 if ($mem$$index < 8) {
2361 emit_opcode(cbuf, Assembler::REX_W);
2362 } else {
2363 emit_opcode(cbuf, Assembler::REX_WX);
2364 }
2365 }
2366 %}
2367
2368 // for byte regs
2369 enc_class REX_breg(rRegI reg)
2370 %{
2371 if ($reg$$reg >= 4) {
2372 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2373 }
2374 %}
2375
2376 // for byte regs
2377 enc_class REX_reg_breg(rRegI dst, rRegI src)
2378 %{
2379 if ($dst$$reg < 8) {
2380 if ($src$$reg >= 4) {
2381 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2382 }
2383 } else {
2384 if ($src$$reg < 8) {
2385 emit_opcode(cbuf, Assembler::REX_R);
2386 } else {
2387 emit_opcode(cbuf, Assembler::REX_RB);
2388 }
2389 }
2390 %}
2391
2392 // for byte regs
2393 enc_class REX_breg_mem(rRegI reg, memory mem)
2394 %{
2395 if ($reg$$reg < 8) {
2396 if ($mem$$base < 8) {
2397 if ($mem$$index >= 8) {
2398 emit_opcode(cbuf, Assembler::REX_X);
2399 } else if ($reg$$reg >= 4) {
2400 emit_opcode(cbuf, Assembler::REX);
2401 }
2402 } else {
2403 if ($mem$$index < 8) {
2404 emit_opcode(cbuf, Assembler::REX_B);
2405 } else {
2406 emit_opcode(cbuf, Assembler::REX_XB);
2407 }
2408 }
2409 } else {
2410 if ($mem$$base < 8) {
2411 if ($mem$$index < 8) {
2412 emit_opcode(cbuf, Assembler::REX_R);
2413 } else {
2414 emit_opcode(cbuf, Assembler::REX_RX);
2415 }
2416 } else {
2417 if ($mem$$index < 8) {
2418 emit_opcode(cbuf, Assembler::REX_RB);
2419 } else {
2420 emit_opcode(cbuf, Assembler::REX_RXB);
2421 }
2422 }
2423 }
2424 %}
2425
2426 enc_class REX_reg(rRegI reg)
2427 %{
2428 if ($reg$$reg >= 8) {
2429 emit_opcode(cbuf, Assembler::REX_B);
2430 }
2431 %}
2432
2433 enc_class REX_reg_wide(rRegI reg)
2434 %{
2435 if ($reg$$reg < 8) {
2436 emit_opcode(cbuf, Assembler::REX_W);
2437 } else {
2438 emit_opcode(cbuf, Assembler::REX_WB);
2439 }
2440 %}
2441
2442 enc_class REX_reg_reg(rRegI dst, rRegI src)
2443 %{
2444 if ($dst$$reg < 8) {
2445 if ($src$$reg >= 8) {
2446 emit_opcode(cbuf, Assembler::REX_B);
2447 }
2448 } else {
2449 if ($src$$reg < 8) {
2450 emit_opcode(cbuf, Assembler::REX_R);
2451 } else {
2452 emit_opcode(cbuf, Assembler::REX_RB);
2453 }
2454 }
2455 %}
2456
2457 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2458 %{
2459 if ($dst$$reg < 8) {
2460 if ($src$$reg < 8) {
2461 emit_opcode(cbuf, Assembler::REX_W);
2462 } else {
2463 emit_opcode(cbuf, Assembler::REX_WB);
2464 }
2465 } else {
2466 if ($src$$reg < 8) {
2467 emit_opcode(cbuf, Assembler::REX_WR);
2468 } else {
2469 emit_opcode(cbuf, Assembler::REX_WRB);
2470 }
2471 }
2472 %}
2473
2474 enc_class REX_reg_mem(rRegI reg, memory mem)
2475 %{
2476 if ($reg$$reg < 8) {
2477 if ($mem$$base < 8) {
2478 if ($mem$$index >= 8) {
2479 emit_opcode(cbuf, Assembler::REX_X);
2480 }
2481 } else {
2482 if ($mem$$index < 8) {
2483 emit_opcode(cbuf, Assembler::REX_B);
2484 } else {
2485 emit_opcode(cbuf, Assembler::REX_XB);
2486 }
2487 }
2488 } else {
2489 if ($mem$$base < 8) {
2490 if ($mem$$index < 8) {
2491 emit_opcode(cbuf, Assembler::REX_R);
2492 } else {
2493 emit_opcode(cbuf, Assembler::REX_RX);
2494 }
2495 } else {
2496 if ($mem$$index < 8) {
2497 emit_opcode(cbuf, Assembler::REX_RB);
2498 } else {
2499 emit_opcode(cbuf, Assembler::REX_RXB);
2500 }
2501 }
2502 }
2503 %}
2504
2505 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2506 %{
2507 if ($reg$$reg < 8) {
2508 if ($mem$$base < 8) {
2509 if ($mem$$index < 8) {
2510 emit_opcode(cbuf, Assembler::REX_W);
2511 } else {
2512 emit_opcode(cbuf, Assembler::REX_WX);
2513 }
2514 } else {
2515 if ($mem$$index < 8) {
2516 emit_opcode(cbuf, Assembler::REX_WB);
2517 } else {
2518 emit_opcode(cbuf, Assembler::REX_WXB);
2519 }
2520 }
2521 } else {
2522 if ($mem$$base < 8) {
2523 if ($mem$$index < 8) {
2524 emit_opcode(cbuf, Assembler::REX_WR);
2525 } else {
2526 emit_opcode(cbuf, Assembler::REX_WRX);
2527 }
2528 } else {
2529 if ($mem$$index < 8) {
2530 emit_opcode(cbuf, Assembler::REX_WRB);
2531 } else {
2532 emit_opcode(cbuf, Assembler::REX_WRXB);
2533 }
2534 }
2535 }
2536 %}
2537
2538 enc_class reg_mem(rRegI ereg, memory mem)
2539 %{
2540 // High registers handle in encode_RegMem
2541 int reg = $ereg$$reg;
2542 int base = $mem$$base;
2543 int index = $mem$$index;
2544 int scale = $mem$$scale;
2545 int disp = $mem$$disp;
2546 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2547
2548 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2549 %}
2550
2551 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2552 %{
2553 int rm_byte_opcode = $rm_opcode$$constant;
2554
2555 // High registers handle in encode_RegMem
2556 int base = $mem$$base;
2557 int index = $mem$$index;
2558 int scale = $mem$$scale;
2559 int displace = $mem$$disp;
2560
2561 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2562 // working with static
2563 // globals
2564 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2565 disp_reloc);
2566 %}
2567
2568 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2569 %{
2570 int reg_encoding = $dst$$reg;
2571 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2572 int index = 0x04; // 0x04 indicates no index
2573 int scale = 0x00; // 0x00 indicates no scale
2574 int displace = $src1$$constant; // 0x00 indicates no displacement
2575 relocInfo::relocType disp_reloc = relocInfo::none;
2576 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2577 disp_reloc);
2578 %}
2579
2580 enc_class neg_reg(rRegI dst)
2581 %{
2582 int dstenc = $dst$$reg;
2583 if (dstenc >= 8) {
2584 emit_opcode(cbuf, Assembler::REX_B);
2585 dstenc -= 8;
2586 }
2587 // NEG $dst
2588 emit_opcode(cbuf, 0xF7);
2589 emit_rm(cbuf, 0x3, 0x03, dstenc);
2590 %}
2591
2592 enc_class neg_reg_wide(rRegI dst)
2593 %{
2594 int dstenc = $dst$$reg;
2595 if (dstenc < 8) {
2596 emit_opcode(cbuf, Assembler::REX_W);
2597 } else {
2598 emit_opcode(cbuf, Assembler::REX_WB);
2599 dstenc -= 8;
2600 }
2601 // NEG $dst
2602 emit_opcode(cbuf, 0xF7);
2603 emit_rm(cbuf, 0x3, 0x03, dstenc);
2604 %}
2605
2606 enc_class setLT_reg(rRegI dst)
2607 %{
2608 int dstenc = $dst$$reg;
2609 if (dstenc >= 8) {
2610 emit_opcode(cbuf, Assembler::REX_B);
2611 dstenc -= 8;
2612 } else if (dstenc >= 4) {
2613 emit_opcode(cbuf, Assembler::REX);
2614 }
2615 // SETLT $dst
2616 emit_opcode(cbuf, 0x0F);
2617 emit_opcode(cbuf, 0x9C);
2618 emit_rm(cbuf, 0x3, 0x0, dstenc);
2619 %}
2620
2621 enc_class setNZ_reg(rRegI dst)
2622 %{
2623 int dstenc = $dst$$reg;
2624 if (dstenc >= 8) {
2625 emit_opcode(cbuf, Assembler::REX_B);
2626 dstenc -= 8;
2627 } else if (dstenc >= 4) {
2628 emit_opcode(cbuf, Assembler::REX);
2629 }
2630 // SETNZ $dst
2631 emit_opcode(cbuf, 0x0F);
2632 emit_opcode(cbuf, 0x95);
2633 emit_rm(cbuf, 0x3, 0x0, dstenc);
2634 %}
2635
2636
2637 // Compare the lonogs and set -1, 0, or 1 into dst
2638 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2639 %{
2640 int src1enc = $src1$$reg;
2641 int src2enc = $src2$$reg;
2642 int dstenc = $dst$$reg;
2643
2644 // cmpq $src1, $src2
2645 if (src1enc < 8) {
2646 if (src2enc < 8) {
2647 emit_opcode(cbuf, Assembler::REX_W);
2648 } else {
2649 emit_opcode(cbuf, Assembler::REX_WB);
2650 }
2651 } else {
2652 if (src2enc < 8) {
2653 emit_opcode(cbuf, Assembler::REX_WR);
2654 } else {
2655 emit_opcode(cbuf, Assembler::REX_WRB);
2656 }
2657 }
2658 emit_opcode(cbuf, 0x3B);
2659 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2660
2661 // movl $dst, -1
2662 if (dstenc >= 8) {
2663 emit_opcode(cbuf, Assembler::REX_B);
2664 }
2665 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2666 emit_d32(cbuf, -1);
2667
2668 // jl,s done
2669 emit_opcode(cbuf, 0x7C);
2670 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2671
2672 // setne $dst
2673 if (dstenc >= 4) {
2674 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2675 }
2676 emit_opcode(cbuf, 0x0F);
2677 emit_opcode(cbuf, 0x95);
2678 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2679
2680 // movzbl $dst, $dst
2681 if (dstenc >= 4) {
2682 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2683 }
2684 emit_opcode(cbuf, 0x0F);
2685 emit_opcode(cbuf, 0xB6);
2686 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2687 %}
2688
2689 enc_class Push_ResultXD(regD dst) %{
2690 MacroAssembler _masm(&cbuf);
2691 __ fstp_d(Address(rsp, 0));
2692 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2693 __ addptr(rsp, 8);
2694 %}
2695
2696 enc_class Push_SrcXD(regD src) %{
2697 MacroAssembler _masm(&cbuf);
2698 __ subptr(rsp, 8);
2699 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2700 __ fld_d(Address(rsp, 0));
2701 %}
2702
2703
2704 enc_class enc_rethrow()
2705 %{
2706 cbuf.set_insts_mark();
2707 emit_opcode(cbuf, 0xE9); // jmp entry
2708 emit_d32_reloc(cbuf,
2709 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2710 runtime_call_Relocation::spec(),
2711 RELOC_DISP32);
2712 %}
2713
2714 %}
2715
2716
2717
2718 //----------FRAME--------------------------------------------------------------
2719 // Definition of frame structure and management information.
2720 //
2721 // S T A C K L A Y O U T Allocators stack-slot number
2722 // | (to get allocators register number
2723 // G Owned by | | v add OptoReg::stack0())
2724 // r CALLER | |
2725 // o | +--------+ pad to even-align allocators stack-slot
2726 // w V | pad0 | numbers; owned by CALLER
2727 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2728 // h ^ | in | 5
2729 // | | args | 4 Holes in incoming args owned by SELF
2730 // | | | | 3
2731 // | | +--------+
2732 // V | | old out| Empty on Intel, window on Sparc
2733 // | old |preserve| Must be even aligned.
2734 // | SP-+--------+----> Matcher::_old_SP, even aligned
2735 // | | in | 3 area for Intel ret address
2736 // Owned by |preserve| Empty on Sparc.
2737 // SELF +--------+
2738 // | | pad2 | 2 pad to align old SP
2739 // | +--------+ 1
2740 // | | locks | 0
2741 // | +--------+----> OptoReg::stack0(), even aligned
2742 // | | pad1 | 11 pad to align new SP
2743 // | +--------+
2744 // | | | 10
2745 // | | spills | 9 spills
2746 // V | | 8 (pad0 slot for callee)
2747 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2748 // ^ | out | 7
2749 // | | args | 6 Holes in outgoing args owned by CALLEE
2750 // Owned by +--------+
2751 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2752 // | new |preserve| Must be even-aligned.
2753 // | SP-+--------+----> Matcher::_new_SP, even aligned
2754 // | | |
2755 //
2756 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2757 // known from SELF's arguments and the Java calling convention.
2758 // Region 6-7 is determined per call site.
2759 // Note 2: If the calling convention leaves holes in the incoming argument
2760 // area, those holes are owned by SELF. Holes in the outgoing area
2761 // are owned by the CALLEE. Holes should not be nessecary in the
2762 // incoming area, as the Java calling convention is completely under
2763 // the control of the AD file. Doubles can be sorted and packed to
2764 // avoid holes. Holes in the outgoing arguments may be nessecary for
2765 // varargs C calling conventions.
2766 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2767 // even aligned with pad0 as needed.
2768 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2769 // region 6-11 is even aligned; it may be padded out more so that
2770 // the region from SP to FP meets the minimum stack alignment.
2771 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2772 // alignment. Region 11, pad1, may be dynamically extended so that
2773 // SP meets the minimum alignment.
2774
2775 frame
2776 %{
2777 // What direction does stack grow in (assumed to be same for C & Java)
2778 stack_direction(TOWARDS_LOW);
2779
2780 // These three registers define part of the calling convention
2781 // between compiled code and the interpreter.
2782 inline_cache_reg(RAX); // Inline Cache Register
2783 interpreter_method_oop_reg(RBX); // Method Oop Register when
2784 // calling interpreter
2785
2786 // Optional: name the operand used by cisc-spilling to access
2787 // [stack_pointer + offset]
2788 cisc_spilling_operand_name(indOffset32);
2789
2790 // Number of stack slots consumed by locking an object
2791 sync_stack_slots(2);
2792
2793 // Compiled code's Frame Pointer
2794 frame_pointer(RSP);
2795
2796 // Interpreter stores its frame pointer in a register which is
2797 // stored to the stack by I2CAdaptors.
2798 // I2CAdaptors convert from interpreted java to compiled java.
2799 interpreter_frame_pointer(RBP);
2800
2801 // Stack alignment requirement
2802 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2803
2804 // Number of stack slots between incoming argument block and the start of
2805 // a new frame. The PROLOG must add this many slots to the stack. The
2806 // EPILOG must remove this many slots. amd64 needs two slots for
2807 // return address.
2808 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2809
2810 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2811 // for calls to C. Supports the var-args backing area for register parms.
2812 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2813
2814 // The after-PROLOG location of the return address. Location of
2815 // return address specifies a type (REG or STACK) and a number
2816 // representing the register number (i.e. - use a register name) or
2817 // stack slot.
2818 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2819 // Otherwise, it is above the locks and verification slot and alignment word
2820 return_addr(STACK - 2 +
2821 align_up((Compile::current()->in_preserve_stack_slots() +
2822 Compile::current()->fixed_slots()),
2823 stack_alignment_in_slots()));
2824
2825 // Body of function which returns an integer array locating
2826 // arguments either in registers or in stack slots. Passed an array
2827 // of ideal registers called "sig" and a "length" count. Stack-slot
2828 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2829 // arguments for a CALLEE. Incoming stack arguments are
2830 // automatically biased by the preserve_stack_slots field above.
2831
2832 calling_convention
2833 %{
2834 // No difference between ingoing/outgoing just pass false
2835 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2836 %}
2837
2838 c_calling_convention
2839 %{
2840 // This is obviously always outgoing
2841 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2842 %}
2843
2844 // Location of compiled Java return values. Same as C for now.
2845 return_value
2846 %{
2847 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2848 "only return normal values");
2849
2850 static const int lo[Op_RegL + 1] = {
2851 0,
2852 0,
2853 RAX_num, // Op_RegN
2854 RAX_num, // Op_RegI
2855 RAX_num, // Op_RegP
2856 XMM0_num, // Op_RegF
2857 XMM0_num, // Op_RegD
2858 RAX_num // Op_RegL
2859 };
2860 static const int hi[Op_RegL + 1] = {
2861 0,
2862 0,
2863 OptoReg::Bad, // Op_RegN
2864 OptoReg::Bad, // Op_RegI
2865 RAX_H_num, // Op_RegP
2866 OptoReg::Bad, // Op_RegF
2867 XMM0b_num, // Op_RegD
2868 RAX_H_num // Op_RegL
2869 };
2870 // Excluded flags and vector registers.
2871 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2872 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2873 %}
2874 %}
2875
2876 //----------ATTRIBUTES---------------------------------------------------------
2877 //----------Operand Attributes-------------------------------------------------
2878 op_attrib op_cost(0); // Required cost attribute
2879
2880 //----------Instruction Attributes---------------------------------------------
2881 ins_attrib ins_cost(100); // Required cost attribute
2882 ins_attrib ins_size(8); // Required size attribute (in bits)
2883 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2884 // a non-matching short branch variant
2885 // of some long branch?
2886 ins_attrib ins_alignment(1); // Required alignment attribute (must
2887 // be a power of 2) specifies the
2888 // alignment that some part of the
2889 // instruction (not necessarily the
2890 // start) requires. If > 1, a
2891 // compute_padding() function must be
2892 // provided for the instruction
2893
2894 //----------OPERANDS-----------------------------------------------------------
2895 // Operand definitions must precede instruction definitions for correct parsing
2896 // in the ADLC because operands constitute user defined types which are used in
2897 // instruction definitions.
2898
2899 //----------Simple Operands----------------------------------------------------
2900 // Immediate Operands
2901 // Integer Immediate
2902 operand immI()
2903 %{
2904 match(ConI);
2905
2906 op_cost(10);
2907 format %{ %}
2908 interface(CONST_INTER);
2909 %}
2910
2911 // Constant for test vs zero
2912 operand immI0()
2913 %{
2914 predicate(n->get_int() == 0);
2915 match(ConI);
2916
2917 op_cost(0);
2918 format %{ %}
2919 interface(CONST_INTER);
2920 %}
2921
2922 // Constant for increment
2923 operand immI1()
2924 %{
2925 predicate(n->get_int() == 1);
2926 match(ConI);
2927
2928 op_cost(0);
2929 format %{ %}
2930 interface(CONST_INTER);
2931 %}
2932
2933 // Constant for decrement
2934 operand immI_M1()
2935 %{
2936 predicate(n->get_int() == -1);
2937 match(ConI);
2938
2939 op_cost(0);
2940 format %{ %}
2941 interface(CONST_INTER);
2942 %}
2943
2944 // Valid scale values for addressing modes
2945 operand immI2()
2946 %{
2947 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2948 match(ConI);
2949
2950 format %{ %}
2951 interface(CONST_INTER);
2952 %}
2953
2954 operand immI8()
2955 %{
2956 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2957 match(ConI);
2958
2959 op_cost(5);
2960 format %{ %}
2961 interface(CONST_INTER);
2962 %}
2963
2964 operand immU8()
2965 %{
2966 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2967 match(ConI);
2968
2969 op_cost(5);
2970 format %{ %}
2971 interface(CONST_INTER);
2972 %}
2973
2974 operand immI16()
2975 %{
2976 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2977 match(ConI);
2978
2979 op_cost(10);
2980 format %{ %}
2981 interface(CONST_INTER);
2982 %}
2983
2984 // Int Immediate non-negative
2985 operand immU31()
2986 %{
2987 predicate(n->get_int() >= 0);
2988 match(ConI);
2989
2990 op_cost(0);
2991 format %{ %}
2992 interface(CONST_INTER);
2993 %}
2994
2995 // Constant for long shifts
2996 operand immI_32()
2997 %{
2998 predicate( n->get_int() == 32 );
2999 match(ConI);
3000
3001 op_cost(0);
3002 format %{ %}
3003 interface(CONST_INTER);
3004 %}
3005
3006 // Constant for long shifts
3007 operand immI_64()
3008 %{
3009 predicate( n->get_int() == 64 );
3010 match(ConI);
3011
3012 op_cost(0);
3013 format %{ %}
3014 interface(CONST_INTER);
3015 %}
3016
3017 // Pointer Immediate
3018 operand immP()
3019 %{
3020 match(ConP);
3021
3022 op_cost(10);
3023 format %{ %}
3024 interface(CONST_INTER);
3025 %}
3026
3027 // NULL Pointer Immediate
3028 operand immP0()
3029 %{
3030 predicate(n->get_ptr() == 0);
3031 match(ConP);
3032
3033 op_cost(5);
3034 format %{ %}
3035 interface(CONST_INTER);
3036 %}
3037
3038 // Pointer Immediate
3039 operand immN() %{
3040 match(ConN);
3041
3042 op_cost(10);
3043 format %{ %}
3044 interface(CONST_INTER);
3045 %}
3046
3047 operand immNKlass() %{
3048 match(ConNKlass);
3049
3050 op_cost(10);
3051 format %{ %}
3052 interface(CONST_INTER);
3053 %}
3054
3055 // NULL Pointer Immediate
3056 operand immN0() %{
3057 predicate(n->get_narrowcon() == 0);
3058 match(ConN);
3059
3060 op_cost(5);
3061 format %{ %}
3062 interface(CONST_INTER);
3063 %}
3064
3065 operand immP31()
3066 %{
3067 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3068 && (n->get_ptr() >> 31) == 0);
3069 match(ConP);
3070
3071 op_cost(5);
3072 format %{ %}
3073 interface(CONST_INTER);
3074 %}
3075
3076
3077 // Long Immediate
3078 operand immL()
3079 %{
3080 match(ConL);
3081
3082 op_cost(20);
3083 format %{ %}
3084 interface(CONST_INTER);
3085 %}
3086
3087 // Long Immediate 8-bit
3088 operand immL8()
3089 %{
3090 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3091 match(ConL);
3092
3093 op_cost(5);
3094 format %{ %}
3095 interface(CONST_INTER);
3096 %}
3097
3098 // Long Immediate 32-bit unsigned
3099 operand immUL32()
3100 %{
3101 predicate(n->get_long() == (unsigned int) (n->get_long()));
3102 match(ConL);
3103
3104 op_cost(10);
3105 format %{ %}
3106 interface(CONST_INTER);
3107 %}
3108
3109 // Long Immediate 32-bit signed
3110 operand immL32()
3111 %{
3112 predicate(n->get_long() == (int) (n->get_long()));
3113 match(ConL);
3114
3115 op_cost(15);
3116 format %{ %}
3117 interface(CONST_INTER);
3118 %}
3119
3120 // Long Immediate zero
3121 operand immL0()
3122 %{
3123 predicate(n->get_long() == 0L);
3124 match(ConL);
3125
3126 op_cost(10);
3127 format %{ %}
3128 interface(CONST_INTER);
3129 %}
3130
3131 // Constant for increment
3132 operand immL1()
3133 %{
3134 predicate(n->get_long() == 1);
3135 match(ConL);
3136
3137 format %{ %}
3138 interface(CONST_INTER);
3139 %}
3140
3141 // Constant for decrement
3142 operand immL_M1()
3143 %{
3144 predicate(n->get_long() == -1);
3145 match(ConL);
3146
3147 format %{ %}
3148 interface(CONST_INTER);
3149 %}
3150
3151 // Long Immediate: the value 10
3152 operand immL10()
3153 %{
3154 predicate(n->get_long() == 10);
3155 match(ConL);
3156
3157 format %{ %}
3158 interface(CONST_INTER);
3159 %}
3160
3161 // Long immediate from 0 to 127.
3162 // Used for a shorter form of long mul by 10.
3163 operand immL_127()
3164 %{
3165 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3166 match(ConL);
3167
3168 op_cost(10);
3169 format %{ %}
3170 interface(CONST_INTER);
3171 %}
3172
3173 // Long Immediate: low 32-bit mask
3174 operand immL_32bits()
3175 %{
3176 predicate(n->get_long() == 0xFFFFFFFFL);
3177 match(ConL);
3178 op_cost(20);
3179
3180 format %{ %}
3181 interface(CONST_INTER);
3182 %}
3183
3184 // Float Immediate zero
3185 operand immF0()
3186 %{
3187 predicate(jint_cast(n->getf()) == 0);
3188 match(ConF);
3189
3190 op_cost(5);
3191 format %{ %}
3192 interface(CONST_INTER);
3193 %}
3194
3195 // Float Immediate
3196 operand immF()
3197 %{
3198 match(ConF);
3199
3200 op_cost(15);
3201 format %{ %}
3202 interface(CONST_INTER);
3203 %}
3204
3205 // Double Immediate zero
3206 operand immD0()
3207 %{
3208 predicate(jlong_cast(n->getd()) == 0);
3209 match(ConD);
3210
3211 op_cost(5);
3212 format %{ %}
3213 interface(CONST_INTER);
3214 %}
3215
3216 // Double Immediate
3217 operand immD()
3218 %{
3219 match(ConD);
3220
3221 op_cost(15);
3222 format %{ %}
3223 interface(CONST_INTER);
3224 %}
3225
3226 // Immediates for special shifts (sign extend)
3227
3228 // Constants for increment
3229 operand immI_16()
3230 %{
3231 predicate(n->get_int() == 16);
3232 match(ConI);
3233
3234 format %{ %}
3235 interface(CONST_INTER);
3236 %}
3237
3238 operand immI_24()
3239 %{
3240 predicate(n->get_int() == 24);
3241 match(ConI);
3242
3243 format %{ %}
3244 interface(CONST_INTER);
3245 %}
3246
3247 // Constant for byte-wide masking
3248 operand immI_255()
3249 %{
3250 predicate(n->get_int() == 255);
3251 match(ConI);
3252
3253 format %{ %}
3254 interface(CONST_INTER);
3255 %}
3256
3257 // Constant for short-wide masking
3258 operand immI_65535()
3259 %{
3260 predicate(n->get_int() == 65535);
3261 match(ConI);
3262
3263 format %{ %}
3264 interface(CONST_INTER);
3265 %}
3266
3267 // Constant for byte-wide masking
3268 operand immL_255()
3269 %{
3270 predicate(n->get_long() == 255);
3271 match(ConL);
3272
3273 format %{ %}
3274 interface(CONST_INTER);
3275 %}
3276
3277 // Constant for short-wide masking
3278 operand immL_65535()
3279 %{
3280 predicate(n->get_long() == 65535);
3281 match(ConL);
3282
3283 format %{ %}
3284 interface(CONST_INTER);
3285 %}
3286
3287 // Register Operands
3288 // Integer Register
3289 operand rRegI()
3290 %{
3291 constraint(ALLOC_IN_RC(int_reg));
3292 match(RegI);
3293
3294 match(rax_RegI);
3295 match(rbx_RegI);
3296 match(rcx_RegI);
3297 match(rdx_RegI);
3298 match(rdi_RegI);
3299
3300 format %{ %}
3301 interface(REG_INTER);
3302 %}
3303
3304 // Special Registers
3305 operand rax_RegI()
3306 %{
3307 constraint(ALLOC_IN_RC(int_rax_reg));
3308 match(RegI);
3309 match(rRegI);
3310
3311 format %{ "RAX" %}
3312 interface(REG_INTER);
3313 %}
3314
3315 // Special Registers
3316 operand rbx_RegI()
3317 %{
3318 constraint(ALLOC_IN_RC(int_rbx_reg));
3319 match(RegI);
3320 match(rRegI);
3321
3322 format %{ "RBX" %}
3323 interface(REG_INTER);
3324 %}
3325
3326 operand rcx_RegI()
3327 %{
3328 constraint(ALLOC_IN_RC(int_rcx_reg));
3329 match(RegI);
3330 match(rRegI);
3331
3332 format %{ "RCX" %}
3333 interface(REG_INTER);
3334 %}
3335
3336 operand rdx_RegI()
3337 %{
3338 constraint(ALLOC_IN_RC(int_rdx_reg));
3339 match(RegI);
3340 match(rRegI);
3341
3342 format %{ "RDX" %}
3343 interface(REG_INTER);
3344 %}
3345
3346 operand rdi_RegI()
3347 %{
3348 constraint(ALLOC_IN_RC(int_rdi_reg));
3349 match(RegI);
3350 match(rRegI);
3351
3352 format %{ "RDI" %}
3353 interface(REG_INTER);
3354 %}
3355
3356 operand no_rcx_RegI()
3357 %{
3358 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3359 match(RegI);
3360 match(rax_RegI);
3361 match(rbx_RegI);
3362 match(rdx_RegI);
3363 match(rdi_RegI);
3364
3365 format %{ %}
3366 interface(REG_INTER);
3367 %}
3368
3369 operand no_rax_rdx_RegI()
3370 %{
3371 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3372 match(RegI);
3373 match(rbx_RegI);
3374 match(rcx_RegI);
3375 match(rdi_RegI);
3376
3377 format %{ %}
3378 interface(REG_INTER);
3379 %}
3380
3381 // Pointer Register
3382 operand any_RegP()
3383 %{
3384 constraint(ALLOC_IN_RC(any_reg));
3385 match(RegP);
3386 match(rax_RegP);
3387 match(rbx_RegP);
3388 match(rdi_RegP);
3389 match(rsi_RegP);
3390 match(rbp_RegP);
3391 match(r15_RegP);
3392 match(rRegP);
3393
3394 format %{ %}
3395 interface(REG_INTER);
3396 %}
3397
3398 operand rRegP()
3399 %{
3400 constraint(ALLOC_IN_RC(ptr_reg));
3401 match(RegP);
3402 match(rax_RegP);
3403 match(rbx_RegP);
3404 match(rdi_RegP);
3405 match(rsi_RegP);
3406 match(rbp_RegP); // See Q&A below about
3407 match(r15_RegP); // r15_RegP and rbp_RegP.
3408
3409 format %{ %}
3410 interface(REG_INTER);
3411 %}
3412
3413 operand rRegN() %{
3414 constraint(ALLOC_IN_RC(int_reg));
3415 match(RegN);
3416
3417 format %{ %}
3418 interface(REG_INTER);
3419 %}
3420
3421 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3422 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3423 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3424 // The output of an instruction is controlled by the allocator, which respects
3425 // register class masks, not match rules. Unless an instruction mentions
3426 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3427 // by the allocator as an input.
3428 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3429 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3430 // result, RBP is not included in the output of the instruction either.
3431
3432 operand no_rax_RegP()
3433 %{
3434 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3435 match(RegP);
3436 match(rbx_RegP);
3437 match(rsi_RegP);
3438 match(rdi_RegP);
3439
3440 format %{ %}
3441 interface(REG_INTER);
3442 %}
3443
3444 // This operand is not allowed to use RBP even if
3445 // RBP is not used to hold the frame pointer.
3446 operand no_rbp_RegP()
3447 %{
3448 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3449 match(RegP);
3450 match(rbx_RegP);
3451 match(rsi_RegP);
3452 match(rdi_RegP);
3453
3454 format %{ %}
3455 interface(REG_INTER);
3456 %}
3457
3458 operand no_rax_rbx_RegP()
3459 %{
3460 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3461 match(RegP);
3462 match(rsi_RegP);
3463 match(rdi_RegP);
3464
3465 format %{ %}
3466 interface(REG_INTER);
3467 %}
3468
3469 // Special Registers
3470 // Return a pointer value
3471 operand rax_RegP()
3472 %{
3473 constraint(ALLOC_IN_RC(ptr_rax_reg));
3474 match(RegP);
3475 match(rRegP);
3476
3477 format %{ %}
3478 interface(REG_INTER);
3479 %}
3480
3481 // Special Registers
3482 // Return a compressed pointer value
3483 operand rax_RegN()
3484 %{
3485 constraint(ALLOC_IN_RC(int_rax_reg));
3486 match(RegN);
3487 match(rRegN);
3488
3489 format %{ %}
3490 interface(REG_INTER);
3491 %}
3492
3493 // Used in AtomicAdd
3494 operand rbx_RegP()
3495 %{
3496 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3497 match(RegP);
3498 match(rRegP);
3499
3500 format %{ %}
3501 interface(REG_INTER);
3502 %}
3503
3504 operand rsi_RegP()
3505 %{
3506 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3507 match(RegP);
3508 match(rRegP);
3509
3510 format %{ %}
3511 interface(REG_INTER);
3512 %}
3513
3514 // Used in rep stosq
3515 operand rdi_RegP()
3516 %{
3517 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3518 match(RegP);
3519 match(rRegP);
3520
3521 format %{ %}
3522 interface(REG_INTER);
3523 %}
3524
3525 operand r15_RegP()
3526 %{
3527 constraint(ALLOC_IN_RC(ptr_r15_reg));
3528 match(RegP);
3529 match(rRegP);
3530
3531 format %{ %}
3532 interface(REG_INTER);
3533 %}
3534
3535 operand rRegL()
3536 %{
3537 constraint(ALLOC_IN_RC(long_reg));
3538 match(RegL);
3539 match(rax_RegL);
3540 match(rdx_RegL);
3541
3542 format %{ %}
3543 interface(REG_INTER);
3544 %}
3545
3546 // Special Registers
3547 operand no_rax_rdx_RegL()
3548 %{
3549 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3550 match(RegL);
3551 match(rRegL);
3552
3553 format %{ %}
3554 interface(REG_INTER);
3555 %}
3556
3557 operand no_rax_RegL()
3558 %{
3559 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3560 match(RegL);
3561 match(rRegL);
3562 match(rdx_RegL);
3563
3564 format %{ %}
3565 interface(REG_INTER);
3566 %}
3567
3568 operand no_rcx_RegL()
3569 %{
3570 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3571 match(RegL);
3572 match(rRegL);
3573
3574 format %{ %}
3575 interface(REG_INTER);
3576 %}
3577
3578 operand rax_RegL()
3579 %{
3580 constraint(ALLOC_IN_RC(long_rax_reg));
3581 match(RegL);
3582 match(rRegL);
3583
3584 format %{ "RAX" %}
3585 interface(REG_INTER);
3586 %}
3587
3588 operand rcx_RegL()
3589 %{
3590 constraint(ALLOC_IN_RC(long_rcx_reg));
3591 match(RegL);
3592 match(rRegL);
3593
3594 format %{ %}
3595 interface(REG_INTER);
3596 %}
3597
3598 operand rdx_RegL()
3599 %{
3600 constraint(ALLOC_IN_RC(long_rdx_reg));
3601 match(RegL);
3602 match(rRegL);
3603
3604 format %{ %}
3605 interface(REG_INTER);
3606 %}
3607
3608 // Flags register, used as output of compare instructions
3609 operand rFlagsReg()
3610 %{
3611 constraint(ALLOC_IN_RC(int_flags));
3612 match(RegFlags);
3613
3614 format %{ "RFLAGS" %}
3615 interface(REG_INTER);
3616 %}
3617
3618 // Flags register, used as output of FLOATING POINT compare instructions
3619 operand rFlagsRegU()
3620 %{
3621 constraint(ALLOC_IN_RC(int_flags));
3622 match(RegFlags);
3623
3624 format %{ "RFLAGS_U" %}
3625 interface(REG_INTER);
3626 %}
3627
3628 operand rFlagsRegUCF() %{
3629 constraint(ALLOC_IN_RC(int_flags));
3630 match(RegFlags);
3631 predicate(false);
3632
3633 format %{ "RFLAGS_U_CF" %}
3634 interface(REG_INTER);
3635 %}
3636
3637 // Float register operands
3638 operand regF() %{
3639 constraint(ALLOC_IN_RC(float_reg));
3640 match(RegF);
3641
3642 format %{ %}
3643 interface(REG_INTER);
3644 %}
3645
3646 // Float register operands
3647 operand legRegF() %{
3648 constraint(ALLOC_IN_RC(float_reg_legacy));
3649 match(RegF);
3650
3651 format %{ %}
3652 interface(REG_INTER);
3653 %}
3654
3655 // Float register operands
3656 operand vlRegF() %{
3657 constraint(ALLOC_IN_RC(float_reg_vl));
3658 match(RegF);
3659
3660 format %{ %}
3661 interface(REG_INTER);
3662 %}
3663
3664 // Double register operands
3665 operand regD() %{
3666 constraint(ALLOC_IN_RC(double_reg));
3667 match(RegD);
3668
3669 format %{ %}
3670 interface(REG_INTER);
3671 %}
3672
3673 // Double register operands
3674 operand legRegD() %{
3675 constraint(ALLOC_IN_RC(double_reg_legacy));
3676 match(RegD);
3677
3678 format %{ %}
3679 interface(REG_INTER);
3680 %}
3681
3682 // Double register operands
3683 operand vlRegD() %{
3684 constraint(ALLOC_IN_RC(double_reg_vl));
3685 match(RegD);
3686
3687 format %{ %}
3688 interface(REG_INTER);
3689 %}
3690
3691 // Vectors
3692 operand vecS() %{
3693 constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3694 match(VecS);
3695
3696 format %{ %}
3697 interface(REG_INTER);
3698 %}
3699
3700 // Vectors
3701 operand legVecS() %{
3702 constraint(ALLOC_IN_RC(vectors_reg_legacy));
3703 match(VecS);
3704
3705 format %{ %}
3706 interface(REG_INTER);
3707 %}
3708
3709 operand vecD() %{
3710 constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3711 match(VecD);
3712
3713 format %{ %}
3714 interface(REG_INTER);
3715 %}
3716
3717 operand legVecD() %{
3718 constraint(ALLOC_IN_RC(vectord_reg_legacy));
3719 match(VecD);
3720
3721 format %{ %}
3722 interface(REG_INTER);
3723 %}
3724
3725 operand vecX() %{
3726 constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3727 match(VecX);
3728
3729 format %{ %}
3730 interface(REG_INTER);
3731 %}
3732
3733 operand legVecX() %{
3734 constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3735 match(VecX);
3736
3737 format %{ %}
3738 interface(REG_INTER);
3739 %}
3740
3741 operand vecY() %{
3742 constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3743 match(VecY);
3744
3745 format %{ %}
3746 interface(REG_INTER);
3747 %}
3748
3749 operand legVecY() %{
3750 constraint(ALLOC_IN_RC(vectory_reg_legacy));
3751 match(VecY);
3752
3753 format %{ %}
3754 interface(REG_INTER);
3755 %}
3756
3757 //----------Memory Operands----------------------------------------------------
3758 // Direct Memory Operand
3759 // operand direct(immP addr)
3760 // %{
3761 // match(addr);
3762
3763 // format %{ "[$addr]" %}
3764 // interface(MEMORY_INTER) %{
3765 // base(0xFFFFFFFF);
3766 // index(0x4);
3767 // scale(0x0);
3768 // disp($addr);
3769 // %}
3770 // %}
3771
3772 // Indirect Memory Operand
3773 operand indirect(any_RegP reg)
3774 %{
3775 constraint(ALLOC_IN_RC(ptr_reg));
3776 match(reg);
3777
3778 format %{ "[$reg]" %}
3779 interface(MEMORY_INTER) %{
3780 base($reg);
3781 index(0x4);
3782 scale(0x0);
3783 disp(0x0);
3784 %}
3785 %}
3786
3787 // Indirect Memory Plus Short Offset Operand
3788 operand indOffset8(any_RegP reg, immL8 off)
3789 %{
3790 constraint(ALLOC_IN_RC(ptr_reg));
3791 match(AddP reg off);
3792
3793 format %{ "[$reg + $off (8-bit)]" %}
3794 interface(MEMORY_INTER) %{
3795 base($reg);
3796 index(0x4);
3797 scale(0x0);
3798 disp($off);
3799 %}
3800 %}
3801
3802 // Indirect Memory Plus Long Offset Operand
3803 operand indOffset32(any_RegP reg, immL32 off)
3804 %{
3805 constraint(ALLOC_IN_RC(ptr_reg));
3806 match(AddP reg off);
3807
3808 format %{ "[$reg + $off (32-bit)]" %}
3809 interface(MEMORY_INTER) %{
3810 base($reg);
3811 index(0x4);
3812 scale(0x0);
3813 disp($off);
3814 %}
3815 %}
3816
3817 // Indirect Memory Plus Index Register Plus Offset Operand
3818 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3819 %{
3820 constraint(ALLOC_IN_RC(ptr_reg));
3821 match(AddP (AddP reg lreg) off);
3822
3823 op_cost(10);
3824 format %{"[$reg + $off + $lreg]" %}
3825 interface(MEMORY_INTER) %{
3826 base($reg);
3827 index($lreg);
3828 scale(0x0);
3829 disp($off);
3830 %}
3831 %}
3832
3833 // Indirect Memory Plus Index Register Plus Offset Operand
3834 operand indIndex(any_RegP reg, rRegL lreg)
3835 %{
3836 constraint(ALLOC_IN_RC(ptr_reg));
3837 match(AddP reg lreg);
3838
3839 op_cost(10);
3840 format %{"[$reg + $lreg]" %}
3841 interface(MEMORY_INTER) %{
3842 base($reg);
3843 index($lreg);
3844 scale(0x0);
3845 disp(0x0);
3846 %}
3847 %}
3848
3849 // Indirect Memory Times Scale Plus Index Register
3850 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3851 %{
3852 constraint(ALLOC_IN_RC(ptr_reg));
3853 match(AddP reg (LShiftL lreg scale));
3854
3855 op_cost(10);
3856 format %{"[$reg + $lreg << $scale]" %}
3857 interface(MEMORY_INTER) %{
3858 base($reg);
3859 index($lreg);
3860 scale($scale);
3861 disp(0x0);
3862 %}
3863 %}
3864
3865 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3866 %{
3867 constraint(ALLOC_IN_RC(ptr_reg));
3868 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3869 match(AddP reg (LShiftL (ConvI2L idx) scale));
3870
3871 op_cost(10);
3872 format %{"[$reg + pos $idx << $scale]" %}
3873 interface(MEMORY_INTER) %{
3874 base($reg);
3875 index($idx);
3876 scale($scale);
3877 disp(0x0);
3878 %}
3879 %}
3880
3881 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3882 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3883 %{
3884 constraint(ALLOC_IN_RC(ptr_reg));
3885 match(AddP (AddP reg (LShiftL lreg scale)) off);
3886
3887 op_cost(10);
3888 format %{"[$reg + $off + $lreg << $scale]" %}
3889 interface(MEMORY_INTER) %{
3890 base($reg);
3891 index($lreg);
3892 scale($scale);
3893 disp($off);
3894 %}
3895 %}
3896
3897 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3898 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3899 %{
3900 constraint(ALLOC_IN_RC(ptr_reg));
3901 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3902 match(AddP (AddP reg (ConvI2L idx)) off);
3903
3904 op_cost(10);
3905 format %{"[$reg + $off + $idx]" %}
3906 interface(MEMORY_INTER) %{
3907 base($reg);
3908 index($idx);
3909 scale(0x0);
3910 disp($off);
3911 %}
3912 %}
3913
3914 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3915 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3916 %{
3917 constraint(ALLOC_IN_RC(ptr_reg));
3918 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3919 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3920
3921 op_cost(10);
3922 format %{"[$reg + $off + $idx << $scale]" %}
3923 interface(MEMORY_INTER) %{
3924 base($reg);
3925 index($idx);
3926 scale($scale);
3927 disp($off);
3928 %}
3929 %}
3930
3931 // Indirect Narrow Oop Plus Offset Operand
3932 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3933 // we can't free r12 even with CompressedOops::base() == NULL.
3934 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3935 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3936 constraint(ALLOC_IN_RC(ptr_reg));
3937 match(AddP (DecodeN reg) off);
3938
3939 op_cost(10);
3940 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3941 interface(MEMORY_INTER) %{
3942 base(0xc); // R12
3943 index($reg);
3944 scale(0x3);
3945 disp($off);
3946 %}
3947 %}
3948
3949 // Indirect Memory Operand
3950 operand indirectNarrow(rRegN reg)
3951 %{
3952 predicate(CompressedOops::shift() == 0);
3953 constraint(ALLOC_IN_RC(ptr_reg));
3954 match(DecodeN reg);
3955
3956 format %{ "[$reg]" %}
3957 interface(MEMORY_INTER) %{
3958 base($reg);
3959 index(0x4);
3960 scale(0x0);
3961 disp(0x0);
3962 %}
3963 %}
3964
3965 // Indirect Memory Plus Short Offset Operand
3966 operand indOffset8Narrow(rRegN reg, immL8 off)
3967 %{
3968 predicate(CompressedOops::shift() == 0);
3969 constraint(ALLOC_IN_RC(ptr_reg));
3970 match(AddP (DecodeN reg) off);
3971
3972 format %{ "[$reg + $off (8-bit)]" %}
3973 interface(MEMORY_INTER) %{
3974 base($reg);
3975 index(0x4);
3976 scale(0x0);
3977 disp($off);
3978 %}
3979 %}
3980
3981 // Indirect Memory Plus Long Offset Operand
3982 operand indOffset32Narrow(rRegN reg, immL32 off)
3983 %{
3984 predicate(CompressedOops::shift() == 0);
3985 constraint(ALLOC_IN_RC(ptr_reg));
3986 match(AddP (DecodeN reg) off);
3987
3988 format %{ "[$reg + $off (32-bit)]" %}
3989 interface(MEMORY_INTER) %{
3990 base($reg);
3991 index(0x4);
3992 scale(0x0);
3993 disp($off);
3994 %}
3995 %}
3996
3997 // Indirect Memory Plus Index Register Plus Offset Operand
3998 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3999 %{
4000 predicate(CompressedOops::shift() == 0);
4001 constraint(ALLOC_IN_RC(ptr_reg));
4002 match(AddP (AddP (DecodeN reg) lreg) off);
4003
4004 op_cost(10);
4005 format %{"[$reg + $off + $lreg]" %}
4006 interface(MEMORY_INTER) %{
4007 base($reg);
4008 index($lreg);
4009 scale(0x0);
4010 disp($off);
4011 %}
4012 %}
4013
4014 // Indirect Memory Plus Index Register Plus Offset Operand
4015 operand indIndexNarrow(rRegN reg, rRegL lreg)
4016 %{
4017 predicate(CompressedOops::shift() == 0);
4018 constraint(ALLOC_IN_RC(ptr_reg));
4019 match(AddP (DecodeN reg) lreg);
4020
4021 op_cost(10);
4022 format %{"[$reg + $lreg]" %}
4023 interface(MEMORY_INTER) %{
4024 base($reg);
4025 index($lreg);
4026 scale(0x0);
4027 disp(0x0);
4028 %}
4029 %}
4030
4031 // Indirect Memory Times Scale Plus Index Register
4032 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4033 %{
4034 predicate(CompressedOops::shift() == 0);
4035 constraint(ALLOC_IN_RC(ptr_reg));
4036 match(AddP (DecodeN reg) (LShiftL lreg scale));
4037
4038 op_cost(10);
4039 format %{"[$reg + $lreg << $scale]" %}
4040 interface(MEMORY_INTER) %{
4041 base($reg);
4042 index($lreg);
4043 scale($scale);
4044 disp(0x0);
4045 %}
4046 %}
4047
4048 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4049 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4050 %{
4051 predicate(CompressedOops::shift() == 0);
4052 constraint(ALLOC_IN_RC(ptr_reg));
4053 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4054
4055 op_cost(10);
4056 format %{"[$reg + $off + $lreg << $scale]" %}
4057 interface(MEMORY_INTER) %{
4058 base($reg);
4059 index($lreg);
4060 scale($scale);
4061 disp($off);
4062 %}
4063 %}
4064
4065 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4066 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4067 %{
4068 constraint(ALLOC_IN_RC(ptr_reg));
4069 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4070 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4071
4072 op_cost(10);
4073 format %{"[$reg + $off + $idx]" %}
4074 interface(MEMORY_INTER) %{
4075 base($reg);
4076 index($idx);
4077 scale(0x0);
4078 disp($off);
4079 %}
4080 %}
4081
4082 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4083 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4084 %{
4085 constraint(ALLOC_IN_RC(ptr_reg));
4086 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4087 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4088
4089 op_cost(10);
4090 format %{"[$reg + $off + $idx << $scale]" %}
4091 interface(MEMORY_INTER) %{
4092 base($reg);
4093 index($idx);
4094 scale($scale);
4095 disp($off);
4096 %}
4097 %}
4098
4099 //----------Special Memory Operands--------------------------------------------
4100 // Stack Slot Operand - This operand is used for loading and storing temporary
4101 // values on the stack where a match requires a value to
4102 // flow through memory.
4103 operand stackSlotP(sRegP reg)
4104 %{
4105 constraint(ALLOC_IN_RC(stack_slots));
4106 // No match rule because this operand is only generated in matching
4107
4108 format %{ "[$reg]" %}
4109 interface(MEMORY_INTER) %{
4110 base(0x4); // RSP
4111 index(0x4); // No Index
4112 scale(0x0); // No Scale
4113 disp($reg); // Stack Offset
4114 %}
4115 %}
4116
4117 operand stackSlotI(sRegI reg)
4118 %{
4119 constraint(ALLOC_IN_RC(stack_slots));
4120 // No match rule because this operand is only generated in matching
4121
4122 format %{ "[$reg]" %}
4123 interface(MEMORY_INTER) %{
4124 base(0x4); // RSP
4125 index(0x4); // No Index
4126 scale(0x0); // No Scale
4127 disp($reg); // Stack Offset
4128 %}
4129 %}
4130
4131 operand stackSlotF(sRegF reg)
4132 %{
4133 constraint(ALLOC_IN_RC(stack_slots));
4134 // No match rule because this operand is only generated in matching
4135
4136 format %{ "[$reg]" %}
4137 interface(MEMORY_INTER) %{
4138 base(0x4); // RSP
4139 index(0x4); // No Index
4140 scale(0x0); // No Scale
4141 disp($reg); // Stack Offset
4142 %}
4143 %}
4144
4145 operand stackSlotD(sRegD reg)
4146 %{
4147 constraint(ALLOC_IN_RC(stack_slots));
4148 // No match rule because this operand is only generated in matching
4149
4150 format %{ "[$reg]" %}
4151 interface(MEMORY_INTER) %{
4152 base(0x4); // RSP
4153 index(0x4); // No Index
4154 scale(0x0); // No Scale
4155 disp($reg); // Stack Offset
4156 %}
4157 %}
4158 operand stackSlotL(sRegL reg)
4159 %{
4160 constraint(ALLOC_IN_RC(stack_slots));
4161 // No match rule because this operand is only generated in matching
4162
4163 format %{ "[$reg]" %}
4164 interface(MEMORY_INTER) %{
4165 base(0x4); // RSP
4166 index(0x4); // No Index
4167 scale(0x0); // No Scale
4168 disp($reg); // Stack Offset
4169 %}
4170 %}
4171
4172 //----------Conditional Branch Operands----------------------------------------
4173 // Comparison Op - This is the operation of the comparison, and is limited to
4174 // the following set of codes:
4175 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4176 //
4177 // Other attributes of the comparison, such as unsignedness, are specified
4178 // by the comparison instruction that sets a condition code flags register.
4179 // That result is represented by a flags operand whose subtype is appropriate
4180 // to the unsignedness (etc.) of the comparison.
4181 //
4182 // Later, the instruction which matches both the Comparison Op (a Bool) and
4183 // the flags (produced by the Cmp) specifies the coding of the comparison op
4184 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4185
4186 // Comparision Code
4187 operand cmpOp()
4188 %{
4189 match(Bool);
4190
4191 format %{ "" %}
4192 interface(COND_INTER) %{
4193 equal(0x4, "e");
4194 not_equal(0x5, "ne");
4195 less(0xC, "l");
4196 greater_equal(0xD, "ge");
4197 less_equal(0xE, "le");
4198 greater(0xF, "g");
4199 overflow(0x0, "o");
4200 no_overflow(0x1, "no");
4201 %}
4202 %}
4203
4204 // Comparison Code, unsigned compare. Used by FP also, with
4205 // C2 (unordered) turned into GT or LT already. The other bits
4206 // C0 and C3 are turned into Carry & Zero flags.
4207 operand cmpOpU()
4208 %{
4209 match(Bool);
4210
4211 format %{ "" %}
4212 interface(COND_INTER) %{
4213 equal(0x4, "e");
4214 not_equal(0x5, "ne");
4215 less(0x2, "b");
4216 greater_equal(0x3, "nb");
4217 less_equal(0x6, "be");
4218 greater(0x7, "nbe");
4219 overflow(0x0, "o");
4220 no_overflow(0x1, "no");
4221 %}
4222 %}
4223
4224
4225 // Floating comparisons that don't require any fixup for the unordered case
4226 operand cmpOpUCF() %{
4227 match(Bool);
4228 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4229 n->as_Bool()->_test._test == BoolTest::ge ||
4230 n->as_Bool()->_test._test == BoolTest::le ||
4231 n->as_Bool()->_test._test == BoolTest::gt);
4232 format %{ "" %}
4233 interface(COND_INTER) %{
4234 equal(0x4, "e");
4235 not_equal(0x5, "ne");
4236 less(0x2, "b");
4237 greater_equal(0x3, "nb");
4238 less_equal(0x6, "be");
4239 greater(0x7, "nbe");
4240 overflow(0x0, "o");
4241 no_overflow(0x1, "no");
4242 %}
4243 %}
4244
4245
4246 // Floating comparisons that can be fixed up with extra conditional jumps
4247 operand cmpOpUCF2() %{
4248 match(Bool);
4249 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4250 n->as_Bool()->_test._test == BoolTest::eq);
4251 format %{ "" %}
4252 interface(COND_INTER) %{
4253 equal(0x4, "e");
4254 not_equal(0x5, "ne");
4255 less(0x2, "b");
4256 greater_equal(0x3, "nb");
4257 less_equal(0x6, "be");
4258 greater(0x7, "nbe");
4259 overflow(0x0, "o");
4260 no_overflow(0x1, "no");
4261 %}
4262 %}
4263
4264 // Operands for bound floating pointer register arguments
4265 operand rxmm0() %{
4266 constraint(ALLOC_IN_RC(xmm0_reg));
4267 match(VecX);
4268 format%{%}
4269 interface(REG_INTER);
4270 %}
4271 operand rxmm1() %{
4272 constraint(ALLOC_IN_RC(xmm1_reg));
4273 match(VecX);
4274 format%{%}
4275 interface(REG_INTER);
4276 %}
4277 operand rxmm2() %{
4278 constraint(ALLOC_IN_RC(xmm2_reg));
4279 match(VecX);
4280 format%{%}
4281 interface(REG_INTER);
4282 %}
4283 operand rxmm3() %{
4284 constraint(ALLOC_IN_RC(xmm3_reg));
4285 match(VecX);
4286 format%{%}
4287 interface(REG_INTER);
4288 %}
4289 operand rxmm4() %{
4290 constraint(ALLOC_IN_RC(xmm4_reg));
4291 match(VecX);
4292 format%{%}
4293 interface(REG_INTER);
4294 %}
4295 operand rxmm5() %{
4296 constraint(ALLOC_IN_RC(xmm5_reg));
4297 match(VecX);
4298 format%{%}
4299 interface(REG_INTER);
4300 %}
4301 operand rxmm6() %{
4302 constraint(ALLOC_IN_RC(xmm6_reg));
4303 match(VecX);
4304 format%{%}
4305 interface(REG_INTER);
4306 %}
4307 operand rxmm7() %{
4308 constraint(ALLOC_IN_RC(xmm7_reg));
4309 match(VecX);
4310 format%{%}
4311 interface(REG_INTER);
4312 %}
4313 operand rxmm8() %{
4314 constraint(ALLOC_IN_RC(xmm8_reg));
4315 match(VecX);
4316 format%{%}
4317 interface(REG_INTER);
4318 %}
4319 operand rxmm9() %{
4320 constraint(ALLOC_IN_RC(xmm9_reg));
4321 match(VecX);
4322 format%{%}
4323 interface(REG_INTER);
4324 %}
4325 operand rxmm10() %{
4326 constraint(ALLOC_IN_RC(xmm10_reg));
4327 match(VecX);
4328 format%{%}
4329 interface(REG_INTER);
4330 %}
4331 operand rxmm11() %{
4332 constraint(ALLOC_IN_RC(xmm11_reg));
4333 match(VecX);
4334 format%{%}
4335 interface(REG_INTER);
4336 %}
4337 operand rxmm12() %{
4338 constraint(ALLOC_IN_RC(xmm12_reg));
4339 match(VecX);
4340 format%{%}
4341 interface(REG_INTER);
4342 %}
4343 operand rxmm13() %{
4344 constraint(ALLOC_IN_RC(xmm13_reg));
4345 match(VecX);
4346 format%{%}
4347 interface(REG_INTER);
4348 %}
4349 operand rxmm14() %{
4350 constraint(ALLOC_IN_RC(xmm14_reg));
4351 match(VecX);
4352 format%{%}
4353 interface(REG_INTER);
4354 %}
4355 operand rxmm15() %{
4356 constraint(ALLOC_IN_RC(xmm15_reg));
4357 match(VecX);
4358 format%{%}
4359 interface(REG_INTER);
4360 %}
4361 operand rxmm16() %{
4362 constraint(ALLOC_IN_RC(xmm16_reg));
4363 match(VecX);
4364 format%{%}
4365 interface(REG_INTER);
4366 %}
4367 operand rxmm17() %{
4368 constraint(ALLOC_IN_RC(xmm17_reg));
4369 match(VecX);
4370 format%{%}
4371 interface(REG_INTER);
4372 %}
4373 operand rxmm18() %{
4374 constraint(ALLOC_IN_RC(xmm18_reg));
4375 match(VecX);
4376 format%{%}
4377 interface(REG_INTER);
4378 %}
4379 operand rxmm19() %{
4380 constraint(ALLOC_IN_RC(xmm19_reg));
4381 match(VecX);
4382 format%{%}
4383 interface(REG_INTER);
4384 %}
4385 operand rxmm20() %{
4386 constraint(ALLOC_IN_RC(xmm20_reg));
4387 match(VecX);
4388 format%{%}
4389 interface(REG_INTER);
4390 %}
4391 operand rxmm21() %{
4392 constraint(ALLOC_IN_RC(xmm21_reg));
4393 match(VecX);
4394 format%{%}
4395 interface(REG_INTER);
4396 %}
4397 operand rxmm22() %{
4398 constraint(ALLOC_IN_RC(xmm22_reg));
4399 match(VecX);
4400 format%{%}
4401 interface(REG_INTER);
4402 %}
4403 operand rxmm23() %{
4404 constraint(ALLOC_IN_RC(xmm23_reg));
4405 match(VecX);
4406 format%{%}
4407 interface(REG_INTER);
4408 %}
4409 operand rxmm24() %{
4410 constraint(ALLOC_IN_RC(xmm24_reg));
4411 match(VecX);
4412 format%{%}
4413 interface(REG_INTER);
4414 %}
4415 operand rxmm25() %{
4416 constraint(ALLOC_IN_RC(xmm25_reg));
4417 match(VecX);
4418 format%{%}
4419 interface(REG_INTER);
4420 %}
4421 operand rxmm26() %{
4422 constraint(ALLOC_IN_RC(xmm26_reg));
4423 match(VecX);
4424 format%{%}
4425 interface(REG_INTER);
4426 %}
4427 operand rxmm27() %{
4428 constraint(ALLOC_IN_RC(xmm27_reg));
4429 match(VecX);
4430 format%{%}
4431 interface(REG_INTER);
4432 %}
4433 operand rxmm28() %{
4434 constraint(ALLOC_IN_RC(xmm28_reg));
4435 match(VecX);
4436 format%{%}
4437 interface(REG_INTER);
4438 %}
4439 operand rxmm29() %{
4440 constraint(ALLOC_IN_RC(xmm29_reg));
4441 match(VecX);
4442 format%{%}
4443 interface(REG_INTER);
4444 %}
4445 operand rxmm30() %{
4446 constraint(ALLOC_IN_RC(xmm30_reg));
4447 match(VecX);
4448 format%{%}
4449 interface(REG_INTER);
4450 %}
4451 operand rxmm31() %{
4452 constraint(ALLOC_IN_RC(xmm31_reg));
4453 match(VecX);
4454 format%{%}
4455 interface(REG_INTER);
4456 %}
4457
4458 //----------OPERAND CLASSES----------------------------------------------------
4459 // Operand Classes are groups of operands that are used as to simplify
4460 // instruction definitions by not requiring the AD writer to specify separate
4461 // instructions for every form of operand when the instruction accepts
4462 // multiple operand types with the same basic encoding and format. The classic
4463 // case of this is memory operands.
4464
4465 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4466 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4467 indCompressedOopOffset,
4468 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4469 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4470 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4471
4472 //----------PIPELINE-----------------------------------------------------------
4473 // Rules which define the behavior of the target architectures pipeline.
4474 pipeline %{
4475
4476 //----------ATTRIBUTES---------------------------------------------------------
4477 attributes %{
4478 variable_size_instructions; // Fixed size instructions
4479 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4480 instruction_unit_size = 1; // An instruction is 1 bytes long
4481 instruction_fetch_unit_size = 16; // The processor fetches one line
4482 instruction_fetch_units = 1; // of 16 bytes
4483
4484 // List of nop instructions
4485 nops( MachNop );
4486 %}
4487
4488 //----------RESOURCES----------------------------------------------------------
4489 // Resources are the functional units available to the machine
4490
4491 // Generic P2/P3 pipeline
4492 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4493 // 3 instructions decoded per cycle.
4494 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4495 // 3 ALU op, only ALU0 handles mul instructions.
4496 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4497 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4498 BR, FPU,
4499 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4500
4501 //----------PIPELINE DESCRIPTION-----------------------------------------------
4502 // Pipeline Description specifies the stages in the machine's pipeline
4503
4504 // Generic P2/P3 pipeline
4505 pipe_desc(S0, S1, S2, S3, S4, S5);
4506
4507 //----------PIPELINE CLASSES---------------------------------------------------
4508 // Pipeline Classes describe the stages in which input and output are
4509 // referenced by the hardware pipeline.
4510
4511 // Naming convention: ialu or fpu
4512 // Then: _reg
4513 // Then: _reg if there is a 2nd register
4514 // Then: _long if it's a pair of instructions implementing a long
4515 // Then: _fat if it requires the big decoder
4516 // Or: _mem if it requires the big decoder and a memory unit.
4517
4518 // Integer ALU reg operation
4519 pipe_class ialu_reg(rRegI dst)
4520 %{
4521 single_instruction;
4522 dst : S4(write);
4523 dst : S3(read);
4524 DECODE : S0; // any decoder
4525 ALU : S3; // any alu
4526 %}
4527
4528 // Long ALU reg operation
4529 pipe_class ialu_reg_long(rRegL dst)
4530 %{
4531 instruction_count(2);
4532 dst : S4(write);
4533 dst : S3(read);
4534 DECODE : S0(2); // any 2 decoders
4535 ALU : S3(2); // both alus
4536 %}
4537
4538 // Integer ALU reg operation using big decoder
4539 pipe_class ialu_reg_fat(rRegI dst)
4540 %{
4541 single_instruction;
4542 dst : S4(write);
4543 dst : S3(read);
4544 D0 : S0; // big decoder only
4545 ALU : S3; // any alu
4546 %}
4547
4548 // Long ALU reg operation using big decoder
4549 pipe_class ialu_reg_long_fat(rRegL dst)
4550 %{
4551 instruction_count(2);
4552 dst : S4(write);
4553 dst : S3(read);
4554 D0 : S0(2); // big decoder only; twice
4555 ALU : S3(2); // any 2 alus
4556 %}
4557
4558 // Integer ALU reg-reg operation
4559 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4560 %{
4561 single_instruction;
4562 dst : S4(write);
4563 src : S3(read);
4564 DECODE : S0; // any decoder
4565 ALU : S3; // any alu
4566 %}
4567
4568 // Long ALU reg-reg operation
4569 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4570 %{
4571 instruction_count(2);
4572 dst : S4(write);
4573 src : S3(read);
4574 DECODE : S0(2); // any 2 decoders
4575 ALU : S3(2); // both alus
4576 %}
4577
4578 // Integer ALU reg-reg operation
4579 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4580 %{
4581 single_instruction;
4582 dst : S4(write);
4583 src : S3(read);
4584 D0 : S0; // big decoder only
4585 ALU : S3; // any alu
4586 %}
4587
4588 // Long ALU reg-reg operation
4589 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4590 %{
4591 instruction_count(2);
4592 dst : S4(write);
4593 src : S3(read);
4594 D0 : S0(2); // big decoder only; twice
4595 ALU : S3(2); // both alus
4596 %}
4597
4598 // Integer ALU reg-mem operation
4599 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4600 %{
4601 single_instruction;
4602 dst : S5(write);
4603 mem : S3(read);
4604 D0 : S0; // big decoder only
4605 ALU : S4; // any alu
4606 MEM : S3; // any mem
4607 %}
4608
4609 // Integer mem operation (prefetch)
4610 pipe_class ialu_mem(memory mem)
4611 %{
4612 single_instruction;
4613 mem : S3(read);
4614 D0 : S0; // big decoder only
4615 MEM : S3; // any mem
4616 %}
4617
4618 // Integer Store to Memory
4619 pipe_class ialu_mem_reg(memory mem, rRegI src)
4620 %{
4621 single_instruction;
4622 mem : S3(read);
4623 src : S5(read);
4624 D0 : S0; // big decoder only
4625 ALU : S4; // any alu
4626 MEM : S3;
4627 %}
4628
4629 // // Long Store to Memory
4630 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4631 // %{
4632 // instruction_count(2);
4633 // mem : S3(read);
4634 // src : S5(read);
4635 // D0 : S0(2); // big decoder only; twice
4636 // ALU : S4(2); // any 2 alus
4637 // MEM : S3(2); // Both mems
4638 // %}
4639
4640 // Integer Store to Memory
4641 pipe_class ialu_mem_imm(memory mem)
4642 %{
4643 single_instruction;
4644 mem : S3(read);
4645 D0 : S0; // big decoder only
4646 ALU : S4; // any alu
4647 MEM : S3;
4648 %}
4649
4650 // Integer ALU0 reg-reg operation
4651 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4652 %{
4653 single_instruction;
4654 dst : S4(write);
4655 src : S3(read);
4656 D0 : S0; // Big decoder only
4657 ALU0 : S3; // only alu0
4658 %}
4659
4660 // Integer ALU0 reg-mem operation
4661 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4662 %{
4663 single_instruction;
4664 dst : S5(write);
4665 mem : S3(read);
4666 D0 : S0; // big decoder only
4667 ALU0 : S4; // ALU0 only
4668 MEM : S3; // any mem
4669 %}
4670
4671 // Integer ALU reg-reg operation
4672 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4673 %{
4674 single_instruction;
4675 cr : S4(write);
4676 src1 : S3(read);
4677 src2 : S3(read);
4678 DECODE : S0; // any decoder
4679 ALU : S3; // any alu
4680 %}
4681
4682 // Integer ALU reg-imm operation
4683 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4684 %{
4685 single_instruction;
4686 cr : S4(write);
4687 src1 : S3(read);
4688 DECODE : S0; // any decoder
4689 ALU : S3; // any alu
4690 %}
4691
4692 // Integer ALU reg-mem operation
4693 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4694 %{
4695 single_instruction;
4696 cr : S4(write);
4697 src1 : S3(read);
4698 src2 : S3(read);
4699 D0 : S0; // big decoder only
4700 ALU : S4; // any alu
4701 MEM : S3;
4702 %}
4703
4704 // Conditional move reg-reg
4705 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4706 %{
4707 instruction_count(4);
4708 y : S4(read);
4709 q : S3(read);
4710 p : S3(read);
4711 DECODE : S0(4); // any decoder
4712 %}
4713
4714 // Conditional move reg-reg
4715 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4716 %{
4717 single_instruction;
4718 dst : S4(write);
4719 src : S3(read);
4720 cr : S3(read);
4721 DECODE : S0; // any decoder
4722 %}
4723
4724 // Conditional move reg-mem
4725 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4726 %{
4727 single_instruction;
4728 dst : S4(write);
4729 src : S3(read);
4730 cr : S3(read);
4731 DECODE : S0; // any decoder
4732 MEM : S3;
4733 %}
4734
4735 // Conditional move reg-reg long
4736 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4737 %{
4738 single_instruction;
4739 dst : S4(write);
4740 src : S3(read);
4741 cr : S3(read);
4742 DECODE : S0(2); // any 2 decoders
4743 %}
4744
4745 // XXX
4746 // // Conditional move double reg-reg
4747 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4748 // %{
4749 // single_instruction;
4750 // dst : S4(write);
4751 // src : S3(read);
4752 // cr : S3(read);
4753 // DECODE : S0; // any decoder
4754 // %}
4755
4756 // Float reg-reg operation
4757 pipe_class fpu_reg(regD dst)
4758 %{
4759 instruction_count(2);
4760 dst : S3(read);
4761 DECODE : S0(2); // any 2 decoders
4762 FPU : S3;
4763 %}
4764
4765 // Float reg-reg operation
4766 pipe_class fpu_reg_reg(regD dst, regD src)
4767 %{
4768 instruction_count(2);
4769 dst : S4(write);
4770 src : S3(read);
4771 DECODE : S0(2); // any 2 decoders
4772 FPU : S3;
4773 %}
4774
4775 // Float reg-reg operation
4776 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4777 %{
4778 instruction_count(3);
4779 dst : S4(write);
4780 src1 : S3(read);
4781 src2 : S3(read);
4782 DECODE : S0(3); // any 3 decoders
4783 FPU : S3(2);
4784 %}
4785
4786 // Float reg-reg operation
4787 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4788 %{
4789 instruction_count(4);
4790 dst : S4(write);
4791 src1 : S3(read);
4792 src2 : S3(read);
4793 src3 : S3(read);
4794 DECODE : S0(4); // any 3 decoders
4795 FPU : S3(2);
4796 %}
4797
4798 // Float reg-reg operation
4799 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4800 %{
4801 instruction_count(4);
4802 dst : S4(write);
4803 src1 : S3(read);
4804 src2 : S3(read);
4805 src3 : S3(read);
4806 DECODE : S1(3); // any 3 decoders
4807 D0 : S0; // Big decoder only
4808 FPU : S3(2);
4809 MEM : S3;
4810 %}
4811
4812 // Float reg-mem operation
4813 pipe_class fpu_reg_mem(regD dst, memory mem)
4814 %{
4815 instruction_count(2);
4816 dst : S5(write);
4817 mem : S3(read);
4818 D0 : S0; // big decoder only
4819 DECODE : S1; // any decoder for FPU POP
4820 FPU : S4;
4821 MEM : S3; // any mem
4822 %}
4823
4824 // Float reg-mem operation
4825 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4826 %{
4827 instruction_count(3);
4828 dst : S5(write);
4829 src1 : S3(read);
4830 mem : S3(read);
4831 D0 : S0; // big decoder only
4832 DECODE : S1(2); // any decoder for FPU POP
4833 FPU : S4;
4834 MEM : S3; // any mem
4835 %}
4836
4837 // Float mem-reg operation
4838 pipe_class fpu_mem_reg(memory mem, regD src)
4839 %{
4840 instruction_count(2);
4841 src : S5(read);
4842 mem : S3(read);
4843 DECODE : S0; // any decoder for FPU PUSH
4844 D0 : S1; // big decoder only
4845 FPU : S4;
4846 MEM : S3; // any mem
4847 %}
4848
4849 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4850 %{
4851 instruction_count(3);
4852 src1 : S3(read);
4853 src2 : S3(read);
4854 mem : S3(read);
4855 DECODE : S0(2); // any decoder for FPU PUSH
4856 D0 : S1; // big decoder only
4857 FPU : S4;
4858 MEM : S3; // any mem
4859 %}
4860
4861 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4862 %{
4863 instruction_count(3);
4864 src1 : S3(read);
4865 src2 : S3(read);
4866 mem : S4(read);
4867 DECODE : S0; // any decoder for FPU PUSH
4868 D0 : S0(2); // big decoder only
4869 FPU : S4;
4870 MEM : S3(2); // any mem
4871 %}
4872
4873 pipe_class fpu_mem_mem(memory dst, memory src1)
4874 %{
4875 instruction_count(2);
4876 src1 : S3(read);
4877 dst : S4(read);
4878 D0 : S0(2); // big decoder only
4879 MEM : S3(2); // any mem
4880 %}
4881
4882 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4883 %{
4884 instruction_count(3);
4885 src1 : S3(read);
4886 src2 : S3(read);
4887 dst : S4(read);
4888 D0 : S0(3); // big decoder only
4889 FPU : S4;
4890 MEM : S3(3); // any mem
4891 %}
4892
4893 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4894 %{
4895 instruction_count(3);
4896 src1 : S4(read);
4897 mem : S4(read);
4898 DECODE : S0; // any decoder for FPU PUSH
4899 D0 : S0(2); // big decoder only
4900 FPU : S4;
4901 MEM : S3(2); // any mem
4902 %}
4903
4904 // Float load constant
4905 pipe_class fpu_reg_con(regD dst)
4906 %{
4907 instruction_count(2);
4908 dst : S5(write);
4909 D0 : S0; // big decoder only for the load
4910 DECODE : S1; // any decoder for FPU POP
4911 FPU : S4;
4912 MEM : S3; // any mem
4913 %}
4914
4915 // Float load constant
4916 pipe_class fpu_reg_reg_con(regD dst, regD src)
4917 %{
4918 instruction_count(3);
4919 dst : S5(write);
4920 src : S3(read);
4921 D0 : S0; // big decoder only for the load
4922 DECODE : S1(2); // any decoder for FPU POP
4923 FPU : S4;
4924 MEM : S3; // any mem
4925 %}
4926
4927 // UnConditional branch
4928 pipe_class pipe_jmp(label labl)
4929 %{
4930 single_instruction;
4931 BR : S3;
4932 %}
4933
4934 // Conditional branch
4935 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4936 %{
4937 single_instruction;
4938 cr : S1(read);
4939 BR : S3;
4940 %}
4941
4942 // Allocation idiom
4943 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4944 %{
4945 instruction_count(1); force_serialization;
4946 fixed_latency(6);
4947 heap_ptr : S3(read);
4948 DECODE : S0(3);
4949 D0 : S2;
4950 MEM : S3;
4951 ALU : S3(2);
4952 dst : S5(write);
4953 BR : S5;
4954 %}
4955
4956 // Generic big/slow expanded idiom
4957 pipe_class pipe_slow()
4958 %{
4959 instruction_count(10); multiple_bundles; force_serialization;
4960 fixed_latency(100);
4961 D0 : S0(2);
4962 MEM : S3(2);
4963 %}
4964
4965 // The real do-nothing guy
4966 pipe_class empty()
4967 %{
4968 instruction_count(0);
4969 %}
4970
4971 // Define the class for the Nop node
4972 define
4973 %{
4974 MachNop = empty;
4975 %}
4976
4977 %}
4978
4979 //----------INSTRUCTIONS-------------------------------------------------------
4980 //
4981 // match -- States which machine-independent subtree may be replaced
4982 // by this instruction.
4983 // ins_cost -- The estimated cost of this instruction is used by instruction
4984 // selection to identify a minimum cost tree of machine
4985 // instructions that matches a tree of machine-independent
4986 // instructions.
4987 // format -- A string providing the disassembly for this instruction.
4988 // The value of an instruction's operand may be inserted
4989 // by referring to it with a '$' prefix.
4990 // opcode -- Three instruction opcodes may be provided. These are referred
4991 // to within an encode class as $primary, $secondary, and $tertiary
4992 // rrspectively. The primary opcode is commonly used to
4993 // indicate the type of machine instruction, while secondary
4994 // and tertiary are often used for prefix options or addressing
4995 // modes.
4996 // ins_encode -- A list of encode classes with parameters. The encode class
4997 // name must have been defined in an 'enc_class' specification
4998 // in the encode section of the architecture description.
4999
5000
5001 //----------Load/Store/Move Instructions---------------------------------------
5002 //----------Load Instructions--------------------------------------------------
5003
5004 // Load Byte (8 bit signed)
5005 instruct loadB(rRegI dst, memory mem)
5006 %{
5007 match(Set dst (LoadB mem));
5008
5009 ins_cost(125);
5010 format %{ "movsbl $dst, $mem\t# byte" %}
5011
5012 ins_encode %{
5013 __ movsbl($dst$$Register, $mem$$Address);
5014 %}
5015
5016 ins_pipe(ialu_reg_mem);
5017 %}
5018
5019 // Load Byte (8 bit signed) into Long Register
5020 instruct loadB2L(rRegL dst, memory mem)
5021 %{
5022 match(Set dst (ConvI2L (LoadB mem)));
5023
5024 ins_cost(125);
5025 format %{ "movsbq $dst, $mem\t# byte -> long" %}
5026
5027 ins_encode %{
5028 __ movsbq($dst$$Register, $mem$$Address);
5029 %}
5030
5031 ins_pipe(ialu_reg_mem);
5032 %}
5033
5034 // Load Unsigned Byte (8 bit UNsigned)
5035 instruct loadUB(rRegI dst, memory mem)
5036 %{
5037 match(Set dst (LoadUB mem));
5038
5039 ins_cost(125);
5040 format %{ "movzbl $dst, $mem\t# ubyte" %}
5041
5042 ins_encode %{
5043 __ movzbl($dst$$Register, $mem$$Address);
5044 %}
5045
5046 ins_pipe(ialu_reg_mem);
5047 %}
5048
5049 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5050 instruct loadUB2L(rRegL dst, memory mem)
5051 %{
5052 match(Set dst (ConvI2L (LoadUB mem)));
5053
5054 ins_cost(125);
5055 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
5056
5057 ins_encode %{
5058 __ movzbq($dst$$Register, $mem$$Address);
5059 %}
5060
5061 ins_pipe(ialu_reg_mem);
5062 %}
5063
5064 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5065 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5066 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5067 effect(KILL cr);
5068
5069 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
5070 "andl $dst, right_n_bits($mask, 8)" %}
5071 ins_encode %{
5072 Register Rdst = $dst$$Register;
5073 __ movzbq(Rdst, $mem$$Address);
5074 __ andl(Rdst, $mask$$constant & right_n_bits(8));
5075 %}
5076 ins_pipe(ialu_reg_mem);
5077 %}
5078
5079 // Load Short (16 bit signed)
5080 instruct loadS(rRegI dst, memory mem)
5081 %{
5082 match(Set dst (LoadS mem));
5083
5084 ins_cost(125);
5085 format %{ "movswl $dst, $mem\t# short" %}
5086
5087 ins_encode %{
5088 __ movswl($dst$$Register, $mem$$Address);
5089 %}
5090
5091 ins_pipe(ialu_reg_mem);
5092 %}
5093
5094 // Load Short (16 bit signed) to Byte (8 bit signed)
5095 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5096 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5097
5098 ins_cost(125);
5099 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5100 ins_encode %{
5101 __ movsbl($dst$$Register, $mem$$Address);
5102 %}
5103 ins_pipe(ialu_reg_mem);
5104 %}
5105
5106 // Load Short (16 bit signed) into Long Register
5107 instruct loadS2L(rRegL dst, memory mem)
5108 %{
5109 match(Set dst (ConvI2L (LoadS mem)));
5110
5111 ins_cost(125);
5112 format %{ "movswq $dst, $mem\t# short -> long" %}
5113
5114 ins_encode %{
5115 __ movswq($dst$$Register, $mem$$Address);
5116 %}
5117
5118 ins_pipe(ialu_reg_mem);
5119 %}
5120
5121 // Load Unsigned Short/Char (16 bit UNsigned)
5122 instruct loadUS(rRegI dst, memory mem)
5123 %{
5124 match(Set dst (LoadUS mem));
5125
5126 ins_cost(125);
5127 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5128
5129 ins_encode %{
5130 __ movzwl($dst$$Register, $mem$$Address);
5131 %}
5132
5133 ins_pipe(ialu_reg_mem);
5134 %}
5135
5136 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5137 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5138 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5139
5140 ins_cost(125);
5141 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5142 ins_encode %{
5143 __ movsbl($dst$$Register, $mem$$Address);
5144 %}
5145 ins_pipe(ialu_reg_mem);
5146 %}
5147
5148 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5149 instruct loadUS2L(rRegL dst, memory mem)
5150 %{
5151 match(Set dst (ConvI2L (LoadUS mem)));
5152
5153 ins_cost(125);
5154 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5155
5156 ins_encode %{
5157 __ movzwq($dst$$Register, $mem$$Address);
5158 %}
5159
5160 ins_pipe(ialu_reg_mem);
5161 %}
5162
5163 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5164 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5165 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5166
5167 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5168 ins_encode %{
5169 __ movzbq($dst$$Register, $mem$$Address);
5170 %}
5171 ins_pipe(ialu_reg_mem);
5172 %}
5173
5174 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5175 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5176 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5177 effect(KILL cr);
5178
5179 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5180 "andl $dst, right_n_bits($mask, 16)" %}
5181 ins_encode %{
5182 Register Rdst = $dst$$Register;
5183 __ movzwq(Rdst, $mem$$Address);
5184 __ andl(Rdst, $mask$$constant & right_n_bits(16));
5185 %}
5186 ins_pipe(ialu_reg_mem);
5187 %}
5188
5189 // Load Integer
5190 instruct loadI(rRegI dst, memory mem)
5191 %{
5192 match(Set dst (LoadI mem));
5193
5194 ins_cost(125);
5195 format %{ "movl $dst, $mem\t# int" %}
5196
5197 ins_encode %{
5198 __ movl($dst$$Register, $mem$$Address);
5199 %}
5200
5201 ins_pipe(ialu_reg_mem);
5202 %}
5203
5204 // Load Integer (32 bit signed) to Byte (8 bit signed)
5205 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5206 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5207
5208 ins_cost(125);
5209 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5210 ins_encode %{
5211 __ movsbl($dst$$Register, $mem$$Address);
5212 %}
5213 ins_pipe(ialu_reg_mem);
5214 %}
5215
5216 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5217 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5218 match(Set dst (AndI (LoadI mem) mask));
5219
5220 ins_cost(125);
5221 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5222 ins_encode %{
5223 __ movzbl($dst$$Register, $mem$$Address);
5224 %}
5225 ins_pipe(ialu_reg_mem);
5226 %}
5227
5228 // Load Integer (32 bit signed) to Short (16 bit signed)
5229 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5230 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5231
5232 ins_cost(125);
5233 format %{ "movswl $dst, $mem\t# int -> short" %}
5234 ins_encode %{
5235 __ movswl($dst$$Register, $mem$$Address);
5236 %}
5237 ins_pipe(ialu_reg_mem);
5238 %}
5239
5240 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5241 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5242 match(Set dst (AndI (LoadI mem) mask));
5243
5244 ins_cost(125);
5245 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5246 ins_encode %{
5247 __ movzwl($dst$$Register, $mem$$Address);
5248 %}
5249 ins_pipe(ialu_reg_mem);
5250 %}
5251
5252 // Load Integer into Long Register
5253 instruct loadI2L(rRegL dst, memory mem)
5254 %{
5255 match(Set dst (ConvI2L (LoadI mem)));
5256
5257 ins_cost(125);
5258 format %{ "movslq $dst, $mem\t# int -> long" %}
5259
5260 ins_encode %{
5261 __ movslq($dst$$Register, $mem$$Address);
5262 %}
5263
5264 ins_pipe(ialu_reg_mem);
5265 %}
5266
5267 // Load Integer with mask 0xFF into Long Register
5268 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5269 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5270
5271 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5272 ins_encode %{
5273 __ movzbq($dst$$Register, $mem$$Address);
5274 %}
5275 ins_pipe(ialu_reg_mem);
5276 %}
5277
5278 // Load Integer with mask 0xFFFF into Long Register
5279 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5280 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5281
5282 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5283 ins_encode %{
5284 __ movzwq($dst$$Register, $mem$$Address);
5285 %}
5286 ins_pipe(ialu_reg_mem);
5287 %}
5288
5289 // Load Integer with a 31-bit mask into Long Register
5290 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5291 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5292 effect(KILL cr);
5293
5294 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5295 "andl $dst, $mask" %}
5296 ins_encode %{
5297 Register Rdst = $dst$$Register;
5298 __ movl(Rdst, $mem$$Address);
5299 __ andl(Rdst, $mask$$constant);
5300 %}
5301 ins_pipe(ialu_reg_mem);
5302 %}
5303
5304 // Load Unsigned Integer into Long Register
5305 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5306 %{
5307 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5308
5309 ins_cost(125);
5310 format %{ "movl $dst, $mem\t# uint -> long" %}
5311
5312 ins_encode %{
5313 __ movl($dst$$Register, $mem$$Address);
5314 %}
5315
5316 ins_pipe(ialu_reg_mem);
5317 %}
5318
5319 // Load Long
5320 instruct loadL(rRegL dst, memory mem)
5321 %{
5322 match(Set dst (LoadL mem));
5323
5324 ins_cost(125);
5325 format %{ "movq $dst, $mem\t# long" %}
5326
5327 ins_encode %{
5328 __ movq($dst$$Register, $mem$$Address);
5329 %}
5330
5331 ins_pipe(ialu_reg_mem); // XXX
5332 %}
5333
5334 // Load Range
5335 instruct loadRange(rRegI dst, memory mem)
5336 %{
5337 match(Set dst (LoadRange mem));
5338
5339 ins_cost(125); // XXX
5340 format %{ "movl $dst, $mem\t# range" %}
5341 opcode(0x8B);
5342 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5343 ins_pipe(ialu_reg_mem);
5344 %}
5345
5346 // Load Pointer
5347 instruct loadP(rRegP dst, memory mem)
5348 %{
5349 match(Set dst (LoadP mem));
5350
5351 ins_cost(125); // XXX
5352 format %{ "movq $dst, $mem\t# ptr" %}
5353 opcode(0x8B);
5354 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5355 ins_pipe(ialu_reg_mem); // XXX
5356 %}
5357
5358 // Load Compressed Pointer
5359 instruct loadN(rRegN dst, memory mem)
5360 %{
5361 match(Set dst (LoadN mem));
5362
5363 ins_cost(125); // XXX
5364 format %{ "movl $dst, $mem\t# compressed ptr" %}
5365 ins_encode %{
5366 __ movl($dst$$Register, $mem$$Address);
5367 %}
5368 ins_pipe(ialu_reg_mem); // XXX
5369 %}
5370
5371
5372 // Load Klass Pointer
5373 instruct loadKlass(rRegP dst, memory mem)
5374 %{
5375 match(Set dst (LoadKlass mem));
5376
5377 ins_cost(125); // XXX
5378 format %{ "movq $dst, $mem\t# class" %}
5379 opcode(0x8B);
5380 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5381 ins_pipe(ialu_reg_mem); // XXX
5382 %}
5383
5384 // Load narrow Klass Pointer
5385 instruct loadNKlass(rRegN dst, memory mem)
5386 %{
5387 match(Set dst (LoadNKlass mem));
5388
5389 ins_cost(125); // XXX
5390 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5391 ins_encode %{
5392 __ movl($dst$$Register, $mem$$Address);
5393 %}
5394 ins_pipe(ialu_reg_mem); // XXX
5395 %}
5396
5397 // Load Float
5398 instruct loadF(regF dst, memory mem)
5399 %{
5400 match(Set dst (LoadF mem));
5401
5402 ins_cost(145); // XXX
5403 format %{ "movss $dst, $mem\t# float" %}
5404 ins_encode %{
5405 __ movflt($dst$$XMMRegister, $mem$$Address);
5406 %}
5407 ins_pipe(pipe_slow); // XXX
5408 %}
5409
5410 // Load Float
5411 instruct MoveF2VL(vlRegF dst, regF src) %{
5412 match(Set dst src);
5413 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5414 ins_encode %{
5415 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5416 %}
5417 ins_pipe( fpu_reg_reg );
5418 %}
5419
5420 // Load Float
5421 instruct MoveF2LEG(legRegF dst, regF src) %{
5422 match(Set dst src);
5423 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5424 ins_encode %{
5425 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5426 %}
5427 ins_pipe( fpu_reg_reg );
5428 %}
5429
5430 // Load Float
5431 instruct MoveVL2F(regF dst, vlRegF src) %{
5432 match(Set dst src);
5433 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5434 ins_encode %{
5435 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5436 %}
5437 ins_pipe( fpu_reg_reg );
5438 %}
5439
5440 // Load Float
5441 instruct MoveLEG2F(regF dst, legRegF src) %{
5442 match(Set dst src);
5443 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5444 ins_encode %{
5445 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5446 %}
5447 ins_pipe( fpu_reg_reg );
5448 %}
5449
5450 // Load Double
5451 instruct loadD_partial(regD dst, memory mem)
5452 %{
5453 predicate(!UseXmmLoadAndClearUpper);
5454 match(Set dst (LoadD mem));
5455
5456 ins_cost(145); // XXX
5457 format %{ "movlpd $dst, $mem\t# double" %}
5458 ins_encode %{
5459 __ movdbl($dst$$XMMRegister, $mem$$Address);
5460 %}
5461 ins_pipe(pipe_slow); // XXX
5462 %}
5463
5464 instruct loadD(regD dst, memory mem)
5465 %{
5466 predicate(UseXmmLoadAndClearUpper);
5467 match(Set dst (LoadD mem));
5468
5469 ins_cost(145); // XXX
5470 format %{ "movsd $dst, $mem\t# double" %}
5471 ins_encode %{
5472 __ movdbl($dst$$XMMRegister, $mem$$Address);
5473 %}
5474 ins_pipe(pipe_slow); // XXX
5475 %}
5476
5477 // Load Double
5478 instruct MoveD2VL(vlRegD dst, regD src) %{
5479 match(Set dst src);
5480 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5481 ins_encode %{
5482 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5483 %}
5484 ins_pipe( fpu_reg_reg );
5485 %}
5486
5487 // Load Double
5488 instruct MoveD2LEG(legRegD dst, regD src) %{
5489 match(Set dst src);
5490 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5491 ins_encode %{
5492 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5493 %}
5494 ins_pipe( fpu_reg_reg );
5495 %}
5496
5497 // Load Double
5498 instruct MoveVL2D(regD dst, vlRegD src) %{
5499 match(Set dst src);
5500 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5501 ins_encode %{
5502 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5503 %}
5504 ins_pipe( fpu_reg_reg );
5505 %}
5506
5507 // Load Double
5508 instruct MoveLEG2D(regD dst, legRegD src) %{
5509 match(Set dst src);
5510 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5511 ins_encode %{
5512 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5513 %}
5514 ins_pipe( fpu_reg_reg );
5515 %}
5516
5517 // Following pseudo code describes the algorithm for max[FD]:
5518 // Min algorithm is on similar lines
5519 // btmp = (b < +0.0) ? a : b
5520 // atmp = (b < +0.0) ? b : a
5521 // Tmp = Max_Float(atmp , btmp)
5522 // Res = (atmp == NaN) ? atmp : Tmp
5523
5524 // max = java.lang.Math.max(float a, float b)
5525 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5526 predicate(UseAVX > 0 && !n->is_reduction());
5527 match(Set dst (MaxF a b));
5528 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5529 format %{
5530 "blendvps $btmp,$b,$a,$b \n\t"
5531 "blendvps $atmp,$a,$b,$b \n\t"
5532 "vmaxss $tmp,$atmp,$btmp \n\t"
5533 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5534 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5535 %}
5536 ins_encode %{
5537 int vector_len = Assembler::AVX_128bit;
5538 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5539 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5540 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5541 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5542 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5543 %}
5544 ins_pipe( pipe_slow );
5545 %}
5546
5547 instruct maxF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{
5548 predicate(UseAVX > 0 && n->is_reduction());
5549 match(Set dst (MaxF a b));
5550 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5551
5552 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5553 ins_encode %{
5554 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5555 false /*min*/, true /*single*/);
5556 %}
5557 ins_pipe( pipe_slow );
5558 %}
5559
5560 // max = java.lang.Math.max(double a, double b)
5561 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5562 predicate(UseAVX > 0 && !n->is_reduction());
5563 match(Set dst (MaxD a b));
5564 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5565 format %{
5566 "blendvpd $btmp,$b,$a,$b \n\t"
5567 "blendvpd $atmp,$a,$b,$b \n\t"
5568 "vmaxsd $tmp,$atmp,$btmp \n\t"
5569 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5570 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5571 %}
5572 ins_encode %{
5573 int vector_len = Assembler::AVX_128bit;
5574 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5575 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5576 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5577 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5578 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5579 %}
5580 ins_pipe( pipe_slow );
5581 %}
5582
5583 instruct maxD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{
5584 predicate(UseAVX > 0 && n->is_reduction());
5585 match(Set dst (MaxD a b));
5586 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5587
5588 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5589 ins_encode %{
5590 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5591 false /*min*/, false /*single*/);
5592 %}
5593 ins_pipe( pipe_slow );
5594 %}
5595
5596 // min = java.lang.Math.min(float a, float b)
5597 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5598 predicate(UseAVX > 0 && !n->is_reduction());
5599 match(Set dst (MinF a b));
5600 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5601 format %{
5602 "blendvps $atmp,$a,$b,$a \n\t"
5603 "blendvps $btmp,$b,$a,$a \n\t"
5604 "vminss $tmp,$atmp,$btmp \n\t"
5605 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5606 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5607 %}
5608 ins_encode %{
5609 int vector_len = Assembler::AVX_128bit;
5610 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5611 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5612 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5613 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5614 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5615 %}
5616 ins_pipe( pipe_slow );
5617 %}
5618
5619 instruct minF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{
5620 predicate(UseAVX > 0 && n->is_reduction());
5621 match(Set dst (MinF a b));
5622 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5623
5624 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5625 ins_encode %{
5626 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5627 true /*min*/, true /*single*/);
5628 %}
5629 ins_pipe( pipe_slow );
5630 %}
5631
5632 // min = java.lang.Math.min(double a, double b)
5633 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5634 predicate(UseAVX > 0 && !n->is_reduction());
5635 match(Set dst (MinD a b));
5636 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5637 format %{
5638 "blendvpd $atmp,$a,$b,$a \n\t"
5639 "blendvpd $btmp,$b,$a,$a \n\t"
5640 "vminsd $tmp,$atmp,$btmp \n\t"
5641 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5642 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5643 %}
5644 ins_encode %{
5645 int vector_len = Assembler::AVX_128bit;
5646 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5647 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5648 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5649 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5650 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5651 %}
5652 ins_pipe( pipe_slow );
5653 %}
5654
5655 instruct minD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{
5656 predicate(UseAVX > 0 && n->is_reduction());
5657 match(Set dst (MinD a b));
5658 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5659
5660 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5661 ins_encode %{
5662 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5663 true /*min*/, false /*single*/);
5664 %}
5665 ins_pipe( pipe_slow );
5666 %}
5667
5668 // Load Effective Address
5669 instruct leaP8(rRegP dst, indOffset8 mem)
5670 %{
5671 match(Set dst mem);
5672
5673 ins_cost(110); // XXX
5674 format %{ "leaq $dst, $mem\t# ptr 8" %}
5675 opcode(0x8D);
5676 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5677 ins_pipe(ialu_reg_reg_fat);
5678 %}
5679
5680 instruct leaP32(rRegP dst, indOffset32 mem)
5681 %{
5682 match(Set dst mem);
5683
5684 ins_cost(110);
5685 format %{ "leaq $dst, $mem\t# ptr 32" %}
5686 opcode(0x8D);
5687 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5688 ins_pipe(ialu_reg_reg_fat);
5689 %}
5690
5691 // instruct leaPIdx(rRegP dst, indIndex mem)
5692 // %{
5693 // match(Set dst mem);
5694
5695 // ins_cost(110);
5696 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5697 // opcode(0x8D);
5698 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5699 // ins_pipe(ialu_reg_reg_fat);
5700 // %}
5701
5702 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5703 %{
5704 match(Set dst mem);
5705
5706 ins_cost(110);
5707 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5708 opcode(0x8D);
5709 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5710 ins_pipe(ialu_reg_reg_fat);
5711 %}
5712
5713 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5714 %{
5715 match(Set dst mem);
5716
5717 ins_cost(110);
5718 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5719 opcode(0x8D);
5720 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5721 ins_pipe(ialu_reg_reg_fat);
5722 %}
5723
5724 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5725 %{
5726 match(Set dst mem);
5727
5728 ins_cost(110);
5729 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5730 opcode(0x8D);
5731 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5732 ins_pipe(ialu_reg_reg_fat);
5733 %}
5734
5735 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5736 %{
5737 match(Set dst mem);
5738
5739 ins_cost(110);
5740 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5741 opcode(0x8D);
5742 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5743 ins_pipe(ialu_reg_reg_fat);
5744 %}
5745
5746 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5747 %{
5748 match(Set dst mem);
5749
5750 ins_cost(110);
5751 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5752 opcode(0x8D);
5753 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5754 ins_pipe(ialu_reg_reg_fat);
5755 %}
5756
5757 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5758 %{
5759 match(Set dst mem);
5760
5761 ins_cost(110);
5762 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5763 opcode(0x8D);
5764 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5765 ins_pipe(ialu_reg_reg_fat);
5766 %}
5767
5768 // Load Effective Address which uses Narrow (32-bits) oop
5769 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5770 %{
5771 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
5772 match(Set dst mem);
5773
5774 ins_cost(110);
5775 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5776 opcode(0x8D);
5777 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5778 ins_pipe(ialu_reg_reg_fat);
5779 %}
5780
5781 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5782 %{
5783 predicate(CompressedOops::shift() == 0);
5784 match(Set dst mem);
5785
5786 ins_cost(110); // XXX
5787 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5788 opcode(0x8D);
5789 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5790 ins_pipe(ialu_reg_reg_fat);
5791 %}
5792
5793 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5794 %{
5795 predicate(CompressedOops::shift() == 0);
5796 match(Set dst mem);
5797
5798 ins_cost(110);
5799 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5800 opcode(0x8D);
5801 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5802 ins_pipe(ialu_reg_reg_fat);
5803 %}
5804
5805 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5806 %{
5807 predicate(CompressedOops::shift() == 0);
5808 match(Set dst mem);
5809
5810 ins_cost(110);
5811 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5812 opcode(0x8D);
5813 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5814 ins_pipe(ialu_reg_reg_fat);
5815 %}
5816
5817 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5818 %{
5819 predicate(CompressedOops::shift() == 0);
5820 match(Set dst mem);
5821
5822 ins_cost(110);
5823 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5824 opcode(0x8D);
5825 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5826 ins_pipe(ialu_reg_reg_fat);
5827 %}
5828
5829 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5830 %{
5831 predicate(CompressedOops::shift() == 0);
5832 match(Set dst mem);
5833
5834 ins_cost(110);
5835 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5836 opcode(0x8D);
5837 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5838 ins_pipe(ialu_reg_reg_fat);
5839 %}
5840
5841 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5842 %{
5843 predicate(CompressedOops::shift() == 0);
5844 match(Set dst mem);
5845
5846 ins_cost(110);
5847 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5848 opcode(0x8D);
5849 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5850 ins_pipe(ialu_reg_reg_fat);
5851 %}
5852
5853 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5854 %{
5855 predicate(CompressedOops::shift() == 0);
5856 match(Set dst mem);
5857
5858 ins_cost(110);
5859 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5860 opcode(0x8D);
5861 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5862 ins_pipe(ialu_reg_reg_fat);
5863 %}
5864
5865 instruct loadConI(rRegI dst, immI src)
5866 %{
5867 match(Set dst src);
5868
5869 format %{ "movl $dst, $src\t# int" %}
5870 ins_encode(load_immI(dst, src));
5871 ins_pipe(ialu_reg_fat); // XXX
5872 %}
5873
5874 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5875 %{
5876 match(Set dst src);
5877 effect(KILL cr);
5878
5879 ins_cost(50);
5880 format %{ "xorl $dst, $dst\t# int" %}
5881 opcode(0x33); /* + rd */
5882 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5883 ins_pipe(ialu_reg);
5884 %}
5885
5886 instruct loadConL(rRegL dst, immL src)
5887 %{
5888 match(Set dst src);
5889
5890 ins_cost(150);
5891 format %{ "movq $dst, $src\t# long" %}
5892 ins_encode(load_immL(dst, src));
5893 ins_pipe(ialu_reg);
5894 %}
5895
5896 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5897 %{
5898 match(Set dst src);
5899 effect(KILL cr);
5900
5901 ins_cost(50);
5902 format %{ "xorl $dst, $dst\t# long" %}
5903 opcode(0x33); /* + rd */
5904 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5905 ins_pipe(ialu_reg); // XXX
5906 %}
5907
5908 instruct loadConUL32(rRegL dst, immUL32 src)
5909 %{
5910 match(Set dst src);
5911
5912 ins_cost(60);
5913 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5914 ins_encode(load_immUL32(dst, src));
5915 ins_pipe(ialu_reg);
5916 %}
5917
5918 instruct loadConL32(rRegL dst, immL32 src)
5919 %{
5920 match(Set dst src);
5921
5922 ins_cost(70);
5923 format %{ "movq $dst, $src\t# long (32-bit)" %}
5924 ins_encode(load_immL32(dst, src));
5925 ins_pipe(ialu_reg);
5926 %}
5927
5928 instruct loadConP(rRegP dst, immP con) %{
5929 match(Set dst con);
5930
5931 format %{ "movq $dst, $con\t# ptr" %}
5932 ins_encode(load_immP(dst, con));
5933 ins_pipe(ialu_reg_fat); // XXX
5934 %}
5935
5936 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5937 %{
5938 match(Set dst src);
5939 effect(KILL cr);
5940
5941 ins_cost(50);
5942 format %{ "xorl $dst, $dst\t# ptr" %}
5943 opcode(0x33); /* + rd */
5944 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5945 ins_pipe(ialu_reg);
5946 %}
5947
5948 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5949 %{
5950 match(Set dst src);
5951 effect(KILL cr);
5952
5953 ins_cost(60);
5954 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5955 ins_encode(load_immP31(dst, src));
5956 ins_pipe(ialu_reg);
5957 %}
5958
5959 instruct loadConF(regF dst, immF con) %{
5960 match(Set dst con);
5961 ins_cost(125);
5962 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5963 ins_encode %{
5964 __ movflt($dst$$XMMRegister, $constantaddress($con));
5965 %}
5966 ins_pipe(pipe_slow);
5967 %}
5968
5969 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5970 match(Set dst src);
5971 effect(KILL cr);
5972 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5973 ins_encode %{
5974 __ xorq($dst$$Register, $dst$$Register);
5975 %}
5976 ins_pipe(ialu_reg);
5977 %}
5978
5979 instruct loadConN(rRegN dst, immN src) %{
5980 match(Set dst src);
5981
5982 ins_cost(125);
5983 format %{ "movl $dst, $src\t# compressed ptr" %}
5984 ins_encode %{
5985 address con = (address)$src$$constant;
5986 if (con == NULL) {
5987 ShouldNotReachHere();
5988 } else {
5989 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5990 }
5991 %}
5992 ins_pipe(ialu_reg_fat); // XXX
5993 %}
5994
5995 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5996 match(Set dst src);
5997
5998 ins_cost(125);
5999 format %{ "movl $dst, $src\t# compressed klass ptr" %}
6000 ins_encode %{
6001 address con = (address)$src$$constant;
6002 if (con == NULL) {
6003 ShouldNotReachHere();
6004 } else {
6005 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
6006 }
6007 %}
6008 ins_pipe(ialu_reg_fat); // XXX
6009 %}
6010
6011 instruct loadConF0(regF dst, immF0 src)
6012 %{
6013 match(Set dst src);
6014 ins_cost(100);
6015
6016 format %{ "xorps $dst, $dst\t# float 0.0" %}
6017 ins_encode %{
6018 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6019 %}
6020 ins_pipe(pipe_slow);
6021 %}
6022
6023 // Use the same format since predicate() can not be used here.
6024 instruct loadConD(regD dst, immD con) %{
6025 match(Set dst con);
6026 ins_cost(125);
6027 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
6028 ins_encode %{
6029 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6030 %}
6031 ins_pipe(pipe_slow);
6032 %}
6033
6034 instruct loadConD0(regD dst, immD0 src)
6035 %{
6036 match(Set dst src);
6037 ins_cost(100);
6038
6039 format %{ "xorpd $dst, $dst\t# double 0.0" %}
6040 ins_encode %{
6041 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6042 %}
6043 ins_pipe(pipe_slow);
6044 %}
6045
6046 instruct loadSSI(rRegI dst, stackSlotI src)
6047 %{
6048 match(Set dst src);
6049
6050 ins_cost(125);
6051 format %{ "movl $dst, $src\t# int stk" %}
6052 opcode(0x8B);
6053 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6054 ins_pipe(ialu_reg_mem);
6055 %}
6056
6057 instruct loadSSL(rRegL dst, stackSlotL src)
6058 %{
6059 match(Set dst src);
6060
6061 ins_cost(125);
6062 format %{ "movq $dst, $src\t# long stk" %}
6063 opcode(0x8B);
6064 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6065 ins_pipe(ialu_reg_mem);
6066 %}
6067
6068 instruct loadSSP(rRegP dst, stackSlotP src)
6069 %{
6070 match(Set dst src);
6071
6072 ins_cost(125);
6073 format %{ "movq $dst, $src\t# ptr stk" %}
6074 opcode(0x8B);
6075 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6076 ins_pipe(ialu_reg_mem);
6077 %}
6078
6079 instruct loadSSF(regF dst, stackSlotF src)
6080 %{
6081 match(Set dst src);
6082
6083 ins_cost(125);
6084 format %{ "movss $dst, $src\t# float stk" %}
6085 ins_encode %{
6086 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
6087 %}
6088 ins_pipe(pipe_slow); // XXX
6089 %}
6090
6091 // Use the same format since predicate() can not be used here.
6092 instruct loadSSD(regD dst, stackSlotD src)
6093 %{
6094 match(Set dst src);
6095
6096 ins_cost(125);
6097 format %{ "movsd $dst, $src\t# double stk" %}
6098 ins_encode %{
6099 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6100 %}
6101 ins_pipe(pipe_slow); // XXX
6102 %}
6103
6104 // Prefetch instructions for allocation.
6105 // Must be safe to execute with invalid address (cannot fault).
6106
6107 instruct prefetchAlloc( memory mem ) %{
6108 predicate(AllocatePrefetchInstr==3);
6109 match(PrefetchAllocation mem);
6110 ins_cost(125);
6111
6112 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
6113 ins_encode %{
6114 __ prefetchw($mem$$Address);
6115 %}
6116 ins_pipe(ialu_mem);
6117 %}
6118
6119 instruct prefetchAllocNTA( memory mem ) %{
6120 predicate(AllocatePrefetchInstr==0);
6121 match(PrefetchAllocation mem);
6122 ins_cost(125);
6123
6124 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
6125 ins_encode %{
6126 __ prefetchnta($mem$$Address);
6127 %}
6128 ins_pipe(ialu_mem);
6129 %}
6130
6131 instruct prefetchAllocT0( memory mem ) %{
6132 predicate(AllocatePrefetchInstr==1);
6133 match(PrefetchAllocation mem);
6134 ins_cost(125);
6135
6136 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
6137 ins_encode %{
6138 __ prefetcht0($mem$$Address);
6139 %}
6140 ins_pipe(ialu_mem);
6141 %}
6142
6143 instruct prefetchAllocT2( memory mem ) %{
6144 predicate(AllocatePrefetchInstr==2);
6145 match(PrefetchAllocation mem);
6146 ins_cost(125);
6147
6148 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
6149 ins_encode %{
6150 __ prefetcht2($mem$$Address);
6151 %}
6152 ins_pipe(ialu_mem);
6153 %}
6154
6155 //----------Store Instructions-------------------------------------------------
6156
6157 // Store Byte
6158 instruct storeB(memory mem, rRegI src)
6159 %{
6160 match(Set mem (StoreB mem src));
6161
6162 ins_cost(125); // XXX
6163 format %{ "movb $mem, $src\t# byte" %}
6164 opcode(0x88);
6165 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6166 ins_pipe(ialu_mem_reg);
6167 %}
6168
6169 // Store Char/Short
6170 instruct storeC(memory mem, rRegI src)
6171 %{
6172 match(Set mem (StoreC mem src));
6173
6174 ins_cost(125); // XXX
6175 format %{ "movw $mem, $src\t# char/short" %}
6176 opcode(0x89);
6177 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6178 ins_pipe(ialu_mem_reg);
6179 %}
6180
6181 // Store Integer
6182 instruct storeI(memory mem, rRegI src)
6183 %{
6184 match(Set mem (StoreI mem src));
6185
6186 ins_cost(125); // XXX
6187 format %{ "movl $mem, $src\t# int" %}
6188 opcode(0x89);
6189 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6190 ins_pipe(ialu_mem_reg);
6191 %}
6192
6193 // Store Long
6194 instruct storeL(memory mem, rRegL src)
6195 %{
6196 match(Set mem (StoreL mem src));
6197
6198 ins_cost(125); // XXX
6199 format %{ "movq $mem, $src\t# long" %}
6200 opcode(0x89);
6201 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6202 ins_pipe(ialu_mem_reg); // XXX
6203 %}
6204
6205 // Store Pointer
6206 instruct storeP(memory mem, any_RegP src)
6207 %{
6208 match(Set mem (StoreP mem src));
6209
6210 ins_cost(125); // XXX
6211 format %{ "movq $mem, $src\t# ptr" %}
6212 opcode(0x89);
6213 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6214 ins_pipe(ialu_mem_reg);
6215 %}
6216
6217 instruct storeImmP0(memory mem, immP0 zero)
6218 %{
6219 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6220 match(Set mem (StoreP mem zero));
6221
6222 ins_cost(125); // XXX
6223 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6224 ins_encode %{
6225 __ movq($mem$$Address, r12);
6226 %}
6227 ins_pipe(ialu_mem_reg);
6228 %}
6229
6230 // Store NULL Pointer, mark word, or other simple pointer constant.
6231 instruct storeImmP(memory mem, immP31 src)
6232 %{
6233 match(Set mem (StoreP mem src));
6234
6235 ins_cost(150); // XXX
6236 format %{ "movq $mem, $src\t# ptr" %}
6237 opcode(0xC7); /* C7 /0 */
6238 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6239 ins_pipe(ialu_mem_imm);
6240 %}
6241
6242 // Store Compressed Pointer
6243 instruct storeN(memory mem, rRegN src)
6244 %{
6245 match(Set mem (StoreN mem src));
6246
6247 ins_cost(125); // XXX
6248 format %{ "movl $mem, $src\t# compressed ptr" %}
6249 ins_encode %{
6250 __ movl($mem$$Address, $src$$Register);
6251 %}
6252 ins_pipe(ialu_mem_reg);
6253 %}
6254
6255 instruct storeNKlass(memory mem, rRegN src)
6256 %{
6257 match(Set mem (StoreNKlass mem src));
6258
6259 ins_cost(125); // XXX
6260 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6261 ins_encode %{
6262 __ movl($mem$$Address, $src$$Register);
6263 %}
6264 ins_pipe(ialu_mem_reg);
6265 %}
6266
6267 instruct storeImmN0(memory mem, immN0 zero)
6268 %{
6269 predicate(CompressedOops::base() == NULL && CompressedKlassPointers::base() == NULL);
6270 match(Set mem (StoreN mem zero));
6271
6272 ins_cost(125); // XXX
6273 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6274 ins_encode %{
6275 __ movl($mem$$Address, r12);
6276 %}
6277 ins_pipe(ialu_mem_reg);
6278 %}
6279
6280 instruct storeImmN(memory mem, immN src)
6281 %{
6282 match(Set mem (StoreN mem src));
6283
6284 ins_cost(150); // XXX
6285 format %{ "movl $mem, $src\t# compressed ptr" %}
6286 ins_encode %{
6287 address con = (address)$src$$constant;
6288 if (con == NULL) {
6289 __ movl($mem$$Address, (int32_t)0);
6290 } else {
6291 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6292 }
6293 %}
6294 ins_pipe(ialu_mem_imm);
6295 %}
6296
6297 instruct storeImmNKlass(memory mem, immNKlass src)
6298 %{
6299 match(Set mem (StoreNKlass mem src));
6300
6301 ins_cost(150); // XXX
6302 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6303 ins_encode %{
6304 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6305 %}
6306 ins_pipe(ialu_mem_imm);
6307 %}
6308
6309 // Store Integer Immediate
6310 instruct storeImmI0(memory mem, immI0 zero)
6311 %{
6312 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6313 match(Set mem (StoreI mem zero));
6314
6315 ins_cost(125); // XXX
6316 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6317 ins_encode %{
6318 __ movl($mem$$Address, r12);
6319 %}
6320 ins_pipe(ialu_mem_reg);
6321 %}
6322
6323 instruct storeImmI(memory mem, immI src)
6324 %{
6325 match(Set mem (StoreI mem src));
6326
6327 ins_cost(150);
6328 format %{ "movl $mem, $src\t# int" %}
6329 opcode(0xC7); /* C7 /0 */
6330 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6331 ins_pipe(ialu_mem_imm);
6332 %}
6333
6334 // Store Long Immediate
6335 instruct storeImmL0(memory mem, immL0 zero)
6336 %{
6337 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6338 match(Set mem (StoreL mem zero));
6339
6340 ins_cost(125); // XXX
6341 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6342 ins_encode %{
6343 __ movq($mem$$Address, r12);
6344 %}
6345 ins_pipe(ialu_mem_reg);
6346 %}
6347
6348 instruct storeImmL(memory mem, immL32 src)
6349 %{
6350 match(Set mem (StoreL mem src));
6351
6352 ins_cost(150);
6353 format %{ "movq $mem, $src\t# long" %}
6354 opcode(0xC7); /* C7 /0 */
6355 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6356 ins_pipe(ialu_mem_imm);
6357 %}
6358
6359 // Store Short/Char Immediate
6360 instruct storeImmC0(memory mem, immI0 zero)
6361 %{
6362 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6363 match(Set mem (StoreC mem zero));
6364
6365 ins_cost(125); // XXX
6366 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6367 ins_encode %{
6368 __ movw($mem$$Address, r12);
6369 %}
6370 ins_pipe(ialu_mem_reg);
6371 %}
6372
6373 instruct storeImmI16(memory mem, immI16 src)
6374 %{
6375 predicate(UseStoreImmI16);
6376 match(Set mem (StoreC mem src));
6377
6378 ins_cost(150);
6379 format %{ "movw $mem, $src\t# short/char" %}
6380 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6381 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6382 ins_pipe(ialu_mem_imm);
6383 %}
6384
6385 // Store Byte Immediate
6386 instruct storeImmB0(memory mem, immI0 zero)
6387 %{
6388 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6389 match(Set mem (StoreB mem zero));
6390
6391 ins_cost(125); // XXX
6392 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6393 ins_encode %{
6394 __ movb($mem$$Address, r12);
6395 %}
6396 ins_pipe(ialu_mem_reg);
6397 %}
6398
6399 instruct storeImmB(memory mem, immI8 src)
6400 %{
6401 match(Set mem (StoreB mem src));
6402
6403 ins_cost(150); // XXX
6404 format %{ "movb $mem, $src\t# byte" %}
6405 opcode(0xC6); /* C6 /0 */
6406 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6407 ins_pipe(ialu_mem_imm);
6408 %}
6409
6410 // Store CMS card-mark Immediate
6411 instruct storeImmCM0_reg(memory mem, immI0 zero)
6412 %{
6413 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6414 match(Set mem (StoreCM mem zero));
6415
6416 ins_cost(125); // XXX
6417 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6418 ins_encode %{
6419 __ movb($mem$$Address, r12);
6420 %}
6421 ins_pipe(ialu_mem_reg);
6422 %}
6423
6424 instruct storeImmCM0(memory mem, immI0 src)
6425 %{
6426 match(Set mem (StoreCM mem src));
6427
6428 ins_cost(150); // XXX
6429 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6430 opcode(0xC6); /* C6 /0 */
6431 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6432 ins_pipe(ialu_mem_imm);
6433 %}
6434
6435 // Store Float
6436 instruct storeF(memory mem, regF src)
6437 %{
6438 match(Set mem (StoreF mem src));
6439
6440 ins_cost(95); // XXX
6441 format %{ "movss $mem, $src\t# float" %}
6442 ins_encode %{
6443 __ movflt($mem$$Address, $src$$XMMRegister);
6444 %}
6445 ins_pipe(pipe_slow); // XXX
6446 %}
6447
6448 // Store immediate Float value (it is faster than store from XMM register)
6449 instruct storeF0(memory mem, immF0 zero)
6450 %{
6451 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6452 match(Set mem (StoreF mem zero));
6453
6454 ins_cost(25); // XXX
6455 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6456 ins_encode %{
6457 __ movl($mem$$Address, r12);
6458 %}
6459 ins_pipe(ialu_mem_reg);
6460 %}
6461
6462 instruct storeF_imm(memory mem, immF src)
6463 %{
6464 match(Set mem (StoreF mem src));
6465
6466 ins_cost(50);
6467 format %{ "movl $mem, $src\t# float" %}
6468 opcode(0xC7); /* C7 /0 */
6469 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6470 ins_pipe(ialu_mem_imm);
6471 %}
6472
6473 // Store Double
6474 instruct storeD(memory mem, regD src)
6475 %{
6476 match(Set mem (StoreD mem src));
6477
6478 ins_cost(95); // XXX
6479 format %{ "movsd $mem, $src\t# double" %}
6480 ins_encode %{
6481 __ movdbl($mem$$Address, $src$$XMMRegister);
6482 %}
6483 ins_pipe(pipe_slow); // XXX
6484 %}
6485
6486 // Store immediate double 0.0 (it is faster than store from XMM register)
6487 instruct storeD0_imm(memory mem, immD0 src)
6488 %{
6489 predicate(!UseCompressedOops || (CompressedOops::base() != NULL));
6490 match(Set mem (StoreD mem src));
6491
6492 ins_cost(50);
6493 format %{ "movq $mem, $src\t# double 0." %}
6494 opcode(0xC7); /* C7 /0 */
6495 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6496 ins_pipe(ialu_mem_imm);
6497 %}
6498
6499 instruct storeD0(memory mem, immD0 zero)
6500 %{
6501 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6502 match(Set mem (StoreD mem zero));
6503
6504 ins_cost(25); // XXX
6505 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6506 ins_encode %{
6507 __ movq($mem$$Address, r12);
6508 %}
6509 ins_pipe(ialu_mem_reg);
6510 %}
6511
6512 instruct storeSSI(stackSlotI dst, rRegI src)
6513 %{
6514 match(Set dst src);
6515
6516 ins_cost(100);
6517 format %{ "movl $dst, $src\t# int stk" %}
6518 opcode(0x89);
6519 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6520 ins_pipe( ialu_mem_reg );
6521 %}
6522
6523 instruct storeSSL(stackSlotL dst, rRegL src)
6524 %{
6525 match(Set dst src);
6526
6527 ins_cost(100);
6528 format %{ "movq $dst, $src\t# long stk" %}
6529 opcode(0x89);
6530 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6531 ins_pipe(ialu_mem_reg);
6532 %}
6533
6534 instruct storeSSP(stackSlotP dst, rRegP src)
6535 %{
6536 match(Set dst src);
6537
6538 ins_cost(100);
6539 format %{ "movq $dst, $src\t# ptr stk" %}
6540 opcode(0x89);
6541 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6542 ins_pipe(ialu_mem_reg);
6543 %}
6544
6545 instruct storeSSF(stackSlotF dst, regF src)
6546 %{
6547 match(Set dst src);
6548
6549 ins_cost(95); // XXX
6550 format %{ "movss $dst, $src\t# float stk" %}
6551 ins_encode %{
6552 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6553 %}
6554 ins_pipe(pipe_slow); // XXX
6555 %}
6556
6557 instruct storeSSD(stackSlotD dst, regD src)
6558 %{
6559 match(Set dst src);
6560
6561 ins_cost(95); // XXX
6562 format %{ "movsd $dst, $src\t# double stk" %}
6563 ins_encode %{
6564 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6565 %}
6566 ins_pipe(pipe_slow); // XXX
6567 %}
6568
6569 //----------BSWAP Instructions-------------------------------------------------
6570 instruct bytes_reverse_int(rRegI dst) %{
6571 match(Set dst (ReverseBytesI dst));
6572
6573 format %{ "bswapl $dst" %}
6574 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6575 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6576 ins_pipe( ialu_reg );
6577 %}
6578
6579 instruct bytes_reverse_long(rRegL dst) %{
6580 match(Set dst (ReverseBytesL dst));
6581
6582 format %{ "bswapq $dst" %}
6583 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6584 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6585 ins_pipe( ialu_reg);
6586 %}
6587
6588 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6589 match(Set dst (ReverseBytesUS dst));
6590 effect(KILL cr);
6591
6592 format %{ "bswapl $dst\n\t"
6593 "shrl $dst,16\n\t" %}
6594 ins_encode %{
6595 __ bswapl($dst$$Register);
6596 __ shrl($dst$$Register, 16);
6597 %}
6598 ins_pipe( ialu_reg );
6599 %}
6600
6601 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6602 match(Set dst (ReverseBytesS dst));
6603 effect(KILL cr);
6604
6605 format %{ "bswapl $dst\n\t"
6606 "sar $dst,16\n\t" %}
6607 ins_encode %{
6608 __ bswapl($dst$$Register);
6609 __ sarl($dst$$Register, 16);
6610 %}
6611 ins_pipe( ialu_reg );
6612 %}
6613
6614 //---------- Zeros Count Instructions ------------------------------------------
6615
6616 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6617 predicate(UseCountLeadingZerosInstruction);
6618 match(Set dst (CountLeadingZerosI src));
6619 effect(KILL cr);
6620
6621 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6622 ins_encode %{
6623 __ lzcntl($dst$$Register, $src$$Register);
6624 %}
6625 ins_pipe(ialu_reg);
6626 %}
6627
6628 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6629 predicate(!UseCountLeadingZerosInstruction);
6630 match(Set dst (CountLeadingZerosI src));
6631 effect(KILL cr);
6632
6633 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6634 "jnz skip\n\t"
6635 "movl $dst, -1\n"
6636 "skip:\n\t"
6637 "negl $dst\n\t"
6638 "addl $dst, 31" %}
6639 ins_encode %{
6640 Register Rdst = $dst$$Register;
6641 Register Rsrc = $src$$Register;
6642 Label skip;
6643 __ bsrl(Rdst, Rsrc);
6644 __ jccb(Assembler::notZero, skip);
6645 __ movl(Rdst, -1);
6646 __ bind(skip);
6647 __ negl(Rdst);
6648 __ addl(Rdst, BitsPerInt - 1);
6649 %}
6650 ins_pipe(ialu_reg);
6651 %}
6652
6653 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6654 predicate(UseCountLeadingZerosInstruction);
6655 match(Set dst (CountLeadingZerosL src));
6656 effect(KILL cr);
6657
6658 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6659 ins_encode %{
6660 __ lzcntq($dst$$Register, $src$$Register);
6661 %}
6662 ins_pipe(ialu_reg);
6663 %}
6664
6665 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6666 predicate(!UseCountLeadingZerosInstruction);
6667 match(Set dst (CountLeadingZerosL src));
6668 effect(KILL cr);
6669
6670 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6671 "jnz skip\n\t"
6672 "movl $dst, -1\n"
6673 "skip:\n\t"
6674 "negl $dst\n\t"
6675 "addl $dst, 63" %}
6676 ins_encode %{
6677 Register Rdst = $dst$$Register;
6678 Register Rsrc = $src$$Register;
6679 Label skip;
6680 __ bsrq(Rdst, Rsrc);
6681 __ jccb(Assembler::notZero, skip);
6682 __ movl(Rdst, -1);
6683 __ bind(skip);
6684 __ negl(Rdst);
6685 __ addl(Rdst, BitsPerLong - 1);
6686 %}
6687 ins_pipe(ialu_reg);
6688 %}
6689
6690 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6691 predicate(UseCountTrailingZerosInstruction);
6692 match(Set dst (CountTrailingZerosI src));
6693 effect(KILL cr);
6694
6695 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6696 ins_encode %{
6697 __ tzcntl($dst$$Register, $src$$Register);
6698 %}
6699 ins_pipe(ialu_reg);
6700 %}
6701
6702 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6703 predicate(!UseCountTrailingZerosInstruction);
6704 match(Set dst (CountTrailingZerosI src));
6705 effect(KILL cr);
6706
6707 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6708 "jnz done\n\t"
6709 "movl $dst, 32\n"
6710 "done:" %}
6711 ins_encode %{
6712 Register Rdst = $dst$$Register;
6713 Label done;
6714 __ bsfl(Rdst, $src$$Register);
6715 __ jccb(Assembler::notZero, done);
6716 __ movl(Rdst, BitsPerInt);
6717 __ bind(done);
6718 %}
6719 ins_pipe(ialu_reg);
6720 %}
6721
6722 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6723 predicate(UseCountTrailingZerosInstruction);
6724 match(Set dst (CountTrailingZerosL src));
6725 effect(KILL cr);
6726
6727 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6728 ins_encode %{
6729 __ tzcntq($dst$$Register, $src$$Register);
6730 %}
6731 ins_pipe(ialu_reg);
6732 %}
6733
6734 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6735 predicate(!UseCountTrailingZerosInstruction);
6736 match(Set dst (CountTrailingZerosL src));
6737 effect(KILL cr);
6738
6739 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6740 "jnz done\n\t"
6741 "movl $dst, 64\n"
6742 "done:" %}
6743 ins_encode %{
6744 Register Rdst = $dst$$Register;
6745 Label done;
6746 __ bsfq(Rdst, $src$$Register);
6747 __ jccb(Assembler::notZero, done);
6748 __ movl(Rdst, BitsPerLong);
6749 __ bind(done);
6750 %}
6751 ins_pipe(ialu_reg);
6752 %}
6753
6754
6755 //---------- Population Count Instructions -------------------------------------
6756
6757 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6758 predicate(UsePopCountInstruction);
6759 match(Set dst (PopCountI src));
6760 effect(KILL cr);
6761
6762 format %{ "popcnt $dst, $src" %}
6763 ins_encode %{
6764 __ popcntl($dst$$Register, $src$$Register);
6765 %}
6766 ins_pipe(ialu_reg);
6767 %}
6768
6769 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6770 predicate(UsePopCountInstruction);
6771 match(Set dst (PopCountI (LoadI mem)));
6772 effect(KILL cr);
6773
6774 format %{ "popcnt $dst, $mem" %}
6775 ins_encode %{
6776 __ popcntl($dst$$Register, $mem$$Address);
6777 %}
6778 ins_pipe(ialu_reg);
6779 %}
6780
6781 // Note: Long.bitCount(long) returns an int.
6782 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6783 predicate(UsePopCountInstruction);
6784 match(Set dst (PopCountL src));
6785 effect(KILL cr);
6786
6787 format %{ "popcnt $dst, $src" %}
6788 ins_encode %{
6789 __ popcntq($dst$$Register, $src$$Register);
6790 %}
6791 ins_pipe(ialu_reg);
6792 %}
6793
6794 // Note: Long.bitCount(long) returns an int.
6795 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6796 predicate(UsePopCountInstruction);
6797 match(Set dst (PopCountL (LoadL mem)));
6798 effect(KILL cr);
6799
6800 format %{ "popcnt $dst, $mem" %}
6801 ins_encode %{
6802 __ popcntq($dst$$Register, $mem$$Address);
6803 %}
6804 ins_pipe(ialu_reg);
6805 %}
6806
6807
6808 //----------MemBar Instructions-----------------------------------------------
6809 // Memory barrier flavors
6810
6811 instruct membar_acquire()
6812 %{
6813 match(MemBarAcquire);
6814 match(LoadFence);
6815 ins_cost(0);
6816
6817 size(0);
6818 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6819 ins_encode();
6820 ins_pipe(empty);
6821 %}
6822
6823 instruct membar_acquire_lock()
6824 %{
6825 match(MemBarAcquireLock);
6826 ins_cost(0);
6827
6828 size(0);
6829 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6830 ins_encode();
6831 ins_pipe(empty);
6832 %}
6833
6834 instruct membar_release()
6835 %{
6836 match(MemBarRelease);
6837 match(StoreFence);
6838 ins_cost(0);
6839
6840 size(0);
6841 format %{ "MEMBAR-release ! (empty encoding)" %}
6842 ins_encode();
6843 ins_pipe(empty);
6844 %}
6845
6846 instruct membar_release_lock()
6847 %{
6848 match(MemBarReleaseLock);
6849 ins_cost(0);
6850
6851 size(0);
6852 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6853 ins_encode();
6854 ins_pipe(empty);
6855 %}
6856
6857 instruct membar_volatile(rFlagsReg cr) %{
6858 match(MemBarVolatile);
6859 effect(KILL cr);
6860 ins_cost(400);
6861
6862 format %{
6863 $$template
6864 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6865 %}
6866 ins_encode %{
6867 __ membar(Assembler::StoreLoad);
6868 %}
6869 ins_pipe(pipe_slow);
6870 %}
6871
6872 instruct unnecessary_membar_volatile()
6873 %{
6874 match(MemBarVolatile);
6875 predicate(Matcher::post_store_load_barrier(n));
6876 ins_cost(0);
6877
6878 size(0);
6879 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6880 ins_encode();
6881 ins_pipe(empty);
6882 %}
6883
6884 instruct membar_storestore() %{
6885 match(MemBarStoreStore);
6886 ins_cost(0);
6887
6888 size(0);
6889 format %{ "MEMBAR-storestore (empty encoding)" %}
6890 ins_encode( );
6891 ins_pipe(empty);
6892 %}
6893
6894 //----------Move Instructions--------------------------------------------------
6895
6896 instruct castX2P(rRegP dst, rRegL src)
6897 %{
6898 match(Set dst (CastX2P src));
6899
6900 format %{ "movq $dst, $src\t# long->ptr" %}
6901 ins_encode %{
6902 if ($dst$$reg != $src$$reg) {
6903 __ movptr($dst$$Register, $src$$Register);
6904 }
6905 %}
6906 ins_pipe(ialu_reg_reg); // XXX
6907 %}
6908
6909 instruct castP2X(rRegL dst, rRegP src)
6910 %{
6911 match(Set dst (CastP2X src));
6912
6913 format %{ "movq $dst, $src\t# ptr -> long" %}
6914 ins_encode %{
6915 if ($dst$$reg != $src$$reg) {
6916 __ movptr($dst$$Register, $src$$Register);
6917 }
6918 %}
6919 ins_pipe(ialu_reg_reg); // XXX
6920 %}
6921
6922 // Convert oop into int for vectors alignment masking
6923 instruct convP2I(rRegI dst, rRegP src)
6924 %{
6925 match(Set dst (ConvL2I (CastP2X src)));
6926
6927 format %{ "movl $dst, $src\t# ptr -> int" %}
6928 ins_encode %{
6929 __ movl($dst$$Register, $src$$Register);
6930 %}
6931 ins_pipe(ialu_reg_reg); // XXX
6932 %}
6933
6934 // Convert compressed oop into int for vectors alignment masking
6935 // in case of 32bit oops (heap < 4Gb).
6936 instruct convN2I(rRegI dst, rRegN src)
6937 %{
6938 predicate(CompressedOops::shift() == 0);
6939 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6940
6941 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6942 ins_encode %{
6943 __ movl($dst$$Register, $src$$Register);
6944 %}
6945 ins_pipe(ialu_reg_reg); // XXX
6946 %}
6947
6948 // Convert oop pointer into compressed form
6949 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6950 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6951 match(Set dst (EncodeP src));
6952 effect(KILL cr);
6953 format %{ "encode_heap_oop $dst,$src" %}
6954 ins_encode %{
6955 Register s = $src$$Register;
6956 Register d = $dst$$Register;
6957 if (s != d) {
6958 __ movq(d, s);
6959 }
6960 __ encode_heap_oop(d);
6961 %}
6962 ins_pipe(ialu_reg_long);
6963 %}
6964
6965 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6966 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6967 match(Set dst (EncodeP src));
6968 effect(KILL cr);
6969 format %{ "encode_heap_oop_not_null $dst,$src" %}
6970 ins_encode %{
6971 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6972 %}
6973 ins_pipe(ialu_reg_long);
6974 %}
6975
6976 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6977 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6978 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6979 match(Set dst (DecodeN src));
6980 effect(KILL cr);
6981 format %{ "decode_heap_oop $dst,$src" %}
6982 ins_encode %{
6983 Register s = $src$$Register;
6984 Register d = $dst$$Register;
6985 if (s != d) {
6986 __ movq(d, s);
6987 }
6988 __ decode_heap_oop(d);
6989 %}
6990 ins_pipe(ialu_reg_long);
6991 %}
6992
6993 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6994 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6995 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6996 match(Set dst (DecodeN src));
6997 effect(KILL cr);
6998 format %{ "decode_heap_oop_not_null $dst,$src" %}
6999 ins_encode %{
7000 Register s = $src$$Register;
7001 Register d = $dst$$Register;
7002 if (s != d) {
7003 __ decode_heap_oop_not_null(d, s);
7004 } else {
7005 __ decode_heap_oop_not_null(d);
7006 }
7007 %}
7008 ins_pipe(ialu_reg_long);
7009 %}
7010
7011 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
7012 match(Set dst (EncodePKlass src));
7013 effect(KILL cr);
7014 format %{ "encode_klass_not_null $dst,$src" %}
7015 ins_encode %{
7016 __ encode_klass_not_null($dst$$Register, $src$$Register);
7017 %}
7018 ins_pipe(ialu_reg_long);
7019 %}
7020
7021 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
7022 match(Set dst (DecodeNKlass src));
7023 effect(KILL cr);
7024 format %{ "decode_klass_not_null $dst,$src" %}
7025 ins_encode %{
7026 Register s = $src$$Register;
7027 Register d = $dst$$Register;
7028 if (s != d) {
7029 __ decode_klass_not_null(d, s);
7030 } else {
7031 __ decode_klass_not_null(d);
7032 }
7033 %}
7034 ins_pipe(ialu_reg_long);
7035 %}
7036
7037
7038 //----------Conditional Move---------------------------------------------------
7039 // Jump
7040 // dummy instruction for generating temp registers
7041 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7042 match(Jump (LShiftL switch_val shift));
7043 ins_cost(350);
7044 predicate(false);
7045 effect(TEMP dest);
7046
7047 format %{ "leaq $dest, [$constantaddress]\n\t"
7048 "jmp [$dest + $switch_val << $shift]\n\t" %}
7049 ins_encode %{
7050 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7051 // to do that and the compiler is using that register as one it can allocate.
7052 // So we build it all by hand.
7053 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
7054 // ArrayAddress dispatch(table, index);
7055 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
7056 __ lea($dest$$Register, $constantaddress);
7057 __ jmp(dispatch);
7058 %}
7059 ins_pipe(pipe_jmp);
7060 %}
7061
7062 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
7063 match(Jump (AddL (LShiftL switch_val shift) offset));
7064 ins_cost(350);
7065 effect(TEMP dest);
7066
7067 format %{ "leaq $dest, [$constantaddress]\n\t"
7068 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
7069 ins_encode %{
7070 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7071 // to do that and the compiler is using that register as one it can allocate.
7072 // So we build it all by hand.
7073 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
7074 // ArrayAddress dispatch(table, index);
7075 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
7076 __ lea($dest$$Register, $constantaddress);
7077 __ jmp(dispatch);
7078 %}
7079 ins_pipe(pipe_jmp);
7080 %}
7081
7082 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
7083 match(Jump switch_val);
7084 ins_cost(350);
7085 effect(TEMP dest);
7086
7087 format %{ "leaq $dest, [$constantaddress]\n\t"
7088 "jmp [$dest + $switch_val]\n\t" %}
7089 ins_encode %{
7090 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7091 // to do that and the compiler is using that register as one it can allocate.
7092 // So we build it all by hand.
7093 // Address index(noreg, switch_reg, Address::times_1);
7094 // ArrayAddress dispatch(table, index);
7095 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
7096 __ lea($dest$$Register, $constantaddress);
7097 __ jmp(dispatch);
7098 %}
7099 ins_pipe(pipe_jmp);
7100 %}
7101
7102 // Conditional move
7103 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
7104 %{
7105 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7106
7107 ins_cost(200); // XXX
7108 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7109 opcode(0x0F, 0x40);
7110 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7111 ins_pipe(pipe_cmov_reg);
7112 %}
7113
7114 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
7115 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7116
7117 ins_cost(200); // XXX
7118 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7119 opcode(0x0F, 0x40);
7120 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7121 ins_pipe(pipe_cmov_reg);
7122 %}
7123
7124 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7125 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7126 ins_cost(200);
7127 expand %{
7128 cmovI_regU(cop, cr, dst, src);
7129 %}
7130 %}
7131
7132 // Conditional move
7133 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7134 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7135
7136 ins_cost(250); // XXX
7137 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7138 opcode(0x0F, 0x40);
7139 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7140 ins_pipe(pipe_cmov_mem);
7141 %}
7142
7143 // Conditional move
7144 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7145 %{
7146 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7147
7148 ins_cost(250); // XXX
7149 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7150 opcode(0x0F, 0x40);
7151 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7152 ins_pipe(pipe_cmov_mem);
7153 %}
7154
7155 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7156 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7157 ins_cost(250);
7158 expand %{
7159 cmovI_memU(cop, cr, dst, src);
7160 %}
7161 %}
7162
7163 // Conditional move
7164 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7165 %{
7166 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7167
7168 ins_cost(200); // XXX
7169 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7170 opcode(0x0F, 0x40);
7171 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7172 ins_pipe(pipe_cmov_reg);
7173 %}
7174
7175 // Conditional move
7176 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7177 %{
7178 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7179
7180 ins_cost(200); // XXX
7181 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7182 opcode(0x0F, 0x40);
7183 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7184 ins_pipe(pipe_cmov_reg);
7185 %}
7186
7187 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7188 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7189 ins_cost(200);
7190 expand %{
7191 cmovN_regU(cop, cr, dst, src);
7192 %}
7193 %}
7194
7195 // Conditional move
7196 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7197 %{
7198 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7199
7200 ins_cost(200); // XXX
7201 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7202 opcode(0x0F, 0x40);
7203 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7204 ins_pipe(pipe_cmov_reg); // XXX
7205 %}
7206
7207 // Conditional move
7208 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7209 %{
7210 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7211
7212 ins_cost(200); // XXX
7213 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7214 opcode(0x0F, 0x40);
7215 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7216 ins_pipe(pipe_cmov_reg); // XXX
7217 %}
7218
7219 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7220 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7221 ins_cost(200);
7222 expand %{
7223 cmovP_regU(cop, cr, dst, src);
7224 %}
7225 %}
7226
7227 // DISABLED: Requires the ADLC to emit a bottom_type call that
7228 // correctly meets the two pointer arguments; one is an incoming
7229 // register but the other is a memory operand. ALSO appears to
7230 // be buggy with implicit null checks.
7231 //
7232 //// Conditional move
7233 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7234 //%{
7235 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7236 // ins_cost(250);
7237 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7238 // opcode(0x0F,0x40);
7239 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7240 // ins_pipe( pipe_cmov_mem );
7241 //%}
7242 //
7243 //// Conditional move
7244 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7245 //%{
7246 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7247 // ins_cost(250);
7248 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7249 // opcode(0x0F,0x40);
7250 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7251 // ins_pipe( pipe_cmov_mem );
7252 //%}
7253
7254 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7255 %{
7256 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7257
7258 ins_cost(200); // XXX
7259 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7260 opcode(0x0F, 0x40);
7261 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7262 ins_pipe(pipe_cmov_reg); // XXX
7263 %}
7264
7265 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7266 %{
7267 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7268
7269 ins_cost(200); // XXX
7270 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7271 opcode(0x0F, 0x40);
7272 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7273 ins_pipe(pipe_cmov_mem); // XXX
7274 %}
7275
7276 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7277 %{
7278 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7279
7280 ins_cost(200); // XXX
7281 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7282 opcode(0x0F, 0x40);
7283 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7284 ins_pipe(pipe_cmov_reg); // XXX
7285 %}
7286
7287 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7288 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7289 ins_cost(200);
7290 expand %{
7291 cmovL_regU(cop, cr, dst, src);
7292 %}
7293 %}
7294
7295 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7296 %{
7297 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7298
7299 ins_cost(200); // XXX
7300 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7301 opcode(0x0F, 0x40);
7302 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7303 ins_pipe(pipe_cmov_mem); // XXX
7304 %}
7305
7306 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7307 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7308 ins_cost(200);
7309 expand %{
7310 cmovL_memU(cop, cr, dst, src);
7311 %}
7312 %}
7313
7314 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7315 %{
7316 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7317
7318 ins_cost(200); // XXX
7319 format %{ "jn$cop skip\t# signed cmove float\n\t"
7320 "movss $dst, $src\n"
7321 "skip:" %}
7322 ins_encode %{
7323 Label Lskip;
7324 // Invert sense of branch from sense of CMOV
7325 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7326 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7327 __ bind(Lskip);
7328 %}
7329 ins_pipe(pipe_slow);
7330 %}
7331
7332 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7333 // %{
7334 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7335
7336 // ins_cost(200); // XXX
7337 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7338 // "movss $dst, $src\n"
7339 // "skip:" %}
7340 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7341 // ins_pipe(pipe_slow);
7342 // %}
7343
7344 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7345 %{
7346 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7347
7348 ins_cost(200); // XXX
7349 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7350 "movss $dst, $src\n"
7351 "skip:" %}
7352 ins_encode %{
7353 Label Lskip;
7354 // Invert sense of branch from sense of CMOV
7355 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7356 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7357 __ bind(Lskip);
7358 %}
7359 ins_pipe(pipe_slow);
7360 %}
7361
7362 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7363 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7364 ins_cost(200);
7365 expand %{
7366 cmovF_regU(cop, cr, dst, src);
7367 %}
7368 %}
7369
7370 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7371 %{
7372 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7373
7374 ins_cost(200); // XXX
7375 format %{ "jn$cop skip\t# signed cmove double\n\t"
7376 "movsd $dst, $src\n"
7377 "skip:" %}
7378 ins_encode %{
7379 Label Lskip;
7380 // Invert sense of branch from sense of CMOV
7381 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7382 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7383 __ bind(Lskip);
7384 %}
7385 ins_pipe(pipe_slow);
7386 %}
7387
7388 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7389 %{
7390 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7391
7392 ins_cost(200); // XXX
7393 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7394 "movsd $dst, $src\n"
7395 "skip:" %}
7396 ins_encode %{
7397 Label Lskip;
7398 // Invert sense of branch from sense of CMOV
7399 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7400 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7401 __ bind(Lskip);
7402 %}
7403 ins_pipe(pipe_slow);
7404 %}
7405
7406 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7407 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7408 ins_cost(200);
7409 expand %{
7410 cmovD_regU(cop, cr, dst, src);
7411 %}
7412 %}
7413
7414 //----------Arithmetic Instructions--------------------------------------------
7415 //----------Addition Instructions----------------------------------------------
7416
7417 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7418 %{
7419 match(Set dst (AddI dst src));
7420 effect(KILL cr);
7421
7422 format %{ "addl $dst, $src\t# int" %}
7423 opcode(0x03);
7424 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7425 ins_pipe(ialu_reg_reg);
7426 %}
7427
7428 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7429 %{
7430 match(Set dst (AddI dst src));
7431 effect(KILL cr);
7432
7433 format %{ "addl $dst, $src\t# int" %}
7434 opcode(0x81, 0x00); /* /0 id */
7435 ins_encode(OpcSErm(dst, src), Con8or32(src));
7436 ins_pipe( ialu_reg );
7437 %}
7438
7439 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7440 %{
7441 match(Set dst (AddI dst (LoadI src)));
7442 effect(KILL cr);
7443
7444 ins_cost(125); // XXX
7445 format %{ "addl $dst, $src\t# int" %}
7446 opcode(0x03);
7447 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7448 ins_pipe(ialu_reg_mem);
7449 %}
7450
7451 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7452 %{
7453 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7454 effect(KILL cr);
7455
7456 ins_cost(150); // XXX
7457 format %{ "addl $dst, $src\t# int" %}
7458 opcode(0x01); /* Opcode 01 /r */
7459 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7460 ins_pipe(ialu_mem_reg);
7461 %}
7462
7463 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7464 %{
7465 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7466 effect(KILL cr);
7467
7468 ins_cost(125); // XXX
7469 format %{ "addl $dst, $src\t# int" %}
7470 opcode(0x81); /* Opcode 81 /0 id */
7471 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7472 ins_pipe(ialu_mem_imm);
7473 %}
7474
7475 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7476 %{
7477 predicate(UseIncDec);
7478 match(Set dst (AddI dst src));
7479 effect(KILL cr);
7480
7481 format %{ "incl $dst\t# int" %}
7482 opcode(0xFF, 0x00); // FF /0
7483 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7484 ins_pipe(ialu_reg);
7485 %}
7486
7487 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7488 %{
7489 predicate(UseIncDec);
7490 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7491 effect(KILL cr);
7492
7493 ins_cost(125); // XXX
7494 format %{ "incl $dst\t# int" %}
7495 opcode(0xFF); /* Opcode FF /0 */
7496 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7497 ins_pipe(ialu_mem_imm);
7498 %}
7499
7500 // XXX why does that use AddI
7501 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7502 %{
7503 predicate(UseIncDec);
7504 match(Set dst (AddI dst src));
7505 effect(KILL cr);
7506
7507 format %{ "decl $dst\t# int" %}
7508 opcode(0xFF, 0x01); // FF /1
7509 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7510 ins_pipe(ialu_reg);
7511 %}
7512
7513 // XXX why does that use AddI
7514 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7515 %{
7516 predicate(UseIncDec);
7517 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7518 effect(KILL cr);
7519
7520 ins_cost(125); // XXX
7521 format %{ "decl $dst\t# int" %}
7522 opcode(0xFF); /* Opcode FF /1 */
7523 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7524 ins_pipe(ialu_mem_imm);
7525 %}
7526
7527 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7528 %{
7529 match(Set dst (AddI src0 src1));
7530
7531 ins_cost(110);
7532 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7533 opcode(0x8D); /* 0x8D /r */
7534 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7535 ins_pipe(ialu_reg_reg);
7536 %}
7537
7538 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7539 %{
7540 match(Set dst (AddL dst src));
7541 effect(KILL cr);
7542
7543 format %{ "addq $dst, $src\t# long" %}
7544 opcode(0x03);
7545 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7546 ins_pipe(ialu_reg_reg);
7547 %}
7548
7549 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7550 %{
7551 match(Set dst (AddL dst src));
7552 effect(KILL cr);
7553
7554 format %{ "addq $dst, $src\t# long" %}
7555 opcode(0x81, 0x00); /* /0 id */
7556 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7557 ins_pipe( ialu_reg );
7558 %}
7559
7560 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7561 %{
7562 match(Set dst (AddL dst (LoadL src)));
7563 effect(KILL cr);
7564
7565 ins_cost(125); // XXX
7566 format %{ "addq $dst, $src\t# long" %}
7567 opcode(0x03);
7568 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7569 ins_pipe(ialu_reg_mem);
7570 %}
7571
7572 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7573 %{
7574 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7575 effect(KILL cr);
7576
7577 ins_cost(150); // XXX
7578 format %{ "addq $dst, $src\t# long" %}
7579 opcode(0x01); /* Opcode 01 /r */
7580 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7581 ins_pipe(ialu_mem_reg);
7582 %}
7583
7584 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7585 %{
7586 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7587 effect(KILL cr);
7588
7589 ins_cost(125); // XXX
7590 format %{ "addq $dst, $src\t# long" %}
7591 opcode(0x81); /* Opcode 81 /0 id */
7592 ins_encode(REX_mem_wide(dst),
7593 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7594 ins_pipe(ialu_mem_imm);
7595 %}
7596
7597 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7598 %{
7599 predicate(UseIncDec);
7600 match(Set dst (AddL dst src));
7601 effect(KILL cr);
7602
7603 format %{ "incq $dst\t# long" %}
7604 opcode(0xFF, 0x00); // FF /0
7605 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7606 ins_pipe(ialu_reg);
7607 %}
7608
7609 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7610 %{
7611 predicate(UseIncDec);
7612 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7613 effect(KILL cr);
7614
7615 ins_cost(125); // XXX
7616 format %{ "incq $dst\t# long" %}
7617 opcode(0xFF); /* Opcode FF /0 */
7618 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7619 ins_pipe(ialu_mem_imm);
7620 %}
7621
7622 // XXX why does that use AddL
7623 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7624 %{
7625 predicate(UseIncDec);
7626 match(Set dst (AddL dst src));
7627 effect(KILL cr);
7628
7629 format %{ "decq $dst\t# long" %}
7630 opcode(0xFF, 0x01); // FF /1
7631 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7632 ins_pipe(ialu_reg);
7633 %}
7634
7635 // XXX why does that use AddL
7636 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7637 %{
7638 predicate(UseIncDec);
7639 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7640 effect(KILL cr);
7641
7642 ins_cost(125); // XXX
7643 format %{ "decq $dst\t# long" %}
7644 opcode(0xFF); /* Opcode FF /1 */
7645 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7646 ins_pipe(ialu_mem_imm);
7647 %}
7648
7649 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7650 %{
7651 match(Set dst (AddL src0 src1));
7652
7653 ins_cost(110);
7654 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7655 opcode(0x8D); /* 0x8D /r */
7656 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7657 ins_pipe(ialu_reg_reg);
7658 %}
7659
7660 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7661 %{
7662 match(Set dst (AddP dst src));
7663 effect(KILL cr);
7664
7665 format %{ "addq $dst, $src\t# ptr" %}
7666 opcode(0x03);
7667 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7668 ins_pipe(ialu_reg_reg);
7669 %}
7670
7671 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7672 %{
7673 match(Set dst (AddP dst src));
7674 effect(KILL cr);
7675
7676 format %{ "addq $dst, $src\t# ptr" %}
7677 opcode(0x81, 0x00); /* /0 id */
7678 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7679 ins_pipe( ialu_reg );
7680 %}
7681
7682 // XXX addP mem ops ????
7683
7684 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7685 %{
7686 match(Set dst (AddP src0 src1));
7687
7688 ins_cost(110);
7689 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7690 opcode(0x8D); /* 0x8D /r */
7691 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7692 ins_pipe(ialu_reg_reg);
7693 %}
7694
7695 instruct checkCastPP(rRegP dst)
7696 %{
7697 match(Set dst (CheckCastPP dst));
7698
7699 size(0);
7700 format %{ "# checkcastPP of $dst" %}
7701 ins_encode(/* empty encoding */);
7702 ins_pipe(empty);
7703 %}
7704
7705 instruct castPP(rRegP dst)
7706 %{
7707 match(Set dst (CastPP dst));
7708
7709 size(0);
7710 format %{ "# castPP of $dst" %}
7711 ins_encode(/* empty encoding */);
7712 ins_pipe(empty);
7713 %}
7714
7715 instruct castII(rRegI dst)
7716 %{
7717 match(Set dst (CastII dst));
7718
7719 size(0);
7720 format %{ "# castII of $dst" %}
7721 ins_encode(/* empty encoding */);
7722 ins_cost(0);
7723 ins_pipe(empty);
7724 %}
7725
7726 // LoadP-locked same as a regular LoadP when used with compare-swap
7727 instruct loadPLocked(rRegP dst, memory mem)
7728 %{
7729 match(Set dst (LoadPLocked mem));
7730
7731 ins_cost(125); // XXX
7732 format %{ "movq $dst, $mem\t# ptr locked" %}
7733 opcode(0x8B);
7734 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7735 ins_pipe(ialu_reg_mem); // XXX
7736 %}
7737
7738 // Conditional-store of the updated heap-top.
7739 // Used during allocation of the shared heap.
7740 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7741
7742 instruct storePConditional(memory heap_top_ptr,
7743 rax_RegP oldval, rRegP newval,
7744 rFlagsReg cr)
7745 %{
7746 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7747
7748 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7749 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7750 opcode(0x0F, 0xB1);
7751 ins_encode(lock_prefix,
7752 REX_reg_mem_wide(newval, heap_top_ptr),
7753 OpcP, OpcS,
7754 reg_mem(newval, heap_top_ptr));
7755 ins_pipe(pipe_cmpxchg);
7756 %}
7757
7758 // Conditional-store of an int value.
7759 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7760 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7761 %{
7762 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7763 effect(KILL oldval);
7764
7765 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7766 opcode(0x0F, 0xB1);
7767 ins_encode(lock_prefix,
7768 REX_reg_mem(newval, mem),
7769 OpcP, OpcS,
7770 reg_mem(newval, mem));
7771 ins_pipe(pipe_cmpxchg);
7772 %}
7773
7774 // Conditional-store of a long value.
7775 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7776 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7777 %{
7778 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7779 effect(KILL oldval);
7780
7781 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7782 opcode(0x0F, 0xB1);
7783 ins_encode(lock_prefix,
7784 REX_reg_mem_wide(newval, mem),
7785 OpcP, OpcS,
7786 reg_mem(newval, mem));
7787 ins_pipe(pipe_cmpxchg);
7788 %}
7789
7790
7791 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7792 instruct compareAndSwapP(rRegI res,
7793 memory mem_ptr,
7794 rax_RegP oldval, rRegP newval,
7795 rFlagsReg cr)
7796 %{
7797 predicate(VM_Version::supports_cx8());
7798 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7799 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7800 effect(KILL cr, KILL oldval);
7801
7802 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7803 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7804 "sete $res\n\t"
7805 "movzbl $res, $res" %}
7806 opcode(0x0F, 0xB1);
7807 ins_encode(lock_prefix,
7808 REX_reg_mem_wide(newval, mem_ptr),
7809 OpcP, OpcS,
7810 reg_mem(newval, mem_ptr),
7811 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7812 REX_reg_breg(res, res), // movzbl
7813 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7814 ins_pipe( pipe_cmpxchg );
7815 %}
7816
7817 instruct compareAndSwapL(rRegI res,
7818 memory mem_ptr,
7819 rax_RegL oldval, rRegL newval,
7820 rFlagsReg cr)
7821 %{
7822 predicate(VM_Version::supports_cx8());
7823 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7824 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7825 effect(KILL cr, KILL oldval);
7826
7827 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7828 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7829 "sete $res\n\t"
7830 "movzbl $res, $res" %}
7831 opcode(0x0F, 0xB1);
7832 ins_encode(lock_prefix,
7833 REX_reg_mem_wide(newval, mem_ptr),
7834 OpcP, OpcS,
7835 reg_mem(newval, mem_ptr),
7836 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7837 REX_reg_breg(res, res), // movzbl
7838 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7839 ins_pipe( pipe_cmpxchg );
7840 %}
7841
7842 instruct compareAndSwapI(rRegI res,
7843 memory mem_ptr,
7844 rax_RegI oldval, rRegI newval,
7845 rFlagsReg cr)
7846 %{
7847 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7848 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7849 effect(KILL cr, KILL oldval);
7850
7851 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7852 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7853 "sete $res\n\t"
7854 "movzbl $res, $res" %}
7855 opcode(0x0F, 0xB1);
7856 ins_encode(lock_prefix,
7857 REX_reg_mem(newval, mem_ptr),
7858 OpcP, OpcS,
7859 reg_mem(newval, mem_ptr),
7860 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7861 REX_reg_breg(res, res), // movzbl
7862 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7863 ins_pipe( pipe_cmpxchg );
7864 %}
7865
7866 instruct compareAndSwapB(rRegI res,
7867 memory mem_ptr,
7868 rax_RegI oldval, rRegI newval,
7869 rFlagsReg cr)
7870 %{
7871 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7872 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7873 effect(KILL cr, KILL oldval);
7874
7875 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7876 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7877 "sete $res\n\t"
7878 "movzbl $res, $res" %}
7879 opcode(0x0F, 0xB0);
7880 ins_encode(lock_prefix,
7881 REX_breg_mem(newval, mem_ptr),
7882 OpcP, OpcS,
7883 reg_mem(newval, mem_ptr),
7884 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7885 REX_reg_breg(res, res), // movzbl
7886 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7887 ins_pipe( pipe_cmpxchg );
7888 %}
7889
7890 instruct compareAndSwapS(rRegI res,
7891 memory mem_ptr,
7892 rax_RegI oldval, rRegI newval,
7893 rFlagsReg cr)
7894 %{
7895 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7896 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7897 effect(KILL cr, KILL oldval);
7898
7899 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7900 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7901 "sete $res\n\t"
7902 "movzbl $res, $res" %}
7903 opcode(0x0F, 0xB1);
7904 ins_encode(lock_prefix,
7905 SizePrefix,
7906 REX_reg_mem(newval, mem_ptr),
7907 OpcP, OpcS,
7908 reg_mem(newval, mem_ptr),
7909 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7910 REX_reg_breg(res, res), // movzbl
7911 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7912 ins_pipe( pipe_cmpxchg );
7913 %}
7914
7915 instruct compareAndSwapN(rRegI res,
7916 memory mem_ptr,
7917 rax_RegN oldval, rRegN newval,
7918 rFlagsReg cr) %{
7919 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7920 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7921 effect(KILL cr, KILL oldval);
7922
7923 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7924 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7925 "sete $res\n\t"
7926 "movzbl $res, $res" %}
7927 opcode(0x0F, 0xB1);
7928 ins_encode(lock_prefix,
7929 REX_reg_mem(newval, mem_ptr),
7930 OpcP, OpcS,
7931 reg_mem(newval, mem_ptr),
7932 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7933 REX_reg_breg(res, res), // movzbl
7934 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7935 ins_pipe( pipe_cmpxchg );
7936 %}
7937
7938 instruct compareAndExchangeB(
7939 memory mem_ptr,
7940 rax_RegI oldval, rRegI newval,
7941 rFlagsReg cr)
7942 %{
7943 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7944 effect(KILL cr);
7945
7946 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7947 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7948 opcode(0x0F, 0xB0);
7949 ins_encode(lock_prefix,
7950 REX_breg_mem(newval, mem_ptr),
7951 OpcP, OpcS,
7952 reg_mem(newval, mem_ptr) // lock cmpxchg
7953 );
7954 ins_pipe( pipe_cmpxchg );
7955 %}
7956
7957 instruct compareAndExchangeS(
7958 memory mem_ptr,
7959 rax_RegI oldval, rRegI newval,
7960 rFlagsReg cr)
7961 %{
7962 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7963 effect(KILL cr);
7964
7965 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7966 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7967 opcode(0x0F, 0xB1);
7968 ins_encode(lock_prefix,
7969 SizePrefix,
7970 REX_reg_mem(newval, mem_ptr),
7971 OpcP, OpcS,
7972 reg_mem(newval, mem_ptr) // lock cmpxchg
7973 );
7974 ins_pipe( pipe_cmpxchg );
7975 %}
7976
7977 instruct compareAndExchangeI(
7978 memory mem_ptr,
7979 rax_RegI oldval, rRegI newval,
7980 rFlagsReg cr)
7981 %{
7982 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7983 effect(KILL cr);
7984
7985 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7986 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7987 opcode(0x0F, 0xB1);
7988 ins_encode(lock_prefix,
7989 REX_reg_mem(newval, mem_ptr),
7990 OpcP, OpcS,
7991 reg_mem(newval, mem_ptr) // lock cmpxchg
7992 );
7993 ins_pipe( pipe_cmpxchg );
7994 %}
7995
7996 instruct compareAndExchangeL(
7997 memory mem_ptr,
7998 rax_RegL oldval, rRegL newval,
7999 rFlagsReg cr)
8000 %{
8001 predicate(VM_Version::supports_cx8());
8002 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
8003 effect(KILL cr);
8004
8005 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8006 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
8007 opcode(0x0F, 0xB1);
8008 ins_encode(lock_prefix,
8009 REX_reg_mem_wide(newval, mem_ptr),
8010 OpcP, OpcS,
8011 reg_mem(newval, mem_ptr) // lock cmpxchg
8012 );
8013 ins_pipe( pipe_cmpxchg );
8014 %}
8015
8016 instruct compareAndExchangeN(
8017 memory mem_ptr,
8018 rax_RegN oldval, rRegN newval,
8019 rFlagsReg cr) %{
8020 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
8021 effect(KILL cr);
8022
8023 format %{ "cmpxchgl $mem_ptr,$newval\t# "
8024 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
8025 opcode(0x0F, 0xB1);
8026 ins_encode(lock_prefix,
8027 REX_reg_mem(newval, mem_ptr),
8028 OpcP, OpcS,
8029 reg_mem(newval, mem_ptr) // lock cmpxchg
8030 );
8031 ins_pipe( pipe_cmpxchg );
8032 %}
8033
8034 instruct compareAndExchangeP(
8035 memory mem_ptr,
8036 rax_RegP oldval, rRegP newval,
8037 rFlagsReg cr)
8038 %{
8039 predicate(VM_Version::supports_cx8());
8040 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
8041 effect(KILL cr);
8042
8043 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8044 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
8045 opcode(0x0F, 0xB1);
8046 ins_encode(lock_prefix,
8047 REX_reg_mem_wide(newval, mem_ptr),
8048 OpcP, OpcS,
8049 reg_mem(newval, mem_ptr) // lock cmpxchg
8050 );
8051 ins_pipe( pipe_cmpxchg );
8052 %}
8053
8054 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8055 predicate(n->as_LoadStore()->result_not_used());
8056 match(Set dummy (GetAndAddB mem add));
8057 effect(KILL cr);
8058 format %{ "ADDB [$mem],$add" %}
8059 ins_encode %{
8060 __ lock();
8061 __ addb($mem$$Address, $add$$constant);
8062 %}
8063 ins_pipe( pipe_cmpxchg );
8064 %}
8065
8066 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
8067 match(Set newval (GetAndAddB mem newval));
8068 effect(KILL cr);
8069 format %{ "XADDB [$mem],$newval" %}
8070 ins_encode %{
8071 __ lock();
8072 __ xaddb($mem$$Address, $newval$$Register);
8073 %}
8074 ins_pipe( pipe_cmpxchg );
8075 %}
8076
8077 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8078 predicate(n->as_LoadStore()->result_not_used());
8079 match(Set dummy (GetAndAddS mem add));
8080 effect(KILL cr);
8081 format %{ "ADDW [$mem],$add" %}
8082 ins_encode %{
8083 __ lock();
8084 __ addw($mem$$Address, $add$$constant);
8085 %}
8086 ins_pipe( pipe_cmpxchg );
8087 %}
8088
8089 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
8090 match(Set newval (GetAndAddS mem newval));
8091 effect(KILL cr);
8092 format %{ "XADDW [$mem],$newval" %}
8093 ins_encode %{
8094 __ lock();
8095 __ xaddw($mem$$Address, $newval$$Register);
8096 %}
8097 ins_pipe( pipe_cmpxchg );
8098 %}
8099
8100 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8101 predicate(n->as_LoadStore()->result_not_used());
8102 match(Set dummy (GetAndAddI mem add));
8103 effect(KILL cr);
8104 format %{ "ADDL [$mem],$add" %}
8105 ins_encode %{
8106 __ lock();
8107 __ addl($mem$$Address, $add$$constant);
8108 %}
8109 ins_pipe( pipe_cmpxchg );
8110 %}
8111
8112 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
8113 match(Set newval (GetAndAddI mem newval));
8114 effect(KILL cr);
8115 format %{ "XADDL [$mem],$newval" %}
8116 ins_encode %{
8117 __ lock();
8118 __ xaddl($mem$$Address, $newval$$Register);
8119 %}
8120 ins_pipe( pipe_cmpxchg );
8121 %}
8122
8123 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8124 predicate(n->as_LoadStore()->result_not_used());
8125 match(Set dummy (GetAndAddL mem add));
8126 effect(KILL cr);
8127 format %{ "ADDQ [$mem],$add" %}
8128 ins_encode %{
8129 __ lock();
8130 __ addq($mem$$Address, $add$$constant);
8131 %}
8132 ins_pipe( pipe_cmpxchg );
8133 %}
8134
8135 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
8136 match(Set newval (GetAndAddL mem newval));
8137 effect(KILL cr);
8138 format %{ "XADDQ [$mem],$newval" %}
8139 ins_encode %{
8140 __ lock();
8141 __ xaddq($mem$$Address, $newval$$Register);
8142 %}
8143 ins_pipe( pipe_cmpxchg );
8144 %}
8145
8146 instruct xchgB( memory mem, rRegI newval) %{
8147 match(Set newval (GetAndSetB mem newval));
8148 format %{ "XCHGB $newval,[$mem]" %}
8149 ins_encode %{
8150 __ xchgb($newval$$Register, $mem$$Address);
8151 %}
8152 ins_pipe( pipe_cmpxchg );
8153 %}
8154
8155 instruct xchgS( memory mem, rRegI newval) %{
8156 match(Set newval (GetAndSetS mem newval));
8157 format %{ "XCHGW $newval,[$mem]" %}
8158 ins_encode %{
8159 __ xchgw($newval$$Register, $mem$$Address);
8160 %}
8161 ins_pipe( pipe_cmpxchg );
8162 %}
8163
8164 instruct xchgI( memory mem, rRegI newval) %{
8165 match(Set newval (GetAndSetI mem newval));
8166 format %{ "XCHGL $newval,[$mem]" %}
8167 ins_encode %{
8168 __ xchgl($newval$$Register, $mem$$Address);
8169 %}
8170 ins_pipe( pipe_cmpxchg );
8171 %}
8172
8173 instruct xchgL( memory mem, rRegL newval) %{
8174 match(Set newval (GetAndSetL mem newval));
8175 format %{ "XCHGL $newval,[$mem]" %}
8176 ins_encode %{
8177 __ xchgq($newval$$Register, $mem$$Address);
8178 %}
8179 ins_pipe( pipe_cmpxchg );
8180 %}
8181
8182 instruct xchgP( memory mem, rRegP newval) %{
8183 match(Set newval (GetAndSetP mem newval));
8184 format %{ "XCHGQ $newval,[$mem]" %}
8185 ins_encode %{
8186 __ xchgq($newval$$Register, $mem$$Address);
8187 %}
8188 ins_pipe( pipe_cmpxchg );
8189 %}
8190
8191 instruct xchgN( memory mem, rRegN newval) %{
8192 match(Set newval (GetAndSetN mem newval));
8193 format %{ "XCHGL $newval,$mem]" %}
8194 ins_encode %{
8195 __ xchgl($newval$$Register, $mem$$Address);
8196 %}
8197 ins_pipe( pipe_cmpxchg );
8198 %}
8199
8200 //----------Abs Instructions-------------------------------------------
8201
8202 // Integer Absolute Instructions
8203 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
8204 %{
8205 match(Set dst (AbsI src));
8206 effect(TEMP dst, TEMP tmp, KILL cr);
8207 format %{ "movl $tmp, $src\n\t"
8208 "sarl $tmp, 31\n\t"
8209 "movl $dst, $src\n\t"
8210 "xorl $dst, $tmp\n\t"
8211 "subl $dst, $tmp\n"
8212 %}
8213 ins_encode %{
8214 __ movl($tmp$$Register, $src$$Register);
8215 __ sarl($tmp$$Register, 31);
8216 __ movl($dst$$Register, $src$$Register);
8217 __ xorl($dst$$Register, $tmp$$Register);
8218 __ subl($dst$$Register, $tmp$$Register);
8219 %}
8220
8221 ins_pipe(ialu_reg_reg);
8222 %}
8223
8224 // Long Absolute Instructions
8225 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
8226 %{
8227 match(Set dst (AbsL src));
8228 effect(TEMP dst, TEMP tmp, KILL cr);
8229 format %{ "movq $tmp, $src\n\t"
8230 "sarq $tmp, 63\n\t"
8231 "movq $dst, $src\n\t"
8232 "xorq $dst, $tmp\n\t"
8233 "subq $dst, $tmp\n"
8234 %}
8235 ins_encode %{
8236 __ movq($tmp$$Register, $src$$Register);
8237 __ sarq($tmp$$Register, 63);
8238 __ movq($dst$$Register, $src$$Register);
8239 __ xorq($dst$$Register, $tmp$$Register);
8240 __ subq($dst$$Register, $tmp$$Register);
8241 %}
8242
8243 ins_pipe(ialu_reg_reg);
8244 %}
8245
8246 //----------Subtraction Instructions-------------------------------------------
8247
8248 // Integer Subtraction Instructions
8249 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8250 %{
8251 match(Set dst (SubI dst src));
8252 effect(KILL cr);
8253
8254 format %{ "subl $dst, $src\t# int" %}
8255 opcode(0x2B);
8256 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8257 ins_pipe(ialu_reg_reg);
8258 %}
8259
8260 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8261 %{
8262 match(Set dst (SubI dst src));
8263 effect(KILL cr);
8264
8265 format %{ "subl $dst, $src\t# int" %}
8266 opcode(0x81, 0x05); /* Opcode 81 /5 */
8267 ins_encode(OpcSErm(dst, src), Con8or32(src));
8268 ins_pipe(ialu_reg);
8269 %}
8270
8271 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8272 %{
8273 match(Set dst (SubI dst (LoadI src)));
8274 effect(KILL cr);
8275
8276 ins_cost(125);
8277 format %{ "subl $dst, $src\t# int" %}
8278 opcode(0x2B);
8279 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8280 ins_pipe(ialu_reg_mem);
8281 %}
8282
8283 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8284 %{
8285 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8286 effect(KILL cr);
8287
8288 ins_cost(150);
8289 format %{ "subl $dst, $src\t# int" %}
8290 opcode(0x29); /* Opcode 29 /r */
8291 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8292 ins_pipe(ialu_mem_reg);
8293 %}
8294
8295 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8296 %{
8297 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8298 effect(KILL cr);
8299
8300 ins_cost(125); // XXX
8301 format %{ "subl $dst, $src\t# int" %}
8302 opcode(0x81); /* Opcode 81 /5 id */
8303 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8304 ins_pipe(ialu_mem_imm);
8305 %}
8306
8307 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8308 %{
8309 match(Set dst (SubL dst src));
8310 effect(KILL cr);
8311
8312 format %{ "subq $dst, $src\t# long" %}
8313 opcode(0x2B);
8314 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8315 ins_pipe(ialu_reg_reg);
8316 %}
8317
8318 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8319 %{
8320 match(Set dst (SubL dst src));
8321 effect(KILL cr);
8322
8323 format %{ "subq $dst, $src\t# long" %}
8324 opcode(0x81, 0x05); /* Opcode 81 /5 */
8325 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8326 ins_pipe(ialu_reg);
8327 %}
8328
8329 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8330 %{
8331 match(Set dst (SubL dst (LoadL src)));
8332 effect(KILL cr);
8333
8334 ins_cost(125);
8335 format %{ "subq $dst, $src\t# long" %}
8336 opcode(0x2B);
8337 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8338 ins_pipe(ialu_reg_mem);
8339 %}
8340
8341 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8342 %{
8343 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8344 effect(KILL cr);
8345
8346 ins_cost(150);
8347 format %{ "subq $dst, $src\t# long" %}
8348 opcode(0x29); /* Opcode 29 /r */
8349 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8350 ins_pipe(ialu_mem_reg);
8351 %}
8352
8353 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8354 %{
8355 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8356 effect(KILL cr);
8357
8358 ins_cost(125); // XXX
8359 format %{ "subq $dst, $src\t# long" %}
8360 opcode(0x81); /* Opcode 81 /5 id */
8361 ins_encode(REX_mem_wide(dst),
8362 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8363 ins_pipe(ialu_mem_imm);
8364 %}
8365
8366 // Subtract from a pointer
8367 // XXX hmpf???
8368 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8369 %{
8370 match(Set dst (AddP dst (SubI zero src)));
8371 effect(KILL cr);
8372
8373 format %{ "subq $dst, $src\t# ptr - int" %}
8374 opcode(0x2B);
8375 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8376 ins_pipe(ialu_reg_reg);
8377 %}
8378
8379 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8380 %{
8381 match(Set dst (SubI zero dst));
8382 effect(KILL cr);
8383
8384 format %{ "negl $dst\t# int" %}
8385 opcode(0xF7, 0x03); // Opcode F7 /3
8386 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8387 ins_pipe(ialu_reg);
8388 %}
8389
8390 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8391 %{
8392 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8393 effect(KILL cr);
8394
8395 format %{ "negl $dst\t# int" %}
8396 opcode(0xF7, 0x03); // Opcode F7 /3
8397 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8398 ins_pipe(ialu_reg);
8399 %}
8400
8401 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8402 %{
8403 match(Set dst (SubL zero dst));
8404 effect(KILL cr);
8405
8406 format %{ "negq $dst\t# long" %}
8407 opcode(0xF7, 0x03); // Opcode F7 /3
8408 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8409 ins_pipe(ialu_reg);
8410 %}
8411
8412 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8413 %{
8414 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8415 effect(KILL cr);
8416
8417 format %{ "negq $dst\t# long" %}
8418 opcode(0xF7, 0x03); // Opcode F7 /3
8419 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8420 ins_pipe(ialu_reg);
8421 %}
8422
8423 //----------Multiplication/Division Instructions-------------------------------
8424 // Integer Multiplication Instructions
8425 // Multiply Register
8426
8427 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8428 %{
8429 match(Set dst (MulI dst src));
8430 effect(KILL cr);
8431
8432 ins_cost(300);
8433 format %{ "imull $dst, $src\t# int" %}
8434 opcode(0x0F, 0xAF);
8435 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8436 ins_pipe(ialu_reg_reg_alu0);
8437 %}
8438
8439 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8440 %{
8441 match(Set dst (MulI src imm));
8442 effect(KILL cr);
8443
8444 ins_cost(300);
8445 format %{ "imull $dst, $src, $imm\t# int" %}
8446 opcode(0x69); /* 69 /r id */
8447 ins_encode(REX_reg_reg(dst, src),
8448 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8449 ins_pipe(ialu_reg_reg_alu0);
8450 %}
8451
8452 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8453 %{
8454 match(Set dst (MulI dst (LoadI src)));
8455 effect(KILL cr);
8456
8457 ins_cost(350);
8458 format %{ "imull $dst, $src\t# int" %}
8459 opcode(0x0F, 0xAF);
8460 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8461 ins_pipe(ialu_reg_mem_alu0);
8462 %}
8463
8464 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8465 %{
8466 match(Set dst (MulI (LoadI src) imm));
8467 effect(KILL cr);
8468
8469 ins_cost(300);
8470 format %{ "imull $dst, $src, $imm\t# int" %}
8471 opcode(0x69); /* 69 /r id */
8472 ins_encode(REX_reg_mem(dst, src),
8473 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8474 ins_pipe(ialu_reg_mem_alu0);
8475 %}
8476
8477 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8478 %{
8479 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8480 effect(KILL cr, KILL src2);
8481
8482 expand %{ mulI_rReg(dst, src1, cr);
8483 mulI_rReg(src2, src3, cr);
8484 addI_rReg(dst, src2, cr); %}
8485 %}
8486
8487 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8488 %{
8489 match(Set dst (MulL dst src));
8490 effect(KILL cr);
8491
8492 ins_cost(300);
8493 format %{ "imulq $dst, $src\t# long" %}
8494 opcode(0x0F, 0xAF);
8495 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8496 ins_pipe(ialu_reg_reg_alu0);
8497 %}
8498
8499 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8500 %{
8501 match(Set dst (MulL src imm));
8502 effect(KILL cr);
8503
8504 ins_cost(300);
8505 format %{ "imulq $dst, $src, $imm\t# long" %}
8506 opcode(0x69); /* 69 /r id */
8507 ins_encode(REX_reg_reg_wide(dst, src),
8508 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8509 ins_pipe(ialu_reg_reg_alu0);
8510 %}
8511
8512 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8513 %{
8514 match(Set dst (MulL dst (LoadL src)));
8515 effect(KILL cr);
8516
8517 ins_cost(350);
8518 format %{ "imulq $dst, $src\t# long" %}
8519 opcode(0x0F, 0xAF);
8520 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8521 ins_pipe(ialu_reg_mem_alu0);
8522 %}
8523
8524 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8525 %{
8526 match(Set dst (MulL (LoadL src) imm));
8527 effect(KILL cr);
8528
8529 ins_cost(300);
8530 format %{ "imulq $dst, $src, $imm\t# long" %}
8531 opcode(0x69); /* 69 /r id */
8532 ins_encode(REX_reg_mem_wide(dst, src),
8533 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8534 ins_pipe(ialu_reg_mem_alu0);
8535 %}
8536
8537 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8538 %{
8539 match(Set dst (MulHiL src rax));
8540 effect(USE_KILL rax, KILL cr);
8541
8542 ins_cost(300);
8543 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8544 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8545 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8546 ins_pipe(ialu_reg_reg_alu0);
8547 %}
8548
8549 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8550 rFlagsReg cr)
8551 %{
8552 match(Set rax (DivI rax div));
8553 effect(KILL rdx, KILL cr);
8554
8555 ins_cost(30*100+10*100); // XXX
8556 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8557 "jne,s normal\n\t"
8558 "xorl rdx, rdx\n\t"
8559 "cmpl $div, -1\n\t"
8560 "je,s done\n"
8561 "normal: cdql\n\t"
8562 "idivl $div\n"
8563 "done:" %}
8564 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8565 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8566 ins_pipe(ialu_reg_reg_alu0);
8567 %}
8568
8569 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8570 rFlagsReg cr)
8571 %{
8572 match(Set rax (DivL rax div));
8573 effect(KILL rdx, KILL cr);
8574
8575 ins_cost(30*100+10*100); // XXX
8576 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8577 "cmpq rax, rdx\n\t"
8578 "jne,s normal\n\t"
8579 "xorl rdx, rdx\n\t"
8580 "cmpq $div, -1\n\t"
8581 "je,s done\n"
8582 "normal: cdqq\n\t"
8583 "idivq $div\n"
8584 "done:" %}
8585 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8586 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8587 ins_pipe(ialu_reg_reg_alu0);
8588 %}
8589
8590 // Integer DIVMOD with Register, both quotient and mod results
8591 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8592 rFlagsReg cr)
8593 %{
8594 match(DivModI rax div);
8595 effect(KILL cr);
8596
8597 ins_cost(30*100+10*100); // XXX
8598 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8599 "jne,s normal\n\t"
8600 "xorl rdx, rdx\n\t"
8601 "cmpl $div, -1\n\t"
8602 "je,s done\n"
8603 "normal: cdql\n\t"
8604 "idivl $div\n"
8605 "done:" %}
8606 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8607 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8608 ins_pipe(pipe_slow);
8609 %}
8610
8611 // Long DIVMOD with Register, both quotient and mod results
8612 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8613 rFlagsReg cr)
8614 %{
8615 match(DivModL rax div);
8616 effect(KILL cr);
8617
8618 ins_cost(30*100+10*100); // XXX
8619 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8620 "cmpq rax, rdx\n\t"
8621 "jne,s normal\n\t"
8622 "xorl rdx, rdx\n\t"
8623 "cmpq $div, -1\n\t"
8624 "je,s done\n"
8625 "normal: cdqq\n\t"
8626 "idivq $div\n"
8627 "done:" %}
8628 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8629 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8630 ins_pipe(pipe_slow);
8631 %}
8632
8633 //----------- DivL-By-Constant-Expansions--------------------------------------
8634 // DivI cases are handled by the compiler
8635
8636 // Magic constant, reciprocal of 10
8637 instruct loadConL_0x6666666666666667(rRegL dst)
8638 %{
8639 effect(DEF dst);
8640
8641 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8642 ins_encode(load_immL(dst, 0x6666666666666667));
8643 ins_pipe(ialu_reg);
8644 %}
8645
8646 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8647 %{
8648 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8649
8650 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8651 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8652 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8653 ins_pipe(ialu_reg_reg_alu0);
8654 %}
8655
8656 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8657 %{
8658 effect(USE_DEF dst, KILL cr);
8659
8660 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8661 opcode(0xC1, 0x7); /* C1 /7 ib */
8662 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8663 ins_pipe(ialu_reg);
8664 %}
8665
8666 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8667 %{
8668 effect(USE_DEF dst, KILL cr);
8669
8670 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8671 opcode(0xC1, 0x7); /* C1 /7 ib */
8672 ins_encode(reg_opc_imm_wide(dst, 0x2));
8673 ins_pipe(ialu_reg);
8674 %}
8675
8676 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8677 %{
8678 match(Set dst (DivL src div));
8679
8680 ins_cost((5+8)*100);
8681 expand %{
8682 rax_RegL rax; // Killed temp
8683 rFlagsReg cr; // Killed
8684 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8685 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8686 sarL_rReg_63(src, cr); // sarq src, 63
8687 sarL_rReg_2(dst, cr); // sarq rdx, 2
8688 subL_rReg(dst, src, cr); // subl rdx, src
8689 %}
8690 %}
8691
8692 //-----------------------------------------------------------------------------
8693
8694 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8695 rFlagsReg cr)
8696 %{
8697 match(Set rdx (ModI rax div));
8698 effect(KILL rax, KILL cr);
8699
8700 ins_cost(300); // XXX
8701 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8702 "jne,s normal\n\t"
8703 "xorl rdx, rdx\n\t"
8704 "cmpl $div, -1\n\t"
8705 "je,s done\n"
8706 "normal: cdql\n\t"
8707 "idivl $div\n"
8708 "done:" %}
8709 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8710 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8711 ins_pipe(ialu_reg_reg_alu0);
8712 %}
8713
8714 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8715 rFlagsReg cr)
8716 %{
8717 match(Set rdx (ModL rax div));
8718 effect(KILL rax, KILL cr);
8719
8720 ins_cost(300); // XXX
8721 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8722 "cmpq rax, rdx\n\t"
8723 "jne,s normal\n\t"
8724 "xorl rdx, rdx\n\t"
8725 "cmpq $div, -1\n\t"
8726 "je,s done\n"
8727 "normal: cdqq\n\t"
8728 "idivq $div\n"
8729 "done:" %}
8730 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8731 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8732 ins_pipe(ialu_reg_reg_alu0);
8733 %}
8734
8735 // Integer Shift Instructions
8736 // Shift Left by one
8737 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8738 %{
8739 match(Set dst (LShiftI dst shift));
8740 effect(KILL cr);
8741
8742 format %{ "sall $dst, $shift" %}
8743 opcode(0xD1, 0x4); /* D1 /4 */
8744 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8745 ins_pipe(ialu_reg);
8746 %}
8747
8748 // Shift Left by one
8749 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8750 %{
8751 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8752 effect(KILL cr);
8753
8754 format %{ "sall $dst, $shift\t" %}
8755 opcode(0xD1, 0x4); /* D1 /4 */
8756 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8757 ins_pipe(ialu_mem_imm);
8758 %}
8759
8760 // Shift Left by 8-bit immediate
8761 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8762 %{
8763 match(Set dst (LShiftI dst shift));
8764 effect(KILL cr);
8765
8766 format %{ "sall $dst, $shift" %}
8767 opcode(0xC1, 0x4); /* C1 /4 ib */
8768 ins_encode(reg_opc_imm(dst, shift));
8769 ins_pipe(ialu_reg);
8770 %}
8771
8772 // Shift Left by 8-bit immediate
8773 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8774 %{
8775 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8776 effect(KILL cr);
8777
8778 format %{ "sall $dst, $shift" %}
8779 opcode(0xC1, 0x4); /* C1 /4 ib */
8780 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8781 ins_pipe(ialu_mem_imm);
8782 %}
8783
8784 // Shift Left by variable
8785 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8786 %{
8787 match(Set dst (LShiftI dst shift));
8788 effect(KILL cr);
8789
8790 format %{ "sall $dst, $shift" %}
8791 opcode(0xD3, 0x4); /* D3 /4 */
8792 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8793 ins_pipe(ialu_reg_reg);
8794 %}
8795
8796 // Shift Left by variable
8797 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8798 %{
8799 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8800 effect(KILL cr);
8801
8802 format %{ "sall $dst, $shift" %}
8803 opcode(0xD3, 0x4); /* D3 /4 */
8804 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8805 ins_pipe(ialu_mem_reg);
8806 %}
8807
8808 // Arithmetic shift right by one
8809 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8810 %{
8811 match(Set dst (RShiftI dst shift));
8812 effect(KILL cr);
8813
8814 format %{ "sarl $dst, $shift" %}
8815 opcode(0xD1, 0x7); /* D1 /7 */
8816 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8817 ins_pipe(ialu_reg);
8818 %}
8819
8820 // Arithmetic shift right by one
8821 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8822 %{
8823 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8824 effect(KILL cr);
8825
8826 format %{ "sarl $dst, $shift" %}
8827 opcode(0xD1, 0x7); /* D1 /7 */
8828 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8829 ins_pipe(ialu_mem_imm);
8830 %}
8831
8832 // Arithmetic Shift Right by 8-bit immediate
8833 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8834 %{
8835 match(Set dst (RShiftI dst shift));
8836 effect(KILL cr);
8837
8838 format %{ "sarl $dst, $shift" %}
8839 opcode(0xC1, 0x7); /* C1 /7 ib */
8840 ins_encode(reg_opc_imm(dst, shift));
8841 ins_pipe(ialu_mem_imm);
8842 %}
8843
8844 // Arithmetic Shift Right by 8-bit immediate
8845 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8846 %{
8847 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8848 effect(KILL cr);
8849
8850 format %{ "sarl $dst, $shift" %}
8851 opcode(0xC1, 0x7); /* C1 /7 ib */
8852 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8853 ins_pipe(ialu_mem_imm);
8854 %}
8855
8856 // Arithmetic Shift Right by variable
8857 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8858 %{
8859 match(Set dst (RShiftI dst shift));
8860 effect(KILL cr);
8861
8862 format %{ "sarl $dst, $shift" %}
8863 opcode(0xD3, 0x7); /* D3 /7 */
8864 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8865 ins_pipe(ialu_reg_reg);
8866 %}
8867
8868 // Arithmetic Shift Right by variable
8869 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8870 %{
8871 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8872 effect(KILL cr);
8873
8874 format %{ "sarl $dst, $shift" %}
8875 opcode(0xD3, 0x7); /* D3 /7 */
8876 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8877 ins_pipe(ialu_mem_reg);
8878 %}
8879
8880 // Logical shift right by one
8881 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8882 %{
8883 match(Set dst (URShiftI dst shift));
8884 effect(KILL cr);
8885
8886 format %{ "shrl $dst, $shift" %}
8887 opcode(0xD1, 0x5); /* D1 /5 */
8888 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8889 ins_pipe(ialu_reg);
8890 %}
8891
8892 // Logical shift right by one
8893 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8894 %{
8895 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8896 effect(KILL cr);
8897
8898 format %{ "shrl $dst, $shift" %}
8899 opcode(0xD1, 0x5); /* D1 /5 */
8900 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8901 ins_pipe(ialu_mem_imm);
8902 %}
8903
8904 // Logical Shift Right by 8-bit immediate
8905 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8906 %{
8907 match(Set dst (URShiftI dst shift));
8908 effect(KILL cr);
8909
8910 format %{ "shrl $dst, $shift" %}
8911 opcode(0xC1, 0x5); /* C1 /5 ib */
8912 ins_encode(reg_opc_imm(dst, shift));
8913 ins_pipe(ialu_reg);
8914 %}
8915
8916 // Logical Shift Right by 8-bit immediate
8917 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8918 %{
8919 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8920 effect(KILL cr);
8921
8922 format %{ "shrl $dst, $shift" %}
8923 opcode(0xC1, 0x5); /* C1 /5 ib */
8924 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8925 ins_pipe(ialu_mem_imm);
8926 %}
8927
8928 // Logical Shift Right by variable
8929 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8930 %{
8931 match(Set dst (URShiftI dst shift));
8932 effect(KILL cr);
8933
8934 format %{ "shrl $dst, $shift" %}
8935 opcode(0xD3, 0x5); /* D3 /5 */
8936 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8937 ins_pipe(ialu_reg_reg);
8938 %}
8939
8940 // Logical Shift Right by variable
8941 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8942 %{
8943 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8944 effect(KILL cr);
8945
8946 format %{ "shrl $dst, $shift" %}
8947 opcode(0xD3, 0x5); /* D3 /5 */
8948 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8949 ins_pipe(ialu_mem_reg);
8950 %}
8951
8952 // Long Shift Instructions
8953 // Shift Left by one
8954 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8955 %{
8956 match(Set dst (LShiftL dst shift));
8957 effect(KILL cr);
8958
8959 format %{ "salq $dst, $shift" %}
8960 opcode(0xD1, 0x4); /* D1 /4 */
8961 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8962 ins_pipe(ialu_reg);
8963 %}
8964
8965 // Shift Left by one
8966 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8967 %{
8968 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8969 effect(KILL cr);
8970
8971 format %{ "salq $dst, $shift" %}
8972 opcode(0xD1, 0x4); /* D1 /4 */
8973 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8974 ins_pipe(ialu_mem_imm);
8975 %}
8976
8977 // Shift Left by 8-bit immediate
8978 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8979 %{
8980 match(Set dst (LShiftL dst shift));
8981 effect(KILL cr);
8982
8983 format %{ "salq $dst, $shift" %}
8984 opcode(0xC1, 0x4); /* C1 /4 ib */
8985 ins_encode(reg_opc_imm_wide(dst, shift));
8986 ins_pipe(ialu_reg);
8987 %}
8988
8989 // Shift Left by 8-bit immediate
8990 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8991 %{
8992 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8993 effect(KILL cr);
8994
8995 format %{ "salq $dst, $shift" %}
8996 opcode(0xC1, 0x4); /* C1 /4 ib */
8997 ins_encode(REX_mem_wide(dst), OpcP,
8998 RM_opc_mem(secondary, dst), Con8or32(shift));
8999 ins_pipe(ialu_mem_imm);
9000 %}
9001
9002 // Shift Left by variable
9003 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9004 %{
9005 match(Set dst (LShiftL dst shift));
9006 effect(KILL cr);
9007
9008 format %{ "salq $dst, $shift" %}
9009 opcode(0xD3, 0x4); /* D3 /4 */
9010 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9011 ins_pipe(ialu_reg_reg);
9012 %}
9013
9014 // Shift Left by variable
9015 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9016 %{
9017 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9018 effect(KILL cr);
9019
9020 format %{ "salq $dst, $shift" %}
9021 opcode(0xD3, 0x4); /* D3 /4 */
9022 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9023 ins_pipe(ialu_mem_reg);
9024 %}
9025
9026 // Arithmetic shift right by one
9027 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9028 %{
9029 match(Set dst (RShiftL dst shift));
9030 effect(KILL cr);
9031
9032 format %{ "sarq $dst, $shift" %}
9033 opcode(0xD1, 0x7); /* D1 /7 */
9034 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9035 ins_pipe(ialu_reg);
9036 %}
9037
9038 // Arithmetic shift right by one
9039 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9040 %{
9041 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9042 effect(KILL cr);
9043
9044 format %{ "sarq $dst, $shift" %}
9045 opcode(0xD1, 0x7); /* D1 /7 */
9046 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9047 ins_pipe(ialu_mem_imm);
9048 %}
9049
9050 // Arithmetic Shift Right by 8-bit immediate
9051 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9052 %{
9053 match(Set dst (RShiftL dst shift));
9054 effect(KILL cr);
9055
9056 format %{ "sarq $dst, $shift" %}
9057 opcode(0xC1, 0x7); /* C1 /7 ib */
9058 ins_encode(reg_opc_imm_wide(dst, shift));
9059 ins_pipe(ialu_mem_imm);
9060 %}
9061
9062 // Arithmetic Shift Right by 8-bit immediate
9063 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9064 %{
9065 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9066 effect(KILL cr);
9067
9068 format %{ "sarq $dst, $shift" %}
9069 opcode(0xC1, 0x7); /* C1 /7 ib */
9070 ins_encode(REX_mem_wide(dst), OpcP,
9071 RM_opc_mem(secondary, dst), Con8or32(shift));
9072 ins_pipe(ialu_mem_imm);
9073 %}
9074
9075 // Arithmetic Shift Right by variable
9076 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9077 %{
9078 match(Set dst (RShiftL dst shift));
9079 effect(KILL cr);
9080
9081 format %{ "sarq $dst, $shift" %}
9082 opcode(0xD3, 0x7); /* D3 /7 */
9083 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9084 ins_pipe(ialu_reg_reg);
9085 %}
9086
9087 // Arithmetic Shift Right by variable
9088 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9089 %{
9090 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9091 effect(KILL cr);
9092
9093 format %{ "sarq $dst, $shift" %}
9094 opcode(0xD3, 0x7); /* D3 /7 */
9095 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9096 ins_pipe(ialu_mem_reg);
9097 %}
9098
9099 // Logical shift right by one
9100 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9101 %{
9102 match(Set dst (URShiftL dst shift));
9103 effect(KILL cr);
9104
9105 format %{ "shrq $dst, $shift" %}
9106 opcode(0xD1, 0x5); /* D1 /5 */
9107 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
9108 ins_pipe(ialu_reg);
9109 %}
9110
9111 // Logical shift right by one
9112 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9113 %{
9114 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9115 effect(KILL cr);
9116
9117 format %{ "shrq $dst, $shift" %}
9118 opcode(0xD1, 0x5); /* D1 /5 */
9119 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9120 ins_pipe(ialu_mem_imm);
9121 %}
9122
9123 // Logical Shift Right by 8-bit immediate
9124 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9125 %{
9126 match(Set dst (URShiftL dst shift));
9127 effect(KILL cr);
9128
9129 format %{ "shrq $dst, $shift" %}
9130 opcode(0xC1, 0x5); /* C1 /5 ib */
9131 ins_encode(reg_opc_imm_wide(dst, shift));
9132 ins_pipe(ialu_reg);
9133 %}
9134
9135
9136 // Logical Shift Right by 8-bit immediate
9137 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9138 %{
9139 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9140 effect(KILL cr);
9141
9142 format %{ "shrq $dst, $shift" %}
9143 opcode(0xC1, 0x5); /* C1 /5 ib */
9144 ins_encode(REX_mem_wide(dst), OpcP,
9145 RM_opc_mem(secondary, dst), Con8or32(shift));
9146 ins_pipe(ialu_mem_imm);
9147 %}
9148
9149 // Logical Shift Right by variable
9150 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9151 %{
9152 match(Set dst (URShiftL dst shift));
9153 effect(KILL cr);
9154
9155 format %{ "shrq $dst, $shift" %}
9156 opcode(0xD3, 0x5); /* D3 /5 */
9157 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9158 ins_pipe(ialu_reg_reg);
9159 %}
9160
9161 // Logical Shift Right by variable
9162 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9163 %{
9164 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9165 effect(KILL cr);
9166
9167 format %{ "shrq $dst, $shift" %}
9168 opcode(0xD3, 0x5); /* D3 /5 */
9169 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9170 ins_pipe(ialu_mem_reg);
9171 %}
9172
9173 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9174 // This idiom is used by the compiler for the i2b bytecode.
9175 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9176 %{
9177 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9178
9179 format %{ "movsbl $dst, $src\t# i2b" %}
9180 opcode(0x0F, 0xBE);
9181 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9182 ins_pipe(ialu_reg_reg);
9183 %}
9184
9185 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9186 // This idiom is used by the compiler the i2s bytecode.
9187 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9188 %{
9189 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9190
9191 format %{ "movswl $dst, $src\t# i2s" %}
9192 opcode(0x0F, 0xBF);
9193 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9194 ins_pipe(ialu_reg_reg);
9195 %}
9196
9197 // ROL/ROR instructions
9198
9199 // ROL expand
9200 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9201 effect(KILL cr, USE_DEF dst);
9202
9203 format %{ "roll $dst" %}
9204 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9205 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9206 ins_pipe(ialu_reg);
9207 %}
9208
9209 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9210 effect(USE_DEF dst, USE shift, KILL cr);
9211
9212 format %{ "roll $dst, $shift" %}
9213 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9214 ins_encode( reg_opc_imm(dst, shift) );
9215 ins_pipe(ialu_reg);
9216 %}
9217
9218 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9219 %{
9220 effect(USE_DEF dst, USE shift, KILL cr);
9221
9222 format %{ "roll $dst, $shift" %}
9223 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9224 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9225 ins_pipe(ialu_reg_reg);
9226 %}
9227 // end of ROL expand
9228
9229 // Rotate Left by one
9230 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9231 %{
9232 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9233
9234 expand %{
9235 rolI_rReg_imm1(dst, cr);
9236 %}
9237 %}
9238
9239 // Rotate Left by 8-bit immediate
9240 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9241 %{
9242 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9243 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9244
9245 expand %{
9246 rolI_rReg_imm8(dst, lshift, cr);
9247 %}
9248 %}
9249
9250 // Rotate Left by variable
9251 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9252 %{
9253 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9254
9255 expand %{
9256 rolI_rReg_CL(dst, shift, cr);
9257 %}
9258 %}
9259
9260 // Rotate Left by variable
9261 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9262 %{
9263 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9264
9265 expand %{
9266 rolI_rReg_CL(dst, shift, cr);
9267 %}
9268 %}
9269
9270 // ROR expand
9271 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9272 %{
9273 effect(USE_DEF dst, KILL cr);
9274
9275 format %{ "rorl $dst" %}
9276 opcode(0xD1, 0x1); /* D1 /1 */
9277 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9278 ins_pipe(ialu_reg);
9279 %}
9280
9281 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9282 %{
9283 effect(USE_DEF dst, USE shift, KILL cr);
9284
9285 format %{ "rorl $dst, $shift" %}
9286 opcode(0xC1, 0x1); /* C1 /1 ib */
9287 ins_encode(reg_opc_imm(dst, shift));
9288 ins_pipe(ialu_reg);
9289 %}
9290
9291 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9292 %{
9293 effect(USE_DEF dst, USE shift, KILL cr);
9294
9295 format %{ "rorl $dst, $shift" %}
9296 opcode(0xD3, 0x1); /* D3 /1 */
9297 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9298 ins_pipe(ialu_reg_reg);
9299 %}
9300 // end of ROR expand
9301
9302 // Rotate Right by one
9303 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9304 %{
9305 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9306
9307 expand %{
9308 rorI_rReg_imm1(dst, cr);
9309 %}
9310 %}
9311
9312 // Rotate Right by 8-bit immediate
9313 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9314 %{
9315 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9316 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9317
9318 expand %{
9319 rorI_rReg_imm8(dst, rshift, cr);
9320 %}
9321 %}
9322
9323 // Rotate Right by variable
9324 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9325 %{
9326 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9327
9328 expand %{
9329 rorI_rReg_CL(dst, shift, cr);
9330 %}
9331 %}
9332
9333 // Rotate Right by variable
9334 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9335 %{
9336 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9337
9338 expand %{
9339 rorI_rReg_CL(dst, shift, cr);
9340 %}
9341 %}
9342
9343 // for long rotate
9344 // ROL expand
9345 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9346 effect(USE_DEF dst, KILL cr);
9347
9348 format %{ "rolq $dst" %}
9349 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9350 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9351 ins_pipe(ialu_reg);
9352 %}
9353
9354 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9355 effect(USE_DEF dst, USE shift, KILL cr);
9356
9357 format %{ "rolq $dst, $shift" %}
9358 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9359 ins_encode( reg_opc_imm_wide(dst, shift) );
9360 ins_pipe(ialu_reg);
9361 %}
9362
9363 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9364 %{
9365 effect(USE_DEF dst, USE shift, KILL cr);
9366
9367 format %{ "rolq $dst, $shift" %}
9368 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9369 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9370 ins_pipe(ialu_reg_reg);
9371 %}
9372 // end of ROL expand
9373
9374 // Rotate Left by one
9375 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9376 %{
9377 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9378
9379 expand %{
9380 rolL_rReg_imm1(dst, cr);
9381 %}
9382 %}
9383
9384 // Rotate Left by 8-bit immediate
9385 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9386 %{
9387 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9388 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9389
9390 expand %{
9391 rolL_rReg_imm8(dst, lshift, cr);
9392 %}
9393 %}
9394
9395 // Rotate Left by variable
9396 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9397 %{
9398 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9399
9400 expand %{
9401 rolL_rReg_CL(dst, shift, cr);
9402 %}
9403 %}
9404
9405 // Rotate Left by variable
9406 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9407 %{
9408 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9409
9410 expand %{
9411 rolL_rReg_CL(dst, shift, cr);
9412 %}
9413 %}
9414
9415 // ROR expand
9416 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9417 %{
9418 effect(USE_DEF dst, KILL cr);
9419
9420 format %{ "rorq $dst" %}
9421 opcode(0xD1, 0x1); /* D1 /1 */
9422 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9423 ins_pipe(ialu_reg);
9424 %}
9425
9426 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9427 %{
9428 effect(USE_DEF dst, USE shift, KILL cr);
9429
9430 format %{ "rorq $dst, $shift" %}
9431 opcode(0xC1, 0x1); /* C1 /1 ib */
9432 ins_encode(reg_opc_imm_wide(dst, shift));
9433 ins_pipe(ialu_reg);
9434 %}
9435
9436 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9437 %{
9438 effect(USE_DEF dst, USE shift, KILL cr);
9439
9440 format %{ "rorq $dst, $shift" %}
9441 opcode(0xD3, 0x1); /* D3 /1 */
9442 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9443 ins_pipe(ialu_reg_reg);
9444 %}
9445 // end of ROR expand
9446
9447 // Rotate Right by one
9448 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9449 %{
9450 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9451
9452 expand %{
9453 rorL_rReg_imm1(dst, cr);
9454 %}
9455 %}
9456
9457 // Rotate Right by 8-bit immediate
9458 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9459 %{
9460 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9461 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9462
9463 expand %{
9464 rorL_rReg_imm8(dst, rshift, cr);
9465 %}
9466 %}
9467
9468 // Rotate Right by variable
9469 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9470 %{
9471 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9472
9473 expand %{
9474 rorL_rReg_CL(dst, shift, cr);
9475 %}
9476 %}
9477
9478 // Rotate Right by variable
9479 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9480 %{
9481 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9482
9483 expand %{
9484 rorL_rReg_CL(dst, shift, cr);
9485 %}
9486 %}
9487
9488 // Logical Instructions
9489
9490 // Integer Logical Instructions
9491
9492 // And Instructions
9493 // And Register with Register
9494 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9495 %{
9496 match(Set dst (AndI dst src));
9497 effect(KILL cr);
9498
9499 format %{ "andl $dst, $src\t# int" %}
9500 opcode(0x23);
9501 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9502 ins_pipe(ialu_reg_reg);
9503 %}
9504
9505 // And Register with Immediate 255
9506 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9507 %{
9508 match(Set dst (AndI dst src));
9509
9510 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9511 opcode(0x0F, 0xB6);
9512 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9513 ins_pipe(ialu_reg);
9514 %}
9515
9516 // And Register with Immediate 255 and promote to long
9517 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9518 %{
9519 match(Set dst (ConvI2L (AndI src mask)));
9520
9521 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9522 opcode(0x0F, 0xB6);
9523 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9524 ins_pipe(ialu_reg);
9525 %}
9526
9527 // And Register with Immediate 65535
9528 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9529 %{
9530 match(Set dst (AndI dst src));
9531
9532 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9533 opcode(0x0F, 0xB7);
9534 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9535 ins_pipe(ialu_reg);
9536 %}
9537
9538 // And Register with Immediate 65535 and promote to long
9539 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9540 %{
9541 match(Set dst (ConvI2L (AndI src mask)));
9542
9543 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9544 opcode(0x0F, 0xB7);
9545 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9546 ins_pipe(ialu_reg);
9547 %}
9548
9549 // And Register with Immediate
9550 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9551 %{
9552 match(Set dst (AndI dst src));
9553 effect(KILL cr);
9554
9555 format %{ "andl $dst, $src\t# int" %}
9556 opcode(0x81, 0x04); /* Opcode 81 /4 */
9557 ins_encode(OpcSErm(dst, src), Con8or32(src));
9558 ins_pipe(ialu_reg);
9559 %}
9560
9561 // And Register with Memory
9562 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9563 %{
9564 match(Set dst (AndI dst (LoadI src)));
9565 effect(KILL cr);
9566
9567 ins_cost(125);
9568 format %{ "andl $dst, $src\t# int" %}
9569 opcode(0x23);
9570 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9571 ins_pipe(ialu_reg_mem);
9572 %}
9573
9574 // And Memory with Register
9575 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9576 %{
9577 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9578 effect(KILL cr);
9579
9580 ins_cost(150);
9581 format %{ "andb $dst, $src\t# byte" %}
9582 opcode(0x20);
9583 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9584 ins_pipe(ialu_mem_reg);
9585 %}
9586
9587 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9588 %{
9589 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9590 effect(KILL cr);
9591
9592 ins_cost(150);
9593 format %{ "andl $dst, $src\t# int" %}
9594 opcode(0x21); /* Opcode 21 /r */
9595 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9596 ins_pipe(ialu_mem_reg);
9597 %}
9598
9599 // And Memory with Immediate
9600 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9601 %{
9602 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9603 effect(KILL cr);
9604
9605 ins_cost(125);
9606 format %{ "andl $dst, $src\t# int" %}
9607 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9608 ins_encode(REX_mem(dst), OpcSE(src),
9609 RM_opc_mem(secondary, dst), Con8or32(src));
9610 ins_pipe(ialu_mem_imm);
9611 %}
9612
9613 // BMI1 instructions
9614 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9615 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9616 predicate(UseBMI1Instructions);
9617 effect(KILL cr);
9618
9619 ins_cost(125);
9620 format %{ "andnl $dst, $src1, $src2" %}
9621
9622 ins_encode %{
9623 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9624 %}
9625 ins_pipe(ialu_reg_mem);
9626 %}
9627
9628 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9629 match(Set dst (AndI (XorI src1 minus_1) src2));
9630 predicate(UseBMI1Instructions);
9631 effect(KILL cr);
9632
9633 format %{ "andnl $dst, $src1, $src2" %}
9634
9635 ins_encode %{
9636 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9637 %}
9638 ins_pipe(ialu_reg);
9639 %}
9640
9641 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9642 match(Set dst (AndI (SubI imm_zero src) src));
9643 predicate(UseBMI1Instructions);
9644 effect(KILL cr);
9645
9646 format %{ "blsil $dst, $src" %}
9647
9648 ins_encode %{
9649 __ blsil($dst$$Register, $src$$Register);
9650 %}
9651 ins_pipe(ialu_reg);
9652 %}
9653
9654 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9655 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9656 predicate(UseBMI1Instructions);
9657 effect(KILL cr);
9658
9659 ins_cost(125);
9660 format %{ "blsil $dst, $src" %}
9661
9662 ins_encode %{
9663 __ blsil($dst$$Register, $src$$Address);
9664 %}
9665 ins_pipe(ialu_reg_mem);
9666 %}
9667
9668 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9669 %{
9670 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9671 predicate(UseBMI1Instructions);
9672 effect(KILL cr);
9673
9674 ins_cost(125);
9675 format %{ "blsmskl $dst, $src" %}
9676
9677 ins_encode %{
9678 __ blsmskl($dst$$Register, $src$$Address);
9679 %}
9680 ins_pipe(ialu_reg_mem);
9681 %}
9682
9683 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9684 %{
9685 match(Set dst (XorI (AddI src minus_1) src));
9686 predicate(UseBMI1Instructions);
9687 effect(KILL cr);
9688
9689 format %{ "blsmskl $dst, $src" %}
9690
9691 ins_encode %{
9692 __ blsmskl($dst$$Register, $src$$Register);
9693 %}
9694
9695 ins_pipe(ialu_reg);
9696 %}
9697
9698 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9699 %{
9700 match(Set dst (AndI (AddI src minus_1) src) );
9701 predicate(UseBMI1Instructions);
9702 effect(KILL cr);
9703
9704 format %{ "blsrl $dst, $src" %}
9705
9706 ins_encode %{
9707 __ blsrl($dst$$Register, $src$$Register);
9708 %}
9709
9710 ins_pipe(ialu_reg_mem);
9711 %}
9712
9713 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9714 %{
9715 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9716 predicate(UseBMI1Instructions);
9717 effect(KILL cr);
9718
9719 ins_cost(125);
9720 format %{ "blsrl $dst, $src" %}
9721
9722 ins_encode %{
9723 __ blsrl($dst$$Register, $src$$Address);
9724 %}
9725
9726 ins_pipe(ialu_reg);
9727 %}
9728
9729 // Or Instructions
9730 // Or Register with Register
9731 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9732 %{
9733 match(Set dst (OrI dst src));
9734 effect(KILL cr);
9735
9736 format %{ "orl $dst, $src\t# int" %}
9737 opcode(0x0B);
9738 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9739 ins_pipe(ialu_reg_reg);
9740 %}
9741
9742 // Or Register with Immediate
9743 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9744 %{
9745 match(Set dst (OrI dst src));
9746 effect(KILL cr);
9747
9748 format %{ "orl $dst, $src\t# int" %}
9749 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9750 ins_encode(OpcSErm(dst, src), Con8or32(src));
9751 ins_pipe(ialu_reg);
9752 %}
9753
9754 // Or Register with Memory
9755 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9756 %{
9757 match(Set dst (OrI dst (LoadI src)));
9758 effect(KILL cr);
9759
9760 ins_cost(125);
9761 format %{ "orl $dst, $src\t# int" %}
9762 opcode(0x0B);
9763 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9764 ins_pipe(ialu_reg_mem);
9765 %}
9766
9767 // Or Memory with Register
9768 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9769 %{
9770 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9771 effect(KILL cr);
9772
9773 ins_cost(150);
9774 format %{ "orb $dst, $src\t# byte" %}
9775 opcode(0x08);
9776 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9777 ins_pipe(ialu_mem_reg);
9778 %}
9779
9780 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9781 %{
9782 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9783 effect(KILL cr);
9784
9785 ins_cost(150);
9786 format %{ "orl $dst, $src\t# int" %}
9787 opcode(0x09); /* Opcode 09 /r */
9788 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9789 ins_pipe(ialu_mem_reg);
9790 %}
9791
9792 // Or Memory with Immediate
9793 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9794 %{
9795 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9796 effect(KILL cr);
9797
9798 ins_cost(125);
9799 format %{ "orl $dst, $src\t# int" %}
9800 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9801 ins_encode(REX_mem(dst), OpcSE(src),
9802 RM_opc_mem(secondary, dst), Con8or32(src));
9803 ins_pipe(ialu_mem_imm);
9804 %}
9805
9806 // Xor Instructions
9807 // Xor Register with Register
9808 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9809 %{
9810 match(Set dst (XorI dst src));
9811 effect(KILL cr);
9812
9813 format %{ "xorl $dst, $src\t# int" %}
9814 opcode(0x33);
9815 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9816 ins_pipe(ialu_reg_reg);
9817 %}
9818
9819 // Xor Register with Immediate -1
9820 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9821 match(Set dst (XorI dst imm));
9822
9823 format %{ "not $dst" %}
9824 ins_encode %{
9825 __ notl($dst$$Register);
9826 %}
9827 ins_pipe(ialu_reg);
9828 %}
9829
9830 // Xor Register with Immediate
9831 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9832 %{
9833 match(Set dst (XorI dst src));
9834 effect(KILL cr);
9835
9836 format %{ "xorl $dst, $src\t# int" %}
9837 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9838 ins_encode(OpcSErm(dst, src), Con8or32(src));
9839 ins_pipe(ialu_reg);
9840 %}
9841
9842 // Xor Register with Memory
9843 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9844 %{
9845 match(Set dst (XorI dst (LoadI src)));
9846 effect(KILL cr);
9847
9848 ins_cost(125);
9849 format %{ "xorl $dst, $src\t# int" %}
9850 opcode(0x33);
9851 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9852 ins_pipe(ialu_reg_mem);
9853 %}
9854
9855 // Xor Memory with Register
9856 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9857 %{
9858 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9859 effect(KILL cr);
9860
9861 ins_cost(150);
9862 format %{ "xorb $dst, $src\t# byte" %}
9863 opcode(0x30);
9864 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9865 ins_pipe(ialu_mem_reg);
9866 %}
9867
9868 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9869 %{
9870 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9871 effect(KILL cr);
9872
9873 ins_cost(150);
9874 format %{ "xorl $dst, $src\t# int" %}
9875 opcode(0x31); /* Opcode 31 /r */
9876 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9877 ins_pipe(ialu_mem_reg);
9878 %}
9879
9880 // Xor Memory with Immediate
9881 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9882 %{
9883 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9884 effect(KILL cr);
9885
9886 ins_cost(125);
9887 format %{ "xorl $dst, $src\t# int" %}
9888 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9889 ins_encode(REX_mem(dst), OpcSE(src),
9890 RM_opc_mem(secondary, dst), Con8or32(src));
9891 ins_pipe(ialu_mem_imm);
9892 %}
9893
9894
9895 // Long Logical Instructions
9896
9897 // And Instructions
9898 // And Register with Register
9899 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9900 %{
9901 match(Set dst (AndL dst src));
9902 effect(KILL cr);
9903
9904 format %{ "andq $dst, $src\t# long" %}
9905 opcode(0x23);
9906 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9907 ins_pipe(ialu_reg_reg);
9908 %}
9909
9910 // And Register with Immediate 255
9911 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9912 %{
9913 match(Set dst (AndL dst src));
9914
9915 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9916 opcode(0x0F, 0xB6);
9917 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9918 ins_pipe(ialu_reg);
9919 %}
9920
9921 // And Register with Immediate 65535
9922 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9923 %{
9924 match(Set dst (AndL dst src));
9925
9926 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9927 opcode(0x0F, 0xB7);
9928 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9929 ins_pipe(ialu_reg);
9930 %}
9931
9932 // And Register with Immediate
9933 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9934 %{
9935 match(Set dst (AndL dst src));
9936 effect(KILL cr);
9937
9938 format %{ "andq $dst, $src\t# long" %}
9939 opcode(0x81, 0x04); /* Opcode 81 /4 */
9940 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9941 ins_pipe(ialu_reg);
9942 %}
9943
9944 // And Register with Memory
9945 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9946 %{
9947 match(Set dst (AndL dst (LoadL src)));
9948 effect(KILL cr);
9949
9950 ins_cost(125);
9951 format %{ "andq $dst, $src\t# long" %}
9952 opcode(0x23);
9953 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9954 ins_pipe(ialu_reg_mem);
9955 %}
9956
9957 // And Memory with Register
9958 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9959 %{
9960 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9961 effect(KILL cr);
9962
9963 ins_cost(150);
9964 format %{ "andq $dst, $src\t# long" %}
9965 opcode(0x21); /* Opcode 21 /r */
9966 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9967 ins_pipe(ialu_mem_reg);
9968 %}
9969
9970 // And Memory with Immediate
9971 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9972 %{
9973 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9974 effect(KILL cr);
9975
9976 ins_cost(125);
9977 format %{ "andq $dst, $src\t# long" %}
9978 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9979 ins_encode(REX_mem_wide(dst), OpcSE(src),
9980 RM_opc_mem(secondary, dst), Con8or32(src));
9981 ins_pipe(ialu_mem_imm);
9982 %}
9983
9984 // BMI1 instructions
9985 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9986 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9987 predicate(UseBMI1Instructions);
9988 effect(KILL cr);
9989
9990 ins_cost(125);
9991 format %{ "andnq $dst, $src1, $src2" %}
9992
9993 ins_encode %{
9994 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9995 %}
9996 ins_pipe(ialu_reg_mem);
9997 %}
9998
9999 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
10000 match(Set dst (AndL (XorL src1 minus_1) src2));
10001 predicate(UseBMI1Instructions);
10002 effect(KILL cr);
10003
10004 format %{ "andnq $dst, $src1, $src2" %}
10005
10006 ins_encode %{
10007 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
10008 %}
10009 ins_pipe(ialu_reg_mem);
10010 %}
10011
10012 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
10013 match(Set dst (AndL (SubL imm_zero src) src));
10014 predicate(UseBMI1Instructions);
10015 effect(KILL cr);
10016
10017 format %{ "blsiq $dst, $src" %}
10018
10019 ins_encode %{
10020 __ blsiq($dst$$Register, $src$$Register);
10021 %}
10022 ins_pipe(ialu_reg);
10023 %}
10024
10025 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
10026 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
10027 predicate(UseBMI1Instructions);
10028 effect(KILL cr);
10029
10030 ins_cost(125);
10031 format %{ "blsiq $dst, $src" %}
10032
10033 ins_encode %{
10034 __ blsiq($dst$$Register, $src$$Address);
10035 %}
10036 ins_pipe(ialu_reg_mem);
10037 %}
10038
10039 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10040 %{
10041 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
10042 predicate(UseBMI1Instructions);
10043 effect(KILL cr);
10044
10045 ins_cost(125);
10046 format %{ "blsmskq $dst, $src" %}
10047
10048 ins_encode %{
10049 __ blsmskq($dst$$Register, $src$$Address);
10050 %}
10051 ins_pipe(ialu_reg_mem);
10052 %}
10053
10054 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10055 %{
10056 match(Set dst (XorL (AddL src minus_1) src));
10057 predicate(UseBMI1Instructions);
10058 effect(KILL cr);
10059
10060 format %{ "blsmskq $dst, $src" %}
10061
10062 ins_encode %{
10063 __ blsmskq($dst$$Register, $src$$Register);
10064 %}
10065
10066 ins_pipe(ialu_reg);
10067 %}
10068
10069 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10070 %{
10071 match(Set dst (AndL (AddL src minus_1) src) );
10072 predicate(UseBMI1Instructions);
10073 effect(KILL cr);
10074
10075 format %{ "blsrq $dst, $src" %}
10076
10077 ins_encode %{
10078 __ blsrq($dst$$Register, $src$$Register);
10079 %}
10080
10081 ins_pipe(ialu_reg);
10082 %}
10083
10084 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10085 %{
10086 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
10087 predicate(UseBMI1Instructions);
10088 effect(KILL cr);
10089
10090 ins_cost(125);
10091 format %{ "blsrq $dst, $src" %}
10092
10093 ins_encode %{
10094 __ blsrq($dst$$Register, $src$$Address);
10095 %}
10096
10097 ins_pipe(ialu_reg);
10098 %}
10099
10100 // Or Instructions
10101 // Or Register with Register
10102 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10103 %{
10104 match(Set dst (OrL dst src));
10105 effect(KILL cr);
10106
10107 format %{ "orq $dst, $src\t# long" %}
10108 opcode(0x0B);
10109 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10110 ins_pipe(ialu_reg_reg);
10111 %}
10112
10113 // Use any_RegP to match R15 (TLS register) without spilling.
10114 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
10115 match(Set dst (OrL dst (CastP2X src)));
10116 effect(KILL cr);
10117
10118 format %{ "orq $dst, $src\t# long" %}
10119 opcode(0x0B);
10120 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10121 ins_pipe(ialu_reg_reg);
10122 %}
10123
10124
10125 // Or Register with Immediate
10126 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10127 %{
10128 match(Set dst (OrL dst src));
10129 effect(KILL cr);
10130
10131 format %{ "orq $dst, $src\t# long" %}
10132 opcode(0x81, 0x01); /* Opcode 81 /1 id */
10133 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10134 ins_pipe(ialu_reg);
10135 %}
10136
10137 // Or Register with Memory
10138 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10139 %{
10140 match(Set dst (OrL dst (LoadL src)));
10141 effect(KILL cr);
10142
10143 ins_cost(125);
10144 format %{ "orq $dst, $src\t# long" %}
10145 opcode(0x0B);
10146 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10147 ins_pipe(ialu_reg_mem);
10148 %}
10149
10150 // Or Memory with Register
10151 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10152 %{
10153 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10154 effect(KILL cr);
10155
10156 ins_cost(150);
10157 format %{ "orq $dst, $src\t# long" %}
10158 opcode(0x09); /* Opcode 09 /r */
10159 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10160 ins_pipe(ialu_mem_reg);
10161 %}
10162
10163 // Or Memory with Immediate
10164 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10165 %{
10166 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10167 effect(KILL cr);
10168
10169 ins_cost(125);
10170 format %{ "orq $dst, $src\t# long" %}
10171 opcode(0x81, 0x1); /* Opcode 81 /1 id */
10172 ins_encode(REX_mem_wide(dst), OpcSE(src),
10173 RM_opc_mem(secondary, dst), Con8or32(src));
10174 ins_pipe(ialu_mem_imm);
10175 %}
10176
10177 // Xor Instructions
10178 // Xor Register with Register
10179 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10180 %{
10181 match(Set dst (XorL dst src));
10182 effect(KILL cr);
10183
10184 format %{ "xorq $dst, $src\t# long" %}
10185 opcode(0x33);
10186 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10187 ins_pipe(ialu_reg_reg);
10188 %}
10189
10190 // Xor Register with Immediate -1
10191 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10192 match(Set dst (XorL dst imm));
10193
10194 format %{ "notq $dst" %}
10195 ins_encode %{
10196 __ notq($dst$$Register);
10197 %}
10198 ins_pipe(ialu_reg);
10199 %}
10200
10201 // Xor Register with Immediate
10202 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10203 %{
10204 match(Set dst (XorL dst src));
10205 effect(KILL cr);
10206
10207 format %{ "xorq $dst, $src\t# long" %}
10208 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10209 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10210 ins_pipe(ialu_reg);
10211 %}
10212
10213 // Xor Register with Memory
10214 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10215 %{
10216 match(Set dst (XorL dst (LoadL src)));
10217 effect(KILL cr);
10218
10219 ins_cost(125);
10220 format %{ "xorq $dst, $src\t# long" %}
10221 opcode(0x33);
10222 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10223 ins_pipe(ialu_reg_mem);
10224 %}
10225
10226 // Xor Memory with Register
10227 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10228 %{
10229 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10230 effect(KILL cr);
10231
10232 ins_cost(150);
10233 format %{ "xorq $dst, $src\t# long" %}
10234 opcode(0x31); /* Opcode 31 /r */
10235 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10236 ins_pipe(ialu_mem_reg);
10237 %}
10238
10239 // Xor Memory with Immediate
10240 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10241 %{
10242 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10243 effect(KILL cr);
10244
10245 ins_cost(125);
10246 format %{ "xorq $dst, $src\t# long" %}
10247 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10248 ins_encode(REX_mem_wide(dst), OpcSE(src),
10249 RM_opc_mem(secondary, dst), Con8or32(src));
10250 ins_pipe(ialu_mem_imm);
10251 %}
10252
10253 // Convert Int to Boolean
10254 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10255 %{
10256 match(Set dst (Conv2B src));
10257 effect(KILL cr);
10258
10259 format %{ "testl $src, $src\t# ci2b\n\t"
10260 "setnz $dst\n\t"
10261 "movzbl $dst, $dst" %}
10262 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10263 setNZ_reg(dst),
10264 REX_reg_breg(dst, dst), // movzbl
10265 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10266 ins_pipe(pipe_slow); // XXX
10267 %}
10268
10269 // Convert Pointer to Boolean
10270 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10271 %{
10272 match(Set dst (Conv2B src));
10273 effect(KILL cr);
10274
10275 format %{ "testq $src, $src\t# cp2b\n\t"
10276 "setnz $dst\n\t"
10277 "movzbl $dst, $dst" %}
10278 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10279 setNZ_reg(dst),
10280 REX_reg_breg(dst, dst), // movzbl
10281 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10282 ins_pipe(pipe_slow); // XXX
10283 %}
10284
10285 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10286 %{
10287 match(Set dst (CmpLTMask p q));
10288 effect(KILL cr);
10289
10290 ins_cost(400);
10291 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10292 "setlt $dst\n\t"
10293 "movzbl $dst, $dst\n\t"
10294 "negl $dst" %}
10295 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10296 setLT_reg(dst),
10297 REX_reg_breg(dst, dst), // movzbl
10298 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10299 neg_reg(dst));
10300 ins_pipe(pipe_slow);
10301 %}
10302
10303 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10304 %{
10305 match(Set dst (CmpLTMask dst zero));
10306 effect(KILL cr);
10307
10308 ins_cost(100);
10309 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10310 ins_encode %{
10311 __ sarl($dst$$Register, 31);
10312 %}
10313 ins_pipe(ialu_reg);
10314 %}
10315
10316 /* Better to save a register than avoid a branch */
10317 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10318 %{
10319 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10320 effect(KILL cr);
10321 ins_cost(300);
10322 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10323 "jge done\n\t"
10324 "addl $p,$y\n"
10325 "done: " %}
10326 ins_encode %{
10327 Register Rp = $p$$Register;
10328 Register Rq = $q$$Register;
10329 Register Ry = $y$$Register;
10330 Label done;
10331 __ subl(Rp, Rq);
10332 __ jccb(Assembler::greaterEqual, done);
10333 __ addl(Rp, Ry);
10334 __ bind(done);
10335 %}
10336 ins_pipe(pipe_cmplt);
10337 %}
10338
10339 /* Better to save a register than avoid a branch */
10340 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10341 %{
10342 match(Set y (AndI (CmpLTMask p q) y));
10343 effect(KILL cr);
10344
10345 ins_cost(300);
10346
10347 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10348 "jlt done\n\t"
10349 "xorl $y, $y\n"
10350 "done: " %}
10351 ins_encode %{
10352 Register Rp = $p$$Register;
10353 Register Rq = $q$$Register;
10354 Register Ry = $y$$Register;
10355 Label done;
10356 __ cmpl(Rp, Rq);
10357 __ jccb(Assembler::less, done);
10358 __ xorl(Ry, Ry);
10359 __ bind(done);
10360 %}
10361 ins_pipe(pipe_cmplt);
10362 %}
10363
10364
10365 //---------- FP Instructions------------------------------------------------
10366
10367 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10368 %{
10369 match(Set cr (CmpF src1 src2));
10370
10371 ins_cost(145);
10372 format %{ "ucomiss $src1, $src2\n\t"
10373 "jnp,s exit\n\t"
10374 "pushfq\t# saw NaN, set CF\n\t"
10375 "andq [rsp], #0xffffff2b\n\t"
10376 "popfq\n"
10377 "exit:" %}
10378 ins_encode %{
10379 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10380 emit_cmpfp_fixup(_masm);
10381 %}
10382 ins_pipe(pipe_slow);
10383 %}
10384
10385 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10386 match(Set cr (CmpF src1 src2));
10387
10388 ins_cost(100);
10389 format %{ "ucomiss $src1, $src2" %}
10390 ins_encode %{
10391 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10392 %}
10393 ins_pipe(pipe_slow);
10394 %}
10395
10396 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10397 %{
10398 match(Set cr (CmpF src1 (LoadF src2)));
10399
10400 ins_cost(145);
10401 format %{ "ucomiss $src1, $src2\n\t"
10402 "jnp,s exit\n\t"
10403 "pushfq\t# saw NaN, set CF\n\t"
10404 "andq [rsp], #0xffffff2b\n\t"
10405 "popfq\n"
10406 "exit:" %}
10407 ins_encode %{
10408 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10409 emit_cmpfp_fixup(_masm);
10410 %}
10411 ins_pipe(pipe_slow);
10412 %}
10413
10414 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10415 match(Set cr (CmpF src1 (LoadF src2)));
10416
10417 ins_cost(100);
10418 format %{ "ucomiss $src1, $src2" %}
10419 ins_encode %{
10420 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10421 %}
10422 ins_pipe(pipe_slow);
10423 %}
10424
10425 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10426 match(Set cr (CmpF src con));
10427
10428 ins_cost(145);
10429 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10430 "jnp,s exit\n\t"
10431 "pushfq\t# saw NaN, set CF\n\t"
10432 "andq [rsp], #0xffffff2b\n\t"
10433 "popfq\n"
10434 "exit:" %}
10435 ins_encode %{
10436 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10437 emit_cmpfp_fixup(_masm);
10438 %}
10439 ins_pipe(pipe_slow);
10440 %}
10441
10442 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10443 match(Set cr (CmpF src con));
10444 ins_cost(100);
10445 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10446 ins_encode %{
10447 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10448 %}
10449 ins_pipe(pipe_slow);
10450 %}
10451
10452 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10453 %{
10454 match(Set cr (CmpD src1 src2));
10455
10456 ins_cost(145);
10457 format %{ "ucomisd $src1, $src2\n\t"
10458 "jnp,s exit\n\t"
10459 "pushfq\t# saw NaN, set CF\n\t"
10460 "andq [rsp], #0xffffff2b\n\t"
10461 "popfq\n"
10462 "exit:" %}
10463 ins_encode %{
10464 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10465 emit_cmpfp_fixup(_masm);
10466 %}
10467 ins_pipe(pipe_slow);
10468 %}
10469
10470 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10471 match(Set cr (CmpD src1 src2));
10472
10473 ins_cost(100);
10474 format %{ "ucomisd $src1, $src2 test" %}
10475 ins_encode %{
10476 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10477 %}
10478 ins_pipe(pipe_slow);
10479 %}
10480
10481 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10482 %{
10483 match(Set cr (CmpD src1 (LoadD src2)));
10484
10485 ins_cost(145);
10486 format %{ "ucomisd $src1, $src2\n\t"
10487 "jnp,s exit\n\t"
10488 "pushfq\t# saw NaN, set CF\n\t"
10489 "andq [rsp], #0xffffff2b\n\t"
10490 "popfq\n"
10491 "exit:" %}
10492 ins_encode %{
10493 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10494 emit_cmpfp_fixup(_masm);
10495 %}
10496 ins_pipe(pipe_slow);
10497 %}
10498
10499 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10500 match(Set cr (CmpD src1 (LoadD src2)));
10501
10502 ins_cost(100);
10503 format %{ "ucomisd $src1, $src2" %}
10504 ins_encode %{
10505 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10506 %}
10507 ins_pipe(pipe_slow);
10508 %}
10509
10510 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10511 match(Set cr (CmpD src con));
10512
10513 ins_cost(145);
10514 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10515 "jnp,s exit\n\t"
10516 "pushfq\t# saw NaN, set CF\n\t"
10517 "andq [rsp], #0xffffff2b\n\t"
10518 "popfq\n"
10519 "exit:" %}
10520 ins_encode %{
10521 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10522 emit_cmpfp_fixup(_masm);
10523 %}
10524 ins_pipe(pipe_slow);
10525 %}
10526
10527 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10528 match(Set cr (CmpD src con));
10529 ins_cost(100);
10530 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10531 ins_encode %{
10532 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10533 %}
10534 ins_pipe(pipe_slow);
10535 %}
10536
10537 // Compare into -1,0,1
10538 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10539 %{
10540 match(Set dst (CmpF3 src1 src2));
10541 effect(KILL cr);
10542
10543 ins_cost(275);
10544 format %{ "ucomiss $src1, $src2\n\t"
10545 "movl $dst, #-1\n\t"
10546 "jp,s done\n\t"
10547 "jb,s done\n\t"
10548 "setne $dst\n\t"
10549 "movzbl $dst, $dst\n"
10550 "done:" %}
10551 ins_encode %{
10552 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10553 emit_cmpfp3(_masm, $dst$$Register);
10554 %}
10555 ins_pipe(pipe_slow);
10556 %}
10557
10558 // Compare into -1,0,1
10559 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10560 %{
10561 match(Set dst (CmpF3 src1 (LoadF src2)));
10562 effect(KILL cr);
10563
10564 ins_cost(275);
10565 format %{ "ucomiss $src1, $src2\n\t"
10566 "movl $dst, #-1\n\t"
10567 "jp,s done\n\t"
10568 "jb,s done\n\t"
10569 "setne $dst\n\t"
10570 "movzbl $dst, $dst\n"
10571 "done:" %}
10572 ins_encode %{
10573 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10574 emit_cmpfp3(_masm, $dst$$Register);
10575 %}
10576 ins_pipe(pipe_slow);
10577 %}
10578
10579 // Compare into -1,0,1
10580 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10581 match(Set dst (CmpF3 src con));
10582 effect(KILL cr);
10583
10584 ins_cost(275);
10585 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10586 "movl $dst, #-1\n\t"
10587 "jp,s done\n\t"
10588 "jb,s done\n\t"
10589 "setne $dst\n\t"
10590 "movzbl $dst, $dst\n"
10591 "done:" %}
10592 ins_encode %{
10593 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10594 emit_cmpfp3(_masm, $dst$$Register);
10595 %}
10596 ins_pipe(pipe_slow);
10597 %}
10598
10599 // Compare into -1,0,1
10600 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10601 %{
10602 match(Set dst (CmpD3 src1 src2));
10603 effect(KILL cr);
10604
10605 ins_cost(275);
10606 format %{ "ucomisd $src1, $src2\n\t"
10607 "movl $dst, #-1\n\t"
10608 "jp,s done\n\t"
10609 "jb,s done\n\t"
10610 "setne $dst\n\t"
10611 "movzbl $dst, $dst\n"
10612 "done:" %}
10613 ins_encode %{
10614 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10615 emit_cmpfp3(_masm, $dst$$Register);
10616 %}
10617 ins_pipe(pipe_slow);
10618 %}
10619
10620 // Compare into -1,0,1
10621 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10622 %{
10623 match(Set dst (CmpD3 src1 (LoadD src2)));
10624 effect(KILL cr);
10625
10626 ins_cost(275);
10627 format %{ "ucomisd $src1, $src2\n\t"
10628 "movl $dst, #-1\n\t"
10629 "jp,s done\n\t"
10630 "jb,s done\n\t"
10631 "setne $dst\n\t"
10632 "movzbl $dst, $dst\n"
10633 "done:" %}
10634 ins_encode %{
10635 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10636 emit_cmpfp3(_masm, $dst$$Register);
10637 %}
10638 ins_pipe(pipe_slow);
10639 %}
10640
10641 // Compare into -1,0,1
10642 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10643 match(Set dst (CmpD3 src con));
10644 effect(KILL cr);
10645
10646 ins_cost(275);
10647 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10648 "movl $dst, #-1\n\t"
10649 "jp,s done\n\t"
10650 "jb,s done\n\t"
10651 "setne $dst\n\t"
10652 "movzbl $dst, $dst\n"
10653 "done:" %}
10654 ins_encode %{
10655 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10656 emit_cmpfp3(_masm, $dst$$Register);
10657 %}
10658 ins_pipe(pipe_slow);
10659 %}
10660
10661 //----------Arithmetic Conversion Instructions---------------------------------
10662
10663 instruct roundFloat_nop(regF dst)
10664 %{
10665 match(Set dst (RoundFloat dst));
10666
10667 ins_cost(0);
10668 ins_encode();
10669 ins_pipe(empty);
10670 %}
10671
10672 instruct roundDouble_nop(regD dst)
10673 %{
10674 match(Set dst (RoundDouble dst));
10675
10676 ins_cost(0);
10677 ins_encode();
10678 ins_pipe(empty);
10679 %}
10680
10681 instruct convF2D_reg_reg(regD dst, regF src)
10682 %{
10683 match(Set dst (ConvF2D src));
10684
10685 format %{ "cvtss2sd $dst, $src" %}
10686 ins_encode %{
10687 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10688 %}
10689 ins_pipe(pipe_slow); // XXX
10690 %}
10691
10692 instruct convF2D_reg_mem(regD dst, memory src)
10693 %{
10694 match(Set dst (ConvF2D (LoadF src)));
10695
10696 format %{ "cvtss2sd $dst, $src" %}
10697 ins_encode %{
10698 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10699 %}
10700 ins_pipe(pipe_slow); // XXX
10701 %}
10702
10703 instruct convD2F_reg_reg(regF dst, regD src)
10704 %{
10705 match(Set dst (ConvD2F src));
10706
10707 format %{ "cvtsd2ss $dst, $src" %}
10708 ins_encode %{
10709 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10710 %}
10711 ins_pipe(pipe_slow); // XXX
10712 %}
10713
10714 instruct convD2F_reg_mem(regF dst, memory src)
10715 %{
10716 match(Set dst (ConvD2F (LoadD src)));
10717
10718 format %{ "cvtsd2ss $dst, $src" %}
10719 ins_encode %{
10720 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10721 %}
10722 ins_pipe(pipe_slow); // XXX
10723 %}
10724
10725 // XXX do mem variants
10726 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10727 %{
10728 match(Set dst (ConvF2I src));
10729 effect(KILL cr);
10730
10731 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10732 "cmpl $dst, #0x80000000\n\t"
10733 "jne,s done\n\t"
10734 "subq rsp, #8\n\t"
10735 "movss [rsp], $src\n\t"
10736 "call f2i_fixup\n\t"
10737 "popq $dst\n"
10738 "done: "%}
10739 ins_encode %{
10740 Label done;
10741 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10742 __ cmpl($dst$$Register, 0x80000000);
10743 __ jccb(Assembler::notEqual, done);
10744 __ subptr(rsp, 8);
10745 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10746 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10747 __ pop($dst$$Register);
10748 __ bind(done);
10749 %}
10750 ins_pipe(pipe_slow);
10751 %}
10752
10753 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10754 %{
10755 match(Set dst (ConvF2L src));
10756 effect(KILL cr);
10757
10758 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10759 "cmpq $dst, [0x8000000000000000]\n\t"
10760 "jne,s done\n\t"
10761 "subq rsp, #8\n\t"
10762 "movss [rsp], $src\n\t"
10763 "call f2l_fixup\n\t"
10764 "popq $dst\n"
10765 "done: "%}
10766 ins_encode %{
10767 Label done;
10768 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10769 __ cmp64($dst$$Register,
10770 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10771 __ jccb(Assembler::notEqual, done);
10772 __ subptr(rsp, 8);
10773 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10774 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10775 __ pop($dst$$Register);
10776 __ bind(done);
10777 %}
10778 ins_pipe(pipe_slow);
10779 %}
10780
10781 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10782 %{
10783 match(Set dst (ConvD2I src));
10784 effect(KILL cr);
10785
10786 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10787 "cmpl $dst, #0x80000000\n\t"
10788 "jne,s done\n\t"
10789 "subq rsp, #8\n\t"
10790 "movsd [rsp], $src\n\t"
10791 "call d2i_fixup\n\t"
10792 "popq $dst\n"
10793 "done: "%}
10794 ins_encode %{
10795 Label done;
10796 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10797 __ cmpl($dst$$Register, 0x80000000);
10798 __ jccb(Assembler::notEqual, done);
10799 __ subptr(rsp, 8);
10800 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10801 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10802 __ pop($dst$$Register);
10803 __ bind(done);
10804 %}
10805 ins_pipe(pipe_slow);
10806 %}
10807
10808 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10809 %{
10810 match(Set dst (ConvD2L src));
10811 effect(KILL cr);
10812
10813 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10814 "cmpq $dst, [0x8000000000000000]\n\t"
10815 "jne,s done\n\t"
10816 "subq rsp, #8\n\t"
10817 "movsd [rsp], $src\n\t"
10818 "call d2l_fixup\n\t"
10819 "popq $dst\n"
10820 "done: "%}
10821 ins_encode %{
10822 Label done;
10823 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10824 __ cmp64($dst$$Register,
10825 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10826 __ jccb(Assembler::notEqual, done);
10827 __ subptr(rsp, 8);
10828 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10829 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10830 __ pop($dst$$Register);
10831 __ bind(done);
10832 %}
10833 ins_pipe(pipe_slow);
10834 %}
10835
10836 instruct convI2F_reg_reg(regF dst, rRegI src)
10837 %{
10838 predicate(!UseXmmI2F);
10839 match(Set dst (ConvI2F src));
10840
10841 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10842 ins_encode %{
10843 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10844 %}
10845 ins_pipe(pipe_slow); // XXX
10846 %}
10847
10848 instruct convI2F_reg_mem(regF dst, memory src)
10849 %{
10850 match(Set dst (ConvI2F (LoadI src)));
10851
10852 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10853 ins_encode %{
10854 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10855 %}
10856 ins_pipe(pipe_slow); // XXX
10857 %}
10858
10859 instruct convI2D_reg_reg(regD dst, rRegI src)
10860 %{
10861 predicate(!UseXmmI2D);
10862 match(Set dst (ConvI2D src));
10863
10864 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10865 ins_encode %{
10866 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10867 %}
10868 ins_pipe(pipe_slow); // XXX
10869 %}
10870
10871 instruct convI2D_reg_mem(regD dst, memory src)
10872 %{
10873 match(Set dst (ConvI2D (LoadI src)));
10874
10875 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10876 ins_encode %{
10877 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10878 %}
10879 ins_pipe(pipe_slow); // XXX
10880 %}
10881
10882 instruct convXI2F_reg(regF dst, rRegI src)
10883 %{
10884 predicate(UseXmmI2F);
10885 match(Set dst (ConvI2F src));
10886
10887 format %{ "movdl $dst, $src\n\t"
10888 "cvtdq2psl $dst, $dst\t# i2f" %}
10889 ins_encode %{
10890 __ movdl($dst$$XMMRegister, $src$$Register);
10891 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10892 %}
10893 ins_pipe(pipe_slow); // XXX
10894 %}
10895
10896 instruct convXI2D_reg(regD dst, rRegI src)
10897 %{
10898 predicate(UseXmmI2D);
10899 match(Set dst (ConvI2D src));
10900
10901 format %{ "movdl $dst, $src\n\t"
10902 "cvtdq2pdl $dst, $dst\t# i2d" %}
10903 ins_encode %{
10904 __ movdl($dst$$XMMRegister, $src$$Register);
10905 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10906 %}
10907 ins_pipe(pipe_slow); // XXX
10908 %}
10909
10910 instruct convL2F_reg_reg(regF dst, rRegL src)
10911 %{
10912 match(Set dst (ConvL2F src));
10913
10914 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10915 ins_encode %{
10916 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10917 %}
10918 ins_pipe(pipe_slow); // XXX
10919 %}
10920
10921 instruct convL2F_reg_mem(regF dst, memory src)
10922 %{
10923 match(Set dst (ConvL2F (LoadL src)));
10924
10925 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10926 ins_encode %{
10927 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10928 %}
10929 ins_pipe(pipe_slow); // XXX
10930 %}
10931
10932 instruct convL2D_reg_reg(regD dst, rRegL src)
10933 %{
10934 match(Set dst (ConvL2D src));
10935
10936 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10937 ins_encode %{
10938 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10939 %}
10940 ins_pipe(pipe_slow); // XXX
10941 %}
10942
10943 instruct convL2D_reg_mem(regD dst, memory src)
10944 %{
10945 match(Set dst (ConvL2D (LoadL src)));
10946
10947 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10948 ins_encode %{
10949 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10950 %}
10951 ins_pipe(pipe_slow); // XXX
10952 %}
10953
10954 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10955 %{
10956 match(Set dst (ConvI2L src));
10957
10958 ins_cost(125);
10959 format %{ "movslq $dst, $src\t# i2l" %}
10960 ins_encode %{
10961 __ movslq($dst$$Register, $src$$Register);
10962 %}
10963 ins_pipe(ialu_reg_reg);
10964 %}
10965
10966 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10967 // %{
10968 // match(Set dst (ConvI2L src));
10969 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10970 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10971 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10972 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10973 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10974 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10975
10976 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10977 // ins_encode(enc_copy(dst, src));
10978 // // opcode(0x63); // needs REX.W
10979 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10980 // ins_pipe(ialu_reg_reg);
10981 // %}
10982
10983 // Zero-extend convert int to long
10984 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10985 %{
10986 match(Set dst (AndL (ConvI2L src) mask));
10987
10988 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10989 ins_encode %{
10990 if ($dst$$reg != $src$$reg) {
10991 __ movl($dst$$Register, $src$$Register);
10992 }
10993 %}
10994 ins_pipe(ialu_reg_reg);
10995 %}
10996
10997 // Zero-extend convert int to long
10998 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10999 %{
11000 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
11001
11002 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11003 ins_encode %{
11004 __ movl($dst$$Register, $src$$Address);
11005 %}
11006 ins_pipe(ialu_reg_mem);
11007 %}
11008
11009 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
11010 %{
11011 match(Set dst (AndL src mask));
11012
11013 format %{ "movl $dst, $src\t# zero-extend long" %}
11014 ins_encode %{
11015 __ movl($dst$$Register, $src$$Register);
11016 %}
11017 ins_pipe(ialu_reg_reg);
11018 %}
11019
11020 instruct convL2I_reg_reg(rRegI dst, rRegL src)
11021 %{
11022 match(Set dst (ConvL2I src));
11023
11024 format %{ "movl $dst, $src\t# l2i" %}
11025 ins_encode %{
11026 __ movl($dst$$Register, $src$$Register);
11027 %}
11028 ins_pipe(ialu_reg_reg);
11029 %}
11030
11031
11032 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11033 match(Set dst (MoveF2I src));
11034 effect(DEF dst, USE src);
11035
11036 ins_cost(125);
11037 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
11038 ins_encode %{
11039 __ movl($dst$$Register, Address(rsp, $src$$disp));
11040 %}
11041 ins_pipe(ialu_reg_mem);
11042 %}
11043
11044 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11045 match(Set dst (MoveI2F src));
11046 effect(DEF dst, USE src);
11047
11048 ins_cost(125);
11049 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
11050 ins_encode %{
11051 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11052 %}
11053 ins_pipe(pipe_slow);
11054 %}
11055
11056 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
11057 match(Set dst (MoveD2L src));
11058 effect(DEF dst, USE src);
11059
11060 ins_cost(125);
11061 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
11062 ins_encode %{
11063 __ movq($dst$$Register, Address(rsp, $src$$disp));
11064 %}
11065 ins_pipe(ialu_reg_mem);
11066 %}
11067
11068 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
11069 predicate(!UseXmmLoadAndClearUpper);
11070 match(Set dst (MoveL2D src));
11071 effect(DEF dst, USE src);
11072
11073 ins_cost(125);
11074 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
11075 ins_encode %{
11076 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11077 %}
11078 ins_pipe(pipe_slow);
11079 %}
11080
11081 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11082 predicate(UseXmmLoadAndClearUpper);
11083 match(Set dst (MoveL2D src));
11084 effect(DEF dst, USE src);
11085
11086 ins_cost(125);
11087 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
11088 ins_encode %{
11089 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11090 %}
11091 ins_pipe(pipe_slow);
11092 %}
11093
11094
11095 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11096 match(Set dst (MoveF2I src));
11097 effect(DEF dst, USE src);
11098
11099 ins_cost(95); // XXX
11100 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
11101 ins_encode %{
11102 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11103 %}
11104 ins_pipe(pipe_slow);
11105 %}
11106
11107 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11108 match(Set dst (MoveI2F src));
11109 effect(DEF dst, USE src);
11110
11111 ins_cost(100);
11112 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
11113 ins_encode %{
11114 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11115 %}
11116 ins_pipe( ialu_mem_reg );
11117 %}
11118
11119 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11120 match(Set dst (MoveD2L src));
11121 effect(DEF dst, USE src);
11122
11123 ins_cost(95); // XXX
11124 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
11125 ins_encode %{
11126 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11127 %}
11128 ins_pipe(pipe_slow);
11129 %}
11130
11131 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
11132 match(Set dst (MoveL2D src));
11133 effect(DEF dst, USE src);
11134
11135 ins_cost(100);
11136 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
11137 ins_encode %{
11138 __ movq(Address(rsp, $dst$$disp), $src$$Register);
11139 %}
11140 ins_pipe(ialu_mem_reg);
11141 %}
11142
11143 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
11144 match(Set dst (MoveF2I src));
11145 effect(DEF dst, USE src);
11146 ins_cost(85);
11147 format %{ "movd $dst,$src\t# MoveF2I" %}
11148 ins_encode %{
11149 __ movdl($dst$$Register, $src$$XMMRegister);
11150 %}
11151 ins_pipe( pipe_slow );
11152 %}
11153
11154 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
11155 match(Set dst (MoveD2L src));
11156 effect(DEF dst, USE src);
11157 ins_cost(85);
11158 format %{ "movd $dst,$src\t# MoveD2L" %}
11159 ins_encode %{
11160 __ movdq($dst$$Register, $src$$XMMRegister);
11161 %}
11162 ins_pipe( pipe_slow );
11163 %}
11164
11165 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11166 match(Set dst (MoveI2F src));
11167 effect(DEF dst, USE src);
11168 ins_cost(100);
11169 format %{ "movd $dst,$src\t# MoveI2F" %}
11170 ins_encode %{
11171 __ movdl($dst$$XMMRegister, $src$$Register);
11172 %}
11173 ins_pipe( pipe_slow );
11174 %}
11175
11176 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11177 match(Set dst (MoveL2D src));
11178 effect(DEF dst, USE src);
11179 ins_cost(100);
11180 format %{ "movd $dst,$src\t# MoveL2D" %}
11181 ins_encode %{
11182 __ movdq($dst$$XMMRegister, $src$$Register);
11183 %}
11184 ins_pipe( pipe_slow );
11185 %}
11186
11187
11188 // =======================================================================
11189 // fast clearing of an array
11190 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11191 Universe dummy, rFlagsReg cr)
11192 %{
11193 predicate(!((ClearArrayNode*)n)->is_large());
11194 match(Set dummy (ClearArray cnt base));
11195 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11196
11197 format %{ $$template
11198 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11199 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11200 $$emit$$"jg LARGE\n\t"
11201 $$emit$$"dec rcx\n\t"
11202 $$emit$$"js DONE\t# Zero length\n\t"
11203 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11204 $$emit$$"dec rcx\n\t"
11205 $$emit$$"jge LOOP\n\t"
11206 $$emit$$"jmp DONE\n\t"
11207 $$emit$$"# LARGE:\n\t"
11208 if (UseFastStosb) {
11209 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11210 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11211 } else if (UseXMMForObjInit) {
11212 $$emit$$"mov rdi,rax\n\t"
11213 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11214 $$emit$$"jmpq L_zero_64_bytes\n\t"
11215 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11216 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11217 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11218 $$emit$$"add 0x40,rax\n\t"
11219 $$emit$$"# L_zero_64_bytes:\n\t"
11220 $$emit$$"sub 0x8,rcx\n\t"
11221 $$emit$$"jge L_loop\n\t"
11222 $$emit$$"add 0x4,rcx\n\t"
11223 $$emit$$"jl L_tail\n\t"
11224 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11225 $$emit$$"add 0x20,rax\n\t"
11226 $$emit$$"sub 0x4,rcx\n\t"
11227 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11228 $$emit$$"add 0x4,rcx\n\t"
11229 $$emit$$"jle L_end\n\t"
11230 $$emit$$"dec rcx\n\t"
11231 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11232 $$emit$$"vmovq xmm0,(rax)\n\t"
11233 $$emit$$"add 0x8,rax\n\t"
11234 $$emit$$"dec rcx\n\t"
11235 $$emit$$"jge L_sloop\n\t"
11236 $$emit$$"# L_end:\n\t"
11237 } else {
11238 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11239 }
11240 $$emit$$"# DONE"
11241 %}
11242 ins_encode %{
11243 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11244 $tmp$$XMMRegister, false);
11245 %}
11246 ins_pipe(pipe_slow);
11247 %}
11248
11249 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11250 Universe dummy, rFlagsReg cr)
11251 %{
11252 predicate(((ClearArrayNode*)n)->is_large());
11253 match(Set dummy (ClearArray cnt base));
11254 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11255
11256 format %{ $$template
11257 if (UseFastStosb) {
11258 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11259 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11260 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11261 } else if (UseXMMForObjInit) {
11262 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11263 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11264 $$emit$$"jmpq L_zero_64_bytes\n\t"
11265 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11266 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11267 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11268 $$emit$$"add 0x40,rax\n\t"
11269 $$emit$$"# L_zero_64_bytes:\n\t"
11270 $$emit$$"sub 0x8,rcx\n\t"
11271 $$emit$$"jge L_loop\n\t"
11272 $$emit$$"add 0x4,rcx\n\t"
11273 $$emit$$"jl L_tail\n\t"
11274 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11275 $$emit$$"add 0x20,rax\n\t"
11276 $$emit$$"sub 0x4,rcx\n\t"
11277 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11278 $$emit$$"add 0x4,rcx\n\t"
11279 $$emit$$"jle L_end\n\t"
11280 $$emit$$"dec rcx\n\t"
11281 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11282 $$emit$$"vmovq xmm0,(rax)\n\t"
11283 $$emit$$"add 0x8,rax\n\t"
11284 $$emit$$"dec rcx\n\t"
11285 $$emit$$"jge L_sloop\n\t"
11286 $$emit$$"# L_end:\n\t"
11287 } else {
11288 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11289 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11290 }
11291 %}
11292 ins_encode %{
11293 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11294 $tmp$$XMMRegister, true);
11295 %}
11296 ins_pipe(pipe_slow);
11297 %}
11298
11299 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11300 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11301 %{
11302 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11303 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11304 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11305
11306 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11307 ins_encode %{
11308 __ string_compare($str1$$Register, $str2$$Register,
11309 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11310 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11311 %}
11312 ins_pipe( pipe_slow );
11313 %}
11314
11315 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11316 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11317 %{
11318 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11319 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11320 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11321
11322 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11323 ins_encode %{
11324 __ string_compare($str1$$Register, $str2$$Register,
11325 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11326 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11327 %}
11328 ins_pipe( pipe_slow );
11329 %}
11330
11331 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11332 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11333 %{
11334 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11335 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11336 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11337
11338 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11339 ins_encode %{
11340 __ string_compare($str1$$Register, $str2$$Register,
11341 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11342 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11343 %}
11344 ins_pipe( pipe_slow );
11345 %}
11346
11347 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11348 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11349 %{
11350 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11351 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11352 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11353
11354 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11355 ins_encode %{
11356 __ string_compare($str2$$Register, $str1$$Register,
11357 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11358 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11359 %}
11360 ins_pipe( pipe_slow );
11361 %}
11362
11363 // fast search of substring with known size.
11364 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11365 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11366 %{
11367 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11368 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11369 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11370
11371 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11372 ins_encode %{
11373 int icnt2 = (int)$int_cnt2$$constant;
11374 if (icnt2 >= 16) {
11375 // IndexOf for constant substrings with size >= 16 elements
11376 // which don't need to be loaded through stack.
11377 __ string_indexofC8($str1$$Register, $str2$$Register,
11378 $cnt1$$Register, $cnt2$$Register,
11379 icnt2, $result$$Register,
11380 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11381 } else {
11382 // Small strings are loaded through stack if they cross page boundary.
11383 __ string_indexof($str1$$Register, $str2$$Register,
11384 $cnt1$$Register, $cnt2$$Register,
11385 icnt2, $result$$Register,
11386 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11387 }
11388 %}
11389 ins_pipe( pipe_slow );
11390 %}
11391
11392 // fast search of substring with known size.
11393 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11394 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11395 %{
11396 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11397 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11398 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11399
11400 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11401 ins_encode %{
11402 int icnt2 = (int)$int_cnt2$$constant;
11403 if (icnt2 >= 8) {
11404 // IndexOf for constant substrings with size >= 8 elements
11405 // which don't need to be loaded through stack.
11406 __ string_indexofC8($str1$$Register, $str2$$Register,
11407 $cnt1$$Register, $cnt2$$Register,
11408 icnt2, $result$$Register,
11409 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11410 } else {
11411 // Small strings are loaded through stack if they cross page boundary.
11412 __ string_indexof($str1$$Register, $str2$$Register,
11413 $cnt1$$Register, $cnt2$$Register,
11414 icnt2, $result$$Register,
11415 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11416 }
11417 %}
11418 ins_pipe( pipe_slow );
11419 %}
11420
11421 // fast search of substring with known size.
11422 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11423 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11424 %{
11425 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11426 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11427 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11428
11429 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11430 ins_encode %{
11431 int icnt2 = (int)$int_cnt2$$constant;
11432 if (icnt2 >= 8) {
11433 // IndexOf for constant substrings with size >= 8 elements
11434 // which don't need to be loaded through stack.
11435 __ string_indexofC8($str1$$Register, $str2$$Register,
11436 $cnt1$$Register, $cnt2$$Register,
11437 icnt2, $result$$Register,
11438 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11439 } else {
11440 // Small strings are loaded through stack if they cross page boundary.
11441 __ string_indexof($str1$$Register, $str2$$Register,
11442 $cnt1$$Register, $cnt2$$Register,
11443 icnt2, $result$$Register,
11444 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11445 }
11446 %}
11447 ins_pipe( pipe_slow );
11448 %}
11449
11450 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11451 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11452 %{
11453 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11454 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11455 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11456
11457 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11458 ins_encode %{
11459 __ string_indexof($str1$$Register, $str2$$Register,
11460 $cnt1$$Register, $cnt2$$Register,
11461 (-1), $result$$Register,
11462 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11463 %}
11464 ins_pipe( pipe_slow );
11465 %}
11466
11467 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11468 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11469 %{
11470 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11471 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11472 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11473
11474 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11475 ins_encode %{
11476 __ string_indexof($str1$$Register, $str2$$Register,
11477 $cnt1$$Register, $cnt2$$Register,
11478 (-1), $result$$Register,
11479 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11480 %}
11481 ins_pipe( pipe_slow );
11482 %}
11483
11484 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11485 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11486 %{
11487 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11488 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11489 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11490
11491 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11492 ins_encode %{
11493 __ string_indexof($str1$$Register, $str2$$Register,
11494 $cnt1$$Register, $cnt2$$Register,
11495 (-1), $result$$Register,
11496 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11497 %}
11498 ins_pipe( pipe_slow );
11499 %}
11500
11501 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11502 rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11503 %{
11504 predicate(UseSSE42Intrinsics);
11505 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11506 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11507 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11508 ins_encode %{
11509 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11510 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11511 %}
11512 ins_pipe( pipe_slow );
11513 %}
11514
11515 // fast string equals
11516 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11517 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11518 %{
11519 match(Set result (StrEquals (Binary str1 str2) cnt));
11520 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11521
11522 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11523 ins_encode %{
11524 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11525 $cnt$$Register, $result$$Register, $tmp3$$Register,
11526 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11527 %}
11528 ins_pipe( pipe_slow );
11529 %}
11530
11531 // fast array equals
11532 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11533 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11534 %{
11535 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11536 match(Set result (AryEq ary1 ary2));
11537 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11538
11539 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11540 ins_encode %{
11541 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11542 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11543 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11544 %}
11545 ins_pipe( pipe_slow );
11546 %}
11547
11548 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11549 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11550 %{
11551 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11552 match(Set result (AryEq ary1 ary2));
11553 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11554
11555 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11556 ins_encode %{
11557 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11558 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11559 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11560 %}
11561 ins_pipe( pipe_slow );
11562 %}
11563
11564 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11565 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11566 %{
11567 match(Set result (HasNegatives ary1 len));
11568 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11569
11570 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11571 ins_encode %{
11572 __ has_negatives($ary1$$Register, $len$$Register,
11573 $result$$Register, $tmp3$$Register,
11574 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11575 %}
11576 ins_pipe( pipe_slow );
11577 %}
11578
11579 // fast char[] to byte[] compression
11580 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11581 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11582 match(Set result (StrCompressedCopy src (Binary dst len)));
11583 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11584
11585 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11586 ins_encode %{
11587 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11588 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11589 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11590 %}
11591 ins_pipe( pipe_slow );
11592 %}
11593
11594 // fast byte[] to char[] inflation
11595 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11596 legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11597 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11598 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11599
11600 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11601 ins_encode %{
11602 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11603 $tmp1$$XMMRegister, $tmp2$$Register);
11604 %}
11605 ins_pipe( pipe_slow );
11606 %}
11607
11608 // encode char[] to byte[] in ISO_8859_1
11609 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11610 legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11611 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11612 match(Set result (EncodeISOArray src (Binary dst len)));
11613 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11614
11615 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11616 ins_encode %{
11617 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11618 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11619 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11620 %}
11621 ins_pipe( pipe_slow );
11622 %}
11623
11624 //----------Overflow Math Instructions-----------------------------------------
11625
11626 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11627 %{
11628 match(Set cr (OverflowAddI op1 op2));
11629 effect(DEF cr, USE_KILL op1, USE op2);
11630
11631 format %{ "addl $op1, $op2\t# overflow check int" %}
11632
11633 ins_encode %{
11634 __ addl($op1$$Register, $op2$$Register);
11635 %}
11636 ins_pipe(ialu_reg_reg);
11637 %}
11638
11639 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11640 %{
11641 match(Set cr (OverflowAddI op1 op2));
11642 effect(DEF cr, USE_KILL op1, USE op2);
11643
11644 format %{ "addl $op1, $op2\t# overflow check int" %}
11645
11646 ins_encode %{
11647 __ addl($op1$$Register, $op2$$constant);
11648 %}
11649 ins_pipe(ialu_reg_reg);
11650 %}
11651
11652 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11653 %{
11654 match(Set cr (OverflowAddL op1 op2));
11655 effect(DEF cr, USE_KILL op1, USE op2);
11656
11657 format %{ "addq $op1, $op2\t# overflow check long" %}
11658 ins_encode %{
11659 __ addq($op1$$Register, $op2$$Register);
11660 %}
11661 ins_pipe(ialu_reg_reg);
11662 %}
11663
11664 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11665 %{
11666 match(Set cr (OverflowAddL op1 op2));
11667 effect(DEF cr, USE_KILL op1, USE op2);
11668
11669 format %{ "addq $op1, $op2\t# overflow check long" %}
11670 ins_encode %{
11671 __ addq($op1$$Register, $op2$$constant);
11672 %}
11673 ins_pipe(ialu_reg_reg);
11674 %}
11675
11676 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11677 %{
11678 match(Set cr (OverflowSubI op1 op2));
11679
11680 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11681 ins_encode %{
11682 __ cmpl($op1$$Register, $op2$$Register);
11683 %}
11684 ins_pipe(ialu_reg_reg);
11685 %}
11686
11687 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11688 %{
11689 match(Set cr (OverflowSubI op1 op2));
11690
11691 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11692 ins_encode %{
11693 __ cmpl($op1$$Register, $op2$$constant);
11694 %}
11695 ins_pipe(ialu_reg_reg);
11696 %}
11697
11698 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11699 %{
11700 match(Set cr (OverflowSubL op1 op2));
11701
11702 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11703 ins_encode %{
11704 __ cmpq($op1$$Register, $op2$$Register);
11705 %}
11706 ins_pipe(ialu_reg_reg);
11707 %}
11708
11709 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11710 %{
11711 match(Set cr (OverflowSubL op1 op2));
11712
11713 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11714 ins_encode %{
11715 __ cmpq($op1$$Register, $op2$$constant);
11716 %}
11717 ins_pipe(ialu_reg_reg);
11718 %}
11719
11720 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11721 %{
11722 match(Set cr (OverflowSubI zero op2));
11723 effect(DEF cr, USE_KILL op2);
11724
11725 format %{ "negl $op2\t# overflow check int" %}
11726 ins_encode %{
11727 __ negl($op2$$Register);
11728 %}
11729 ins_pipe(ialu_reg_reg);
11730 %}
11731
11732 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11733 %{
11734 match(Set cr (OverflowSubL zero op2));
11735 effect(DEF cr, USE_KILL op2);
11736
11737 format %{ "negq $op2\t# overflow check long" %}
11738 ins_encode %{
11739 __ negq($op2$$Register);
11740 %}
11741 ins_pipe(ialu_reg_reg);
11742 %}
11743
11744 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11745 %{
11746 match(Set cr (OverflowMulI op1 op2));
11747 effect(DEF cr, USE_KILL op1, USE op2);
11748
11749 format %{ "imull $op1, $op2\t# overflow check int" %}
11750 ins_encode %{
11751 __ imull($op1$$Register, $op2$$Register);
11752 %}
11753 ins_pipe(ialu_reg_reg_alu0);
11754 %}
11755
11756 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11757 %{
11758 match(Set cr (OverflowMulI op1 op2));
11759 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11760
11761 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11762 ins_encode %{
11763 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11764 %}
11765 ins_pipe(ialu_reg_reg_alu0);
11766 %}
11767
11768 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11769 %{
11770 match(Set cr (OverflowMulL op1 op2));
11771 effect(DEF cr, USE_KILL op1, USE op2);
11772
11773 format %{ "imulq $op1, $op2\t# overflow check long" %}
11774 ins_encode %{
11775 __ imulq($op1$$Register, $op2$$Register);
11776 %}
11777 ins_pipe(ialu_reg_reg_alu0);
11778 %}
11779
11780 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11781 %{
11782 match(Set cr (OverflowMulL op1 op2));
11783 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11784
11785 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11786 ins_encode %{
11787 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11788 %}
11789 ins_pipe(ialu_reg_reg_alu0);
11790 %}
11791
11792
11793 //----------Control Flow Instructions------------------------------------------
11794 // Signed compare Instructions
11795
11796 // XXX more variants!!
11797 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11798 %{
11799 match(Set cr (CmpI op1 op2));
11800 effect(DEF cr, USE op1, USE op2);
11801
11802 format %{ "cmpl $op1, $op2" %}
11803 opcode(0x3B); /* Opcode 3B /r */
11804 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11805 ins_pipe(ialu_cr_reg_reg);
11806 %}
11807
11808 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11809 %{
11810 match(Set cr (CmpI op1 op2));
11811
11812 format %{ "cmpl $op1, $op2" %}
11813 opcode(0x81, 0x07); /* Opcode 81 /7 */
11814 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11815 ins_pipe(ialu_cr_reg_imm);
11816 %}
11817
11818 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11819 %{
11820 match(Set cr (CmpI op1 (LoadI op2)));
11821
11822 ins_cost(500); // XXX
11823 format %{ "cmpl $op1, $op2" %}
11824 opcode(0x3B); /* Opcode 3B /r */
11825 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11826 ins_pipe(ialu_cr_reg_mem);
11827 %}
11828
11829 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11830 %{
11831 match(Set cr (CmpI src zero));
11832
11833 format %{ "testl $src, $src" %}
11834 opcode(0x85);
11835 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11836 ins_pipe(ialu_cr_reg_imm);
11837 %}
11838
11839 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11840 %{
11841 match(Set cr (CmpI (AndI src con) zero));
11842
11843 format %{ "testl $src, $con" %}
11844 opcode(0xF7, 0x00);
11845 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11846 ins_pipe(ialu_cr_reg_imm);
11847 %}
11848
11849 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11850 %{
11851 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11852
11853 format %{ "testl $src, $mem" %}
11854 opcode(0x85);
11855 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11856 ins_pipe(ialu_cr_reg_mem);
11857 %}
11858
11859 // Unsigned compare Instructions; really, same as signed except they
11860 // produce an rFlagsRegU instead of rFlagsReg.
11861 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11862 %{
11863 match(Set cr (CmpU op1 op2));
11864
11865 format %{ "cmpl $op1, $op2\t# unsigned" %}
11866 opcode(0x3B); /* Opcode 3B /r */
11867 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11868 ins_pipe(ialu_cr_reg_reg);
11869 %}
11870
11871 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11872 %{
11873 match(Set cr (CmpU op1 op2));
11874
11875 format %{ "cmpl $op1, $op2\t# unsigned" %}
11876 opcode(0x81,0x07); /* Opcode 81 /7 */
11877 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11878 ins_pipe(ialu_cr_reg_imm);
11879 %}
11880
11881 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11882 %{
11883 match(Set cr (CmpU op1 (LoadI op2)));
11884
11885 ins_cost(500); // XXX
11886 format %{ "cmpl $op1, $op2\t# unsigned" %}
11887 opcode(0x3B); /* Opcode 3B /r */
11888 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11889 ins_pipe(ialu_cr_reg_mem);
11890 %}
11891
11892 // // // Cisc-spilled version of cmpU_rReg
11893 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11894 // //%{
11895 // // match(Set cr (CmpU (LoadI op1) op2));
11896 // //
11897 // // format %{ "CMPu $op1,$op2" %}
11898 // // ins_cost(500);
11899 // // opcode(0x39); /* Opcode 39 /r */
11900 // // ins_encode( OpcP, reg_mem( op1, op2) );
11901 // //%}
11902
11903 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11904 %{
11905 match(Set cr (CmpU src zero));
11906
11907 format %{ "testl $src, $src\t# unsigned" %}
11908 opcode(0x85);
11909 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11910 ins_pipe(ialu_cr_reg_imm);
11911 %}
11912
11913 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11914 %{
11915 match(Set cr (CmpP op1 op2));
11916
11917 format %{ "cmpq $op1, $op2\t# ptr" %}
11918 opcode(0x3B); /* Opcode 3B /r */
11919 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11920 ins_pipe(ialu_cr_reg_reg);
11921 %}
11922
11923 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11924 %{
11925 match(Set cr (CmpP op1 (LoadP op2)));
11926
11927 ins_cost(500); // XXX
11928 format %{ "cmpq $op1, $op2\t# ptr" %}
11929 opcode(0x3B); /* Opcode 3B /r */
11930 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11931 ins_pipe(ialu_cr_reg_mem);
11932 %}
11933
11934 // // // Cisc-spilled version of cmpP_rReg
11935 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11936 // //%{
11937 // // match(Set cr (CmpP (LoadP op1) op2));
11938 // //
11939 // // format %{ "CMPu $op1,$op2" %}
11940 // // ins_cost(500);
11941 // // opcode(0x39); /* Opcode 39 /r */
11942 // // ins_encode( OpcP, reg_mem( op1, op2) );
11943 // //%}
11944
11945 // XXX this is generalized by compP_rReg_mem???
11946 // Compare raw pointer (used in out-of-heap check).
11947 // Only works because non-oop pointers must be raw pointers
11948 // and raw pointers have no anti-dependencies.
11949 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11950 %{
11951 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11952 match(Set cr (CmpP op1 (LoadP op2)));
11953
11954 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11955 opcode(0x3B); /* Opcode 3B /r */
11956 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11957 ins_pipe(ialu_cr_reg_mem);
11958 %}
11959
11960 // This will generate a signed flags result. This should be OK since
11961 // any compare to a zero should be eq/neq.
11962 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11963 %{
11964 match(Set cr (CmpP src zero));
11965
11966 format %{ "testq $src, $src\t# ptr" %}
11967 opcode(0x85);
11968 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11969 ins_pipe(ialu_cr_reg_imm);
11970 %}
11971
11972 // This will generate a signed flags result. This should be OK since
11973 // any compare to a zero should be eq/neq.
11974 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11975 %{
11976 predicate(!UseCompressedOops || (CompressedOops::base() != NULL));
11977 match(Set cr (CmpP (LoadP op) zero));
11978
11979 ins_cost(500); // XXX
11980 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11981 opcode(0xF7); /* Opcode F7 /0 */
11982 ins_encode(REX_mem_wide(op),
11983 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11984 ins_pipe(ialu_cr_reg_imm);
11985 %}
11986
11987 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11988 %{
11989 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
11990 match(Set cr (CmpP (LoadP mem) zero));
11991
11992 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11993 ins_encode %{
11994 __ cmpq(r12, $mem$$Address);
11995 %}
11996 ins_pipe(ialu_cr_reg_mem);
11997 %}
11998
11999 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
12000 %{
12001 match(Set cr (CmpN op1 op2));
12002
12003 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
12004 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
12005 ins_pipe(ialu_cr_reg_reg);
12006 %}
12007
12008 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
12009 %{
12010 match(Set cr (CmpN src (LoadN mem)));
12011
12012 format %{ "cmpl $src, $mem\t# compressed ptr" %}
12013 ins_encode %{
12014 __ cmpl($src$$Register, $mem$$Address);
12015 %}
12016 ins_pipe(ialu_cr_reg_mem);
12017 %}
12018
12019 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
12020 match(Set cr (CmpN op1 op2));
12021
12022 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
12023 ins_encode %{
12024 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
12025 %}
12026 ins_pipe(ialu_cr_reg_imm);
12027 %}
12028
12029 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
12030 %{
12031 match(Set cr (CmpN src (LoadN mem)));
12032
12033 format %{ "cmpl $mem, $src\t# compressed ptr" %}
12034 ins_encode %{
12035 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
12036 %}
12037 ins_pipe(ialu_cr_reg_mem);
12038 %}
12039
12040 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
12041 match(Set cr (CmpN op1 op2));
12042
12043 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
12044 ins_encode %{
12045 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
12046 %}
12047 ins_pipe(ialu_cr_reg_imm);
12048 %}
12049
12050 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
12051 %{
12052 match(Set cr (CmpN src (LoadNKlass mem)));
12053
12054 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
12055 ins_encode %{
12056 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
12057 %}
12058 ins_pipe(ialu_cr_reg_mem);
12059 %}
12060
12061 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
12062 match(Set cr (CmpN src zero));
12063
12064 format %{ "testl $src, $src\t# compressed ptr" %}
12065 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
12066 ins_pipe(ialu_cr_reg_imm);
12067 %}
12068
12069 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
12070 %{
12071 predicate(CompressedOops::base() != NULL);
12072 match(Set cr (CmpN (LoadN mem) zero));
12073
12074 ins_cost(500); // XXX
12075 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
12076 ins_encode %{
12077 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
12078 %}
12079 ins_pipe(ialu_cr_reg_mem);
12080 %}
12081
12082 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
12083 %{
12084 predicate(CompressedOops::base() == NULL && (CompressedKlassPointers::base() == NULL));
12085 match(Set cr (CmpN (LoadN mem) zero));
12086
12087 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
12088 ins_encode %{
12089 __ cmpl(r12, $mem$$Address);
12090 %}
12091 ins_pipe(ialu_cr_reg_mem);
12092 %}
12093
12094 // Yanked all unsigned pointer compare operations.
12095 // Pointer compares are done with CmpP which is already unsigned.
12096
12097 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12098 %{
12099 match(Set cr (CmpL op1 op2));
12100
12101 format %{ "cmpq $op1, $op2" %}
12102 opcode(0x3B); /* Opcode 3B /r */
12103 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12104 ins_pipe(ialu_cr_reg_reg);
12105 %}
12106
12107 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12108 %{
12109 match(Set cr (CmpL op1 op2));
12110
12111 format %{ "cmpq $op1, $op2" %}
12112 opcode(0x81, 0x07); /* Opcode 81 /7 */
12113 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12114 ins_pipe(ialu_cr_reg_imm);
12115 %}
12116
12117 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
12118 %{
12119 match(Set cr (CmpL op1 (LoadL op2)));
12120
12121 format %{ "cmpq $op1, $op2" %}
12122 opcode(0x3B); /* Opcode 3B /r */
12123 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12124 ins_pipe(ialu_cr_reg_mem);
12125 %}
12126
12127 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
12128 %{
12129 match(Set cr (CmpL src zero));
12130
12131 format %{ "testq $src, $src" %}
12132 opcode(0x85);
12133 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12134 ins_pipe(ialu_cr_reg_imm);
12135 %}
12136
12137 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12138 %{
12139 match(Set cr (CmpL (AndL src con) zero));
12140
12141 format %{ "testq $src, $con\t# long" %}
12142 opcode(0xF7, 0x00);
12143 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
12144 ins_pipe(ialu_cr_reg_imm);
12145 %}
12146
12147 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12148 %{
12149 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12150
12151 format %{ "testq $src, $mem" %}
12152 opcode(0x85);
12153 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12154 ins_pipe(ialu_cr_reg_mem);
12155 %}
12156
12157 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12158 %{
12159 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12160
12161 format %{ "testq $src, $mem" %}
12162 opcode(0x85);
12163 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12164 ins_pipe(ialu_cr_reg_mem);
12165 %}
12166
12167 // Manifest a CmpL result in an integer register. Very painful.
12168 // This is the test to avoid.
12169 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12170 %{
12171 match(Set dst (CmpL3 src1 src2));
12172 effect(KILL flags);
12173
12174 ins_cost(275); // XXX
12175 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12176 "movl $dst, -1\n\t"
12177 "jl,s done\n\t"
12178 "setne $dst\n\t"
12179 "movzbl $dst, $dst\n\t"
12180 "done:" %}
12181 ins_encode(cmpl3_flag(src1, src2, dst));
12182 ins_pipe(pipe_slow);
12183 %}
12184
12185 // Unsigned long compare Instructions; really, same as signed long except they
12186 // produce an rFlagsRegU instead of rFlagsReg.
12187 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12188 %{
12189 match(Set cr (CmpUL op1 op2));
12190
12191 format %{ "cmpq $op1, $op2\t# unsigned" %}
12192 opcode(0x3B); /* Opcode 3B /r */
12193 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12194 ins_pipe(ialu_cr_reg_reg);
12195 %}
12196
12197 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12198 %{
12199 match(Set cr (CmpUL op1 op2));
12200
12201 format %{ "cmpq $op1, $op2\t# unsigned" %}
12202 opcode(0x81, 0x07); /* Opcode 81 /7 */
12203 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12204 ins_pipe(ialu_cr_reg_imm);
12205 %}
12206
12207 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12208 %{
12209 match(Set cr (CmpUL op1 (LoadL op2)));
12210
12211 format %{ "cmpq $op1, $op2\t# unsigned" %}
12212 opcode(0x3B); /* Opcode 3B /r */
12213 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12214 ins_pipe(ialu_cr_reg_mem);
12215 %}
12216
12217 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12218 %{
12219 match(Set cr (CmpUL src zero));
12220
12221 format %{ "testq $src, $src\t# unsigned" %}
12222 opcode(0x85);
12223 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12224 ins_pipe(ialu_cr_reg_imm);
12225 %}
12226
12227 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12228 %{
12229 match(Set cr (CmpI (LoadB mem) imm));
12230
12231 ins_cost(125);
12232 format %{ "cmpb $mem, $imm" %}
12233 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12234 ins_pipe(ialu_cr_reg_mem);
12235 %}
12236
12237 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
12238 %{
12239 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12240
12241 ins_cost(125);
12242 format %{ "testb $mem, $imm\t# ubyte" %}
12243 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12244 ins_pipe(ialu_cr_reg_mem);
12245 %}
12246
12247 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
12248 %{
12249 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12250
12251 ins_cost(125);
12252 format %{ "testb $mem, $imm\t# byte" %}
12253 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12254 ins_pipe(ialu_cr_reg_mem);
12255 %}
12256
12257 //----------Max and Min--------------------------------------------------------
12258 // Min Instructions
12259
12260 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12261 %{
12262 effect(USE_DEF dst, USE src, USE cr);
12263
12264 format %{ "cmovlgt $dst, $src\t# min" %}
12265 opcode(0x0F, 0x4F);
12266 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12267 ins_pipe(pipe_cmov_reg);
12268 %}
12269
12270
12271 instruct minI_rReg(rRegI dst, rRegI src)
12272 %{
12273 match(Set dst (MinI dst src));
12274
12275 ins_cost(200);
12276 expand %{
12277 rFlagsReg cr;
12278 compI_rReg(cr, dst, src);
12279 cmovI_reg_g(dst, src, cr);
12280 %}
12281 %}
12282
12283 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12284 %{
12285 effect(USE_DEF dst, USE src, USE cr);
12286
12287 format %{ "cmovllt $dst, $src\t# max" %}
12288 opcode(0x0F, 0x4C);
12289 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12290 ins_pipe(pipe_cmov_reg);
12291 %}
12292
12293
12294 instruct maxI_rReg(rRegI dst, rRegI src)
12295 %{
12296 match(Set dst (MaxI dst src));
12297
12298 ins_cost(200);
12299 expand %{
12300 rFlagsReg cr;
12301 compI_rReg(cr, dst, src);
12302 cmovI_reg_l(dst, src, cr);
12303 %}
12304 %}
12305
12306 // ============================================================================
12307 // Branch Instructions
12308
12309 // Jump Direct - Label defines a relative address from JMP+1
12310 instruct jmpDir(label labl)
12311 %{
12312 match(Goto);
12313 effect(USE labl);
12314
12315 ins_cost(300);
12316 format %{ "jmp $labl" %}
12317 size(5);
12318 ins_encode %{
12319 Label* L = $labl$$label;
12320 __ jmp(*L, false); // Always long jump
12321 %}
12322 ins_pipe(pipe_jmp);
12323 %}
12324
12325 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12326 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12327 %{
12328 match(If cop cr);
12329 effect(USE labl);
12330
12331 ins_cost(300);
12332 format %{ "j$cop $labl" %}
12333 size(6);
12334 ins_encode %{
12335 Label* L = $labl$$label;
12336 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12337 %}
12338 ins_pipe(pipe_jcc);
12339 %}
12340
12341 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12342 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12343 %{
12344 predicate(!n->has_vector_mask_set());
12345 match(CountedLoopEnd cop cr);
12346 effect(USE labl);
12347
12348 ins_cost(300);
12349 format %{ "j$cop $labl\t# loop end" %}
12350 size(6);
12351 ins_encode %{
12352 Label* L = $labl$$label;
12353 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12354 %}
12355 ins_pipe(pipe_jcc);
12356 %}
12357
12358 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12359 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12360 predicate(!n->has_vector_mask_set());
12361 match(CountedLoopEnd cop cmp);
12362 effect(USE labl);
12363
12364 ins_cost(300);
12365 format %{ "j$cop,u $labl\t# loop end" %}
12366 size(6);
12367 ins_encode %{
12368 Label* L = $labl$$label;
12369 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12370 %}
12371 ins_pipe(pipe_jcc);
12372 %}
12373
12374 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12375 predicate(!n->has_vector_mask_set());
12376 match(CountedLoopEnd cop cmp);
12377 effect(USE labl);
12378
12379 ins_cost(200);
12380 format %{ "j$cop,u $labl\t# loop end" %}
12381 size(6);
12382 ins_encode %{
12383 Label* L = $labl$$label;
12384 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12385 %}
12386 ins_pipe(pipe_jcc);
12387 %}
12388
12389 // mask version
12390 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12391 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12392 %{
12393 predicate(n->has_vector_mask_set());
12394 match(CountedLoopEnd cop cr);
12395 effect(USE labl);
12396
12397 ins_cost(400);
12398 format %{ "j$cop $labl\t# loop end\n\t"
12399 "restorevectmask \t# vector mask restore for loops" %}
12400 size(10);
12401 ins_encode %{
12402 Label* L = $labl$$label;
12403 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12404 __ restorevectmask();
12405 %}
12406 ins_pipe(pipe_jcc);
12407 %}
12408
12409 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12410 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12411 predicate(n->has_vector_mask_set());
12412 match(CountedLoopEnd cop cmp);
12413 effect(USE labl);
12414
12415 ins_cost(400);
12416 format %{ "j$cop,u $labl\t# loop end\n\t"
12417 "restorevectmask \t# vector mask restore for loops" %}
12418 size(10);
12419 ins_encode %{
12420 Label* L = $labl$$label;
12421 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12422 __ restorevectmask();
12423 %}
12424 ins_pipe(pipe_jcc);
12425 %}
12426
12427 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12428 predicate(n->has_vector_mask_set());
12429 match(CountedLoopEnd cop cmp);
12430 effect(USE labl);
12431
12432 ins_cost(300);
12433 format %{ "j$cop,u $labl\t# loop end\n\t"
12434 "restorevectmask \t# vector mask restore for loops" %}
12435 size(10);
12436 ins_encode %{
12437 Label* L = $labl$$label;
12438 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12439 __ restorevectmask();
12440 %}
12441 ins_pipe(pipe_jcc);
12442 %}
12443
12444 // Jump Direct Conditional - using unsigned comparison
12445 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12446 match(If cop cmp);
12447 effect(USE labl);
12448
12449 ins_cost(300);
12450 format %{ "j$cop,u $labl" %}
12451 size(6);
12452 ins_encode %{
12453 Label* L = $labl$$label;
12454 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12455 %}
12456 ins_pipe(pipe_jcc);
12457 %}
12458
12459 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12460 match(If cop cmp);
12461 effect(USE labl);
12462
12463 ins_cost(200);
12464 format %{ "j$cop,u $labl" %}
12465 size(6);
12466 ins_encode %{
12467 Label* L = $labl$$label;
12468 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12469 %}
12470 ins_pipe(pipe_jcc);
12471 %}
12472
12473 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12474 match(If cop cmp);
12475 effect(USE labl);
12476
12477 ins_cost(200);
12478 format %{ $$template
12479 if ($cop$$cmpcode == Assembler::notEqual) {
12480 $$emit$$"jp,u $labl\n\t"
12481 $$emit$$"j$cop,u $labl"
12482 } else {
12483 $$emit$$"jp,u done\n\t"
12484 $$emit$$"j$cop,u $labl\n\t"
12485 $$emit$$"done:"
12486 }
12487 %}
12488 ins_encode %{
12489 Label* l = $labl$$label;
12490 if ($cop$$cmpcode == Assembler::notEqual) {
12491 __ jcc(Assembler::parity, *l, false);
12492 __ jcc(Assembler::notEqual, *l, false);
12493 } else if ($cop$$cmpcode == Assembler::equal) {
12494 Label done;
12495 __ jccb(Assembler::parity, done);
12496 __ jcc(Assembler::equal, *l, false);
12497 __ bind(done);
12498 } else {
12499 ShouldNotReachHere();
12500 }
12501 %}
12502 ins_pipe(pipe_jcc);
12503 %}
12504
12505 // ============================================================================
12506 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12507 // superklass array for an instance of the superklass. Set a hidden
12508 // internal cache on a hit (cache is checked with exposed code in
12509 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12510 // encoding ALSO sets flags.
12511
12512 instruct partialSubtypeCheck(rdi_RegP result,
12513 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12514 rFlagsReg cr)
12515 %{
12516 match(Set result (PartialSubtypeCheck sub super));
12517 effect(KILL rcx, KILL cr);
12518
12519 ins_cost(1100); // slightly larger than the next version
12520 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12521 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12522 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12523 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12524 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12525 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12526 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12527 "miss:\t" %}
12528
12529 opcode(0x1); // Force a XOR of RDI
12530 ins_encode(enc_PartialSubtypeCheck());
12531 ins_pipe(pipe_slow);
12532 %}
12533
12534 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12535 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12536 immP0 zero,
12537 rdi_RegP result)
12538 %{
12539 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12540 effect(KILL rcx, KILL result);
12541
12542 ins_cost(1000);
12543 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12544 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12545 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12546 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12547 "jne,s miss\t\t# Missed: flags nz\n\t"
12548 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12549 "miss:\t" %}
12550
12551 opcode(0x0); // No need to XOR RDI
12552 ins_encode(enc_PartialSubtypeCheck());
12553 ins_pipe(pipe_slow);
12554 %}
12555
12556 // ============================================================================
12557 // Branch Instructions -- short offset versions
12558 //
12559 // These instructions are used to replace jumps of a long offset (the default
12560 // match) with jumps of a shorter offset. These instructions are all tagged
12561 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12562 // match rules in general matching. Instead, the ADLC generates a conversion
12563 // method in the MachNode which can be used to do in-place replacement of the
12564 // long variant with the shorter variant. The compiler will determine if a
12565 // branch can be taken by the is_short_branch_offset() predicate in the machine
12566 // specific code section of the file.
12567
12568 // Jump Direct - Label defines a relative address from JMP+1
12569 instruct jmpDir_short(label labl) %{
12570 match(Goto);
12571 effect(USE labl);
12572
12573 ins_cost(300);
12574 format %{ "jmp,s $labl" %}
12575 size(2);
12576 ins_encode %{
12577 Label* L = $labl$$label;
12578 __ jmpb(*L);
12579 %}
12580 ins_pipe(pipe_jmp);
12581 ins_short_branch(1);
12582 %}
12583
12584 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12585 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12586 match(If cop cr);
12587 effect(USE labl);
12588
12589 ins_cost(300);
12590 format %{ "j$cop,s $labl" %}
12591 size(2);
12592 ins_encode %{
12593 Label* L = $labl$$label;
12594 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12595 %}
12596 ins_pipe(pipe_jcc);
12597 ins_short_branch(1);
12598 %}
12599
12600 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12601 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12602 match(CountedLoopEnd cop cr);
12603 effect(USE labl);
12604
12605 ins_cost(300);
12606 format %{ "j$cop,s $labl\t# loop end" %}
12607 size(2);
12608 ins_encode %{
12609 Label* L = $labl$$label;
12610 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12611 %}
12612 ins_pipe(pipe_jcc);
12613 ins_short_branch(1);
12614 %}
12615
12616 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12617 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12618 match(CountedLoopEnd cop cmp);
12619 effect(USE labl);
12620
12621 ins_cost(300);
12622 format %{ "j$cop,us $labl\t# loop end" %}
12623 size(2);
12624 ins_encode %{
12625 Label* L = $labl$$label;
12626 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12627 %}
12628 ins_pipe(pipe_jcc);
12629 ins_short_branch(1);
12630 %}
12631
12632 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12633 match(CountedLoopEnd cop cmp);
12634 effect(USE labl);
12635
12636 ins_cost(300);
12637 format %{ "j$cop,us $labl\t# loop end" %}
12638 size(2);
12639 ins_encode %{
12640 Label* L = $labl$$label;
12641 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12642 %}
12643 ins_pipe(pipe_jcc);
12644 ins_short_branch(1);
12645 %}
12646
12647 // Jump Direct Conditional - using unsigned comparison
12648 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12649 match(If cop cmp);
12650 effect(USE labl);
12651
12652 ins_cost(300);
12653 format %{ "j$cop,us $labl" %}
12654 size(2);
12655 ins_encode %{
12656 Label* L = $labl$$label;
12657 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12658 %}
12659 ins_pipe(pipe_jcc);
12660 ins_short_branch(1);
12661 %}
12662
12663 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12664 match(If cop cmp);
12665 effect(USE labl);
12666
12667 ins_cost(300);
12668 format %{ "j$cop,us $labl" %}
12669 size(2);
12670 ins_encode %{
12671 Label* L = $labl$$label;
12672 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12673 %}
12674 ins_pipe(pipe_jcc);
12675 ins_short_branch(1);
12676 %}
12677
12678 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12679 match(If cop cmp);
12680 effect(USE labl);
12681
12682 ins_cost(300);
12683 format %{ $$template
12684 if ($cop$$cmpcode == Assembler::notEqual) {
12685 $$emit$$"jp,u,s $labl\n\t"
12686 $$emit$$"j$cop,u,s $labl"
12687 } else {
12688 $$emit$$"jp,u,s done\n\t"
12689 $$emit$$"j$cop,u,s $labl\n\t"
12690 $$emit$$"done:"
12691 }
12692 %}
12693 size(4);
12694 ins_encode %{
12695 Label* l = $labl$$label;
12696 if ($cop$$cmpcode == Assembler::notEqual) {
12697 __ jccb(Assembler::parity, *l);
12698 __ jccb(Assembler::notEqual, *l);
12699 } else if ($cop$$cmpcode == Assembler::equal) {
12700 Label done;
12701 __ jccb(Assembler::parity, done);
12702 __ jccb(Assembler::equal, *l);
12703 __ bind(done);
12704 } else {
12705 ShouldNotReachHere();
12706 }
12707 %}
12708 ins_pipe(pipe_jcc);
12709 ins_short_branch(1);
12710 %}
12711
12712 // ============================================================================
12713 // inlined locking and unlocking
12714
12715 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12716 predicate(Compile::current()->use_rtm());
12717 match(Set cr (FastLock object box));
12718 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12719 ins_cost(300);
12720 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12721 ins_encode %{
12722 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12723 $scr$$Register, $cx1$$Register, $cx2$$Register,
12724 _counters, _rtm_counters, _stack_rtm_counters,
12725 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12726 true, ra_->C->profile_rtm());
12727 %}
12728 ins_pipe(pipe_slow);
12729 %}
12730
12731 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12732 predicate(!Compile::current()->use_rtm());
12733 match(Set cr (FastLock object box));
12734 effect(TEMP tmp, TEMP scr, USE_KILL box);
12735 ins_cost(300);
12736 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12737 ins_encode %{
12738 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12739 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12740 %}
12741 ins_pipe(pipe_slow);
12742 %}
12743
12744 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12745 match(Set cr (FastUnlock object box));
12746 effect(TEMP tmp, USE_KILL box);
12747 ins_cost(300);
12748 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12749 ins_encode %{
12750 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12751 %}
12752 ins_pipe(pipe_slow);
12753 %}
12754
12755
12756 // ============================================================================
12757 // Safepoint Instructions
12758 instruct safePoint_poll(rFlagsReg cr)
12759 %{
12760 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12761 match(SafePoint);
12762 effect(KILL cr);
12763
12764 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12765 "# Safepoint: poll for GC" %}
12766 ins_cost(125);
12767 ins_encode %{
12768 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12769 __ testl(rax, addr);
12770 %}
12771 ins_pipe(ialu_reg_mem);
12772 %}
12773
12774 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12775 %{
12776 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12777 match(SafePoint poll);
12778 effect(KILL cr, USE poll);
12779
12780 format %{ "testl rax, [$poll]\t"
12781 "# Safepoint: poll for GC" %}
12782 ins_cost(125);
12783 ins_encode %{
12784 __ relocate(relocInfo::poll_type);
12785 __ testl(rax, Address($poll$$Register, 0));
12786 %}
12787 ins_pipe(ialu_reg_mem);
12788 %}
12789
12790 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12791 %{
12792 predicate(SafepointMechanism::uses_thread_local_poll());
12793 match(SafePoint poll);
12794 effect(KILL cr, USE poll);
12795
12796 format %{ "testl rax, [$poll]\t"
12797 "# Safepoint: poll for GC" %}
12798 ins_cost(125);
12799 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12800 ins_encode %{
12801 __ relocate(relocInfo::poll_type);
12802 address pre_pc = __ pc();
12803 __ testl(rax, Address($poll$$Register, 0));
12804 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12805 %}
12806 ins_pipe(ialu_reg_mem);
12807 %}
12808
12809 // ============================================================================
12810 // Procedure Call/Return Instructions
12811 // Call Java Static Instruction
12812 // Note: If this code changes, the corresponding ret_addr_offset() and
12813 // compute_padding() functions will have to be adjusted.
12814 instruct CallStaticJavaDirect(method meth) %{
12815 match(CallStaticJava);
12816 effect(USE meth);
12817
12818 ins_cost(300);
12819 format %{ "call,static " %}
12820 opcode(0xE8); /* E8 cd */
12821 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12822 ins_pipe(pipe_slow);
12823 ins_alignment(4);
12824 %}
12825
12826 // Call Java Dynamic Instruction
12827 // Note: If this code changes, the corresponding ret_addr_offset() and
12828 // compute_padding() functions will have to be adjusted.
12829 instruct CallDynamicJavaDirect(method meth)
12830 %{
12831 match(CallDynamicJava);
12832 effect(USE meth);
12833
12834 ins_cost(300);
12835 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12836 "call,dynamic " %}
12837 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12838 ins_pipe(pipe_slow);
12839 ins_alignment(4);
12840 %}
12841
12842 // Call Runtime Instruction
12843 instruct CallRuntimeDirect(method meth)
12844 %{
12845 match(CallRuntime);
12846 effect(USE meth);
12847
12848 ins_cost(300);
12849 format %{ "call,runtime " %}
12850 ins_encode(clear_avx, Java_To_Runtime(meth));
12851 ins_pipe(pipe_slow);
12852 %}
12853
12854 // Call runtime without safepoint
12855 instruct CallLeafDirect(method meth)
12856 %{
12857 match(CallLeaf);
12858 effect(USE meth);
12859
12860 ins_cost(300);
12861 format %{ "call_leaf,runtime " %}
12862 ins_encode(clear_avx, Java_To_Runtime(meth));
12863 ins_pipe(pipe_slow);
12864 %}
12865
12866 // Call runtime without safepoint
12867 instruct CallLeafNoFPDirect(method meth)
12868 %{
12869 match(CallLeafNoFP);
12870 effect(USE meth);
12871
12872 ins_cost(300);
12873 format %{ "call_leaf_nofp,runtime " %}
12874 ins_encode(clear_avx, Java_To_Runtime(meth));
12875 ins_pipe(pipe_slow);
12876 %}
12877
12878 // Return Instruction
12879 // Remove the return address & jump to it.
12880 // Notice: We always emit a nop after a ret to make sure there is room
12881 // for safepoint patching
12882 instruct Ret()
12883 %{
12884 match(Return);
12885
12886 format %{ "ret" %}
12887 opcode(0xC3);
12888 ins_encode(OpcP);
12889 ins_pipe(pipe_jmp);
12890 %}
12891
12892 // Tail Call; Jump from runtime stub to Java code.
12893 // Also known as an 'interprocedural jump'.
12894 // Target of jump will eventually return to caller.
12895 // TailJump below removes the return address.
12896 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12897 %{
12898 match(TailCall jump_target method_oop);
12899
12900 ins_cost(300);
12901 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12902 opcode(0xFF, 0x4); /* Opcode FF /4 */
12903 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12904 ins_pipe(pipe_jmp);
12905 %}
12906
12907 // Tail Jump; remove the return address; jump to target.
12908 // TailCall above leaves the return address around.
12909 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12910 %{
12911 match(TailJump jump_target ex_oop);
12912
12913 ins_cost(300);
12914 format %{ "popq rdx\t# pop return address\n\t"
12915 "jmp $jump_target" %}
12916 opcode(0xFF, 0x4); /* Opcode FF /4 */
12917 ins_encode(Opcode(0x5a), // popq rdx
12918 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12919 ins_pipe(pipe_jmp);
12920 %}
12921
12922 // Create exception oop: created by stack-crawling runtime code.
12923 // Created exception is now available to this handler, and is setup
12924 // just prior to jumping to this handler. No code emitted.
12925 instruct CreateException(rax_RegP ex_oop)
12926 %{
12927 match(Set ex_oop (CreateEx));
12928
12929 size(0);
12930 // use the following format syntax
12931 format %{ "# exception oop is in rax; no code emitted" %}
12932 ins_encode();
12933 ins_pipe(empty);
12934 %}
12935
12936 // Rethrow exception:
12937 // The exception oop will come in the first argument position.
12938 // Then JUMP (not call) to the rethrow stub code.
12939 instruct RethrowException()
12940 %{
12941 match(Rethrow);
12942
12943 // use the following format syntax
12944 format %{ "jmp rethrow_stub" %}
12945 ins_encode(enc_rethrow);
12946 ins_pipe(pipe_jmp);
12947 %}
12948
12949 // ============================================================================
12950 // This name is KNOWN by the ADLC and cannot be changed.
12951 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12952 // for this guy.
12953 instruct tlsLoadP(r15_RegP dst) %{
12954 match(Set dst (ThreadLocal));
12955 effect(DEF dst);
12956
12957 size(0);
12958 format %{ "# TLS is in R15" %}
12959 ins_encode( /*empty encoding*/ );
12960 ins_pipe(ialu_reg_reg);
12961 %}
12962
12963
12964 //----------PEEPHOLE RULES-----------------------------------------------------
12965 // These must follow all instruction definitions as they use the names
12966 // defined in the instructions definitions.
12967 //
12968 // peepmatch ( root_instr_name [preceding_instruction]* );
12969 //
12970 // peepconstraint %{
12971 // (instruction_number.operand_name relational_op instruction_number.operand_name
12972 // [, ...] );
12973 // // instruction numbers are zero-based using left to right order in peepmatch
12974 //
12975 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12976 // // provide an instruction_number.operand_name for each operand that appears
12977 // // in the replacement instruction's match rule
12978 //
12979 // ---------VM FLAGS---------------------------------------------------------
12980 //
12981 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12982 //
12983 // Each peephole rule is given an identifying number starting with zero and
12984 // increasing by one in the order seen by the parser. An individual peephole
12985 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12986 // on the command-line.
12987 //
12988 // ---------CURRENT LIMITATIONS----------------------------------------------
12989 //
12990 // Only match adjacent instructions in same basic block
12991 // Only equality constraints
12992 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12993 // Only one replacement instruction
12994 //
12995 // ---------EXAMPLE----------------------------------------------------------
12996 //
12997 // // pertinent parts of existing instructions in architecture description
12998 // instruct movI(rRegI dst, rRegI src)
12999 // %{
13000 // match(Set dst (CopyI src));
13001 // %}
13002 //
13003 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
13004 // %{
13005 // match(Set dst (AddI dst src));
13006 // effect(KILL cr);
13007 // %}
13008 //
13009 // // Change (inc mov) to lea
13010 // peephole %{
13011 // // increment preceeded by register-register move
13012 // peepmatch ( incI_rReg movI );
13013 // // require that the destination register of the increment
13014 // // match the destination register of the move
13015 // peepconstraint ( 0.dst == 1.dst );
13016 // // construct a replacement instruction that sets
13017 // // the destination to ( move's source register + one )
13018 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
13019 // %}
13020 //
13021
13022 // Implementation no longer uses movX instructions since
13023 // machine-independent system no longer uses CopyX nodes.
13024 //
13025 // peephole
13026 // %{
13027 // peepmatch (incI_rReg movI);
13028 // peepconstraint (0.dst == 1.dst);
13029 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13030 // %}
13031
13032 // peephole
13033 // %{
13034 // peepmatch (decI_rReg movI);
13035 // peepconstraint (0.dst == 1.dst);
13036 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13037 // %}
13038
13039 // peephole
13040 // %{
13041 // peepmatch (addI_rReg_imm movI);
13042 // peepconstraint (0.dst == 1.dst);
13043 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13044 // %}
13045
13046 // peephole
13047 // %{
13048 // peepmatch (incL_rReg movL);
13049 // peepconstraint (0.dst == 1.dst);
13050 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13051 // %}
13052
13053 // peephole
13054 // %{
13055 // peepmatch (decL_rReg movL);
13056 // peepconstraint (0.dst == 1.dst);
13057 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13058 // %}
13059
13060 // peephole
13061 // %{
13062 // peepmatch (addL_rReg_imm movL);
13063 // peepconstraint (0.dst == 1.dst);
13064 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13065 // %}
13066
13067 // peephole
13068 // %{
13069 // peepmatch (addP_rReg_imm movP);
13070 // peepconstraint (0.dst == 1.dst);
13071 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
13072 // %}
13073
13074 // // Change load of spilled value to only a spill
13075 // instruct storeI(memory mem, rRegI src)
13076 // %{
13077 // match(Set mem (StoreI mem src));
13078 // %}
13079 //
13080 // instruct loadI(rRegI dst, memory mem)
13081 // %{
13082 // match(Set dst (LoadI mem));
13083 // %}
13084 //
13085
13086 peephole
13087 %{
13088 peepmatch (loadI storeI);
13089 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13090 peepreplace (storeI(1.mem 1.mem 1.src));
13091 %}
13092
13093 peephole
13094 %{
13095 peepmatch (loadL storeL);
13096 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13097 peepreplace (storeL(1.mem 1.mem 1.src));
13098 %}
13099
13100 //----------SMARTSPILL RULES---------------------------------------------------
13101 // These must follow all instruction definitions as they use the names
13102 // defined in the instructions definitions.