1050 n->_idx);
1051 C->set_node_notes_at(m->_idx, nn);
1052 }
1053 debug_only(match_alias_type(C, n, m));
1054 }
1055 n = m; // n is now a new-space node
1056 mstack.set_node(n);
1057 }
1058
1059 // New space!
1060 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1061
1062 int i;
1063 // Put precedence edges on stack first (match them last).
1064 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1065 Node *m = oldn->in(i);
1066 if (m == NULL) break;
1067 // set -1 to call add_prec() instead of set_req() during Step1
1068 mstack.push(m, Visit, n, -1);
1069 }
1070
1071 // For constant debug info, I'd rather have unmatched constants.
1072 int cnt = n->req();
1073 JVMState* jvms = n->jvms();
1074 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1075
1076 // Now do only debug info. Clone constants rather than matching.
1077 // Constants are represented directly in the debug info without
1078 // the need for executable machine instructions.
1079 // Monitor boxes are also represented directly.
1080 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1081 Node *m = n->in(i); // Get input
1082 int op = m->Opcode();
1083 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1084 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1085 op == Op_ConF || op == Op_ConD || op == Op_ConL
1086 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1087 ) {
1088 m = m->clone();
1089 #ifdef ASSERT
1090 _new2old_map.map(m->_idx, n);
1741
1742 // PhaseChaitin::fixup_spills will sometimes generate spill code
1743 // via the matcher. By the time, nodes have been wired into the CFG,
1744 // and any further nodes generated by expand rules will be left hanging
1745 // in space, and will not get emitted as output code. Catch this.
1746 // Also, catch any new register allocation constraints ("projections")
1747 // generated belatedly during spill code generation.
1748 if (_allocation_started) {
1749 guarantee(ex == mach, "no expand rules during spill generation");
1750 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1751 }
1752
1753 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1754 // Record the con for sharing
1755 _shared_nodes.map(leaf->_idx, ex);
1756 }
1757
1758 return ex;
1759 }
1760
1761 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1762 // 'op' is what I am expecting to receive
1763 int op = _leftOp[rule];
1764 // Operand type to catch childs result
1765 // This is what my child will give me.
1766 int opnd_class_instance = s->_rule[op];
1767 // Choose between operand class or not.
1768 // This is what I will receive.
1769 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1770 // New rule for child. Chase operand classes to get the actual rule.
1771 int newrule = s->_rule[catch_op];
1772
1773 if( newrule < NUM_OPERANDS ) {
1774 // Chain from operand or operand class, may be output of shared node
1775 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1776 "Bad AD file: Instruction chain rule must chain from operand");
1777 // Insert operand into array of operands for this instruction
1778 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1779
1780 ReduceOper( s, newrule, mem, mach );
1781 } else {
1782 // Chain from the result of an instruction
1783 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1784 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1785 Node *mem1 = (Node*)1;
1786 debug_only(Node *save_mem_node = _mem_node;)
1787 mach->add_req( ReduceInst(s, newrule, mem1) );
1788 debug_only(_mem_node = save_mem_node;)
1789 }
1790 return;
1791 }
1792
1793
1794 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1795 if( s->_leaf->is_Load() ) {
1796 Node *mem2 = s->_leaf->in(MemNode::Memory);
1797 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1798 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1799 mem = mem2;
1800 }
1801 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1802 if( mach->in(0) == NULL )
1803 mach->set_req(0, s->_leaf->in(0));
1804 }
1805
1806 // Now recursively walk the state tree & add operand list.
1807 for( uint i=0; i<2; i++ ) { // binary tree
1808 State *newstate = s->_kids[i];
1809 if( newstate == NULL ) break; // Might only have 1 child
1810 // 'op' is what I am expecting to receive
1811 int op;
1812 if( i == 0 ) {
1813 op = _leftOp[rule];
1814 } else {
1857 // Skip over it ( do nothing )
1858 // (3) Child is an instruction -
1859 // Call ReduceInst recursively and
1860 // and instruction as an input to the MachNode
1861 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1862 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1863 State *kid = s->_kids[0];
1864 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1865
1866 // Leaf? And not subsumed?
1867 if( kid == NULL && !_swallowed[rule] ) {
1868 mach->add_req( s->_leaf ); // Add leaf pointer
1869 return; // Bail out
1870 }
1871
1872 if( s->_leaf->is_Load() ) {
1873 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1874 mem = s->_leaf->in(MemNode::Memory);
1875 debug_only(_mem_node = s->_leaf;)
1876 }
1877 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1878 if( !mach->in(0) )
1879 mach->set_req(0,s->_leaf->in(0));
1880 else {
1881 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1882 }
1883 }
1884
1885 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1886 int newrule;
1887 if( i == 0)
1888 newrule = kid->_rule[_leftOp[rule]];
1889 else
1890 newrule = kid->_rule[_rightOp[rule]];
1891
1892 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1893 // Internal operand; recurse but do nothing else
1894 ReduceOper( kid, newrule, mem, mach );
1895
1896 } else { // Child is a new instruction
|
1050 n->_idx);
1051 C->set_node_notes_at(m->_idx, nn);
1052 }
1053 debug_only(match_alias_type(C, n, m));
1054 }
1055 n = m; // n is now a new-space node
1056 mstack.set_node(n);
1057 }
1058
1059 // New space!
1060 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1061
1062 int i;
1063 // Put precedence edges on stack first (match them last).
1064 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1065 Node *m = oldn->in(i);
1066 if (m == NULL) break;
1067 // set -1 to call add_prec() instead of set_req() during Step1
1068 mstack.push(m, Visit, n, -1);
1069 }
1070 // Handle precedence edges for interior nodes
1071 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1072 Node *m = n->in(i);
1073 if (m == NULL || C->node_arena()->contains(m)) continue;
1074 n->rm_prec(i);
1075 // set -1 to call add_prec() instead of set_req() during Step1
1076 mstack.push(m, Visit, n, -1);
1077 }
1078 // For constant debug info, I'd rather have unmatched constants.
1079 int cnt = n->req();
1080 JVMState* jvms = n->jvms();
1081 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1082
1083 // Now do only debug info. Clone constants rather than matching.
1084 // Constants are represented directly in the debug info without
1085 // the need for executable machine instructions.
1086 // Monitor boxes are also represented directly.
1087 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1088 Node *m = n->in(i); // Get input
1089 int op = m->Opcode();
1090 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1091 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1092 op == Op_ConF || op == Op_ConD || op == Op_ConL
1093 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1094 ) {
1095 m = m->clone();
1096 #ifdef ASSERT
1097 _new2old_map.map(m->_idx, n);
1748
1749 // PhaseChaitin::fixup_spills will sometimes generate spill code
1750 // via the matcher. By the time, nodes have been wired into the CFG,
1751 // and any further nodes generated by expand rules will be left hanging
1752 // in space, and will not get emitted as output code. Catch this.
1753 // Also, catch any new register allocation constraints ("projections")
1754 // generated belatedly during spill code generation.
1755 if (_allocation_started) {
1756 guarantee(ex == mach, "no expand rules during spill generation");
1757 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1758 }
1759
1760 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1761 // Record the con for sharing
1762 _shared_nodes.map(leaf->_idx, ex);
1763 }
1764
1765 return ex;
1766 }
1767
1768 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1769 for (uint i = n->req(); i < n->len(); i++) {
1770 if (n->in(i) != NULL) {
1771 mach->add_prec(n->in(i));
1772 }
1773 }
1774 }
1775
1776 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1777 // 'op' is what I am expecting to receive
1778 int op = _leftOp[rule];
1779 // Operand type to catch childs result
1780 // This is what my child will give me.
1781 int opnd_class_instance = s->_rule[op];
1782 // Choose between operand class or not.
1783 // This is what I will receive.
1784 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1785 // New rule for child. Chase operand classes to get the actual rule.
1786 int newrule = s->_rule[catch_op];
1787
1788 if( newrule < NUM_OPERANDS ) {
1789 // Chain from operand or operand class, may be output of shared node
1790 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1791 "Bad AD file: Instruction chain rule must chain from operand");
1792 // Insert operand into array of operands for this instruction
1793 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1794
1795 ReduceOper( s, newrule, mem, mach );
1796 } else {
1797 // Chain from the result of an instruction
1798 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1799 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1800 Node *mem1 = (Node*)1;
1801 debug_only(Node *save_mem_node = _mem_node;)
1802 mach->add_req( ReduceInst(s, newrule, mem1) );
1803 debug_only(_mem_node = save_mem_node;)
1804 }
1805 return;
1806 }
1807
1808
1809 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1810 handle_precedence_edges(s->_leaf, mach);
1811 if( s->_leaf->is_Load() ) {
1812 Node *mem2 = s->_leaf->in(MemNode::Memory);
1813 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1814 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1815 mem = mem2;
1816 }
1817 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1818 if( mach->in(0) == NULL )
1819 mach->set_req(0, s->_leaf->in(0));
1820 }
1821
1822 // Now recursively walk the state tree & add operand list.
1823 for( uint i=0; i<2; i++ ) { // binary tree
1824 State *newstate = s->_kids[i];
1825 if( newstate == NULL ) break; // Might only have 1 child
1826 // 'op' is what I am expecting to receive
1827 int op;
1828 if( i == 0 ) {
1829 op = _leftOp[rule];
1830 } else {
1873 // Skip over it ( do nothing )
1874 // (3) Child is an instruction -
1875 // Call ReduceInst recursively and
1876 // and instruction as an input to the MachNode
1877 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1878 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1879 State *kid = s->_kids[0];
1880 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1881
1882 // Leaf? And not subsumed?
1883 if( kid == NULL && !_swallowed[rule] ) {
1884 mach->add_req( s->_leaf ); // Add leaf pointer
1885 return; // Bail out
1886 }
1887
1888 if( s->_leaf->is_Load() ) {
1889 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1890 mem = s->_leaf->in(MemNode::Memory);
1891 debug_only(_mem_node = s->_leaf;)
1892 }
1893
1894 handle_precedence_edges(s->_leaf, mach);
1895
1896 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1897 if( !mach->in(0) )
1898 mach->set_req(0,s->_leaf->in(0));
1899 else {
1900 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1901 }
1902 }
1903
1904 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1905 int newrule;
1906 if( i == 0)
1907 newrule = kid->_rule[_leftOp[rule]];
1908 else
1909 newrule = kid->_rule[_rightOp[rule]];
1910
1911 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1912 // Internal operand; recurse but do nothing else
1913 ReduceOper( kid, newrule, mem, mach );
1914
1915 } else { // Child is a new instruction
|