1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec = (disp_reloc == relocInfo::none)
192 ? RelocationHolder::none
193 : Relocation::spec_simple(disp_reloc);
194 bool valid_index = index != rsp->encoding();
195 if (valid_index) {
196 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
197 madr._rspec = rspec;
198 return madr;
199 } else {
200 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
201 madr._rspec = rspec;
202 return madr;
203 }
204 }
205
206 // Implementation of Assembler
207
208 int AbstractAssembler::code_fill_byte() {
209 return (u_char)'\xF4'; // hlt
210 }
211
212 // make this go away someday
213 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
214 if (rtype == relocInfo::none)
215 emit_int32(data);
216 else
217 emit_data(data, Relocation::spec_simple(rtype), format);
218 }
219
220 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
221 assert(imm_operand == 0, "default format must be immediate in this file");
222 assert(inst_mark() != NULL, "must be inside InstructionMark");
223 if (rspec.type() != relocInfo::none) {
224 #ifdef ASSERT
225 check_relocation(rspec, format);
226 #endif
227 // Do not use AbstractAssembler::relocate, which is not intended for
228 // embedded words. Instead, relocate to the enclosing instruction.
229
230 // hack. call32 is too wide for mask so use disp32
231 if (format == call32_operand)
232 code_section()->relocate(inst_mark(), rspec, disp32_operand);
233 else
234 code_section()->relocate(inst_mark(), rspec, format);
235 }
236 emit_int32(data);
237 }
238
239 static int encode(Register r) {
240 int enc = r->encoding();
241 if (enc >= 8) {
242 enc -= 8;
243 }
244 return enc;
245 }
246
247 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
248 assert(dst->has_byte_register(), "must have byte register");
249 assert(isByte(op1) && isByte(op2), "wrong opcode");
250 assert(isByte(imm8), "not a byte");
251 assert((op1 & 0x01) == 0, "should be 8bit operation");
252 emit_int8(op1);
253 emit_int8(op2 | encode(dst));
254 emit_int8(imm8);
255 }
256
257
258 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
259 assert(isByte(op1) && isByte(op2), "wrong opcode");
260 assert((op1 & 0x01) == 1, "should be 32bit operation");
261 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
262 if (is8bit(imm32)) {
263 emit_int8(op1 | 0x02); // set sign bit
264 emit_int8(op2 | encode(dst));
265 emit_int8(imm32 & 0xFF);
266 } else {
267 emit_int8(op1);
268 emit_int8(op2 | encode(dst));
269 emit_int32(imm32);
270 }
271 }
272
273 // Force generation of a 4 byte immediate value even if it fits into 8bit
274 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
275 assert(isByte(op1) && isByte(op2), "wrong opcode");
276 assert((op1 & 0x01) == 1, "should be 32bit operation");
277 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
278 emit_int8(op1);
279 emit_int8(op2 | encode(dst));
280 emit_int32(imm32);
281 }
282
283 // immediate-to-memory forms
284 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
285 assert((op1 & 0x01) == 1, "should be 32bit operation");
286 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
287 if (is8bit(imm32)) {
288 emit_int8(op1 | 0x02); // set sign bit
289 emit_operand(rm, adr, 1);
290 emit_int8(imm32 & 0xFF);
291 } else {
292 emit_int8(op1);
293 emit_operand(rm, adr, 4);
294 emit_int32(imm32);
295 }
296 }
297
298
299 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
300 assert(isByte(op1) && isByte(op2), "wrong opcode");
301 emit_int8(op1);
302 emit_int8(op2 | encode(dst) << 3 | encode(src));
303 }
304
305
306 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
307 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
308 int mod_idx = 0;
309 // We will test if the displacement fits the compressed format and if so
310 // apply the compression to the displacment iff the result is8bit.
311 if (VM_Version::supports_evex() && is_evex_inst) {
312 switch (cur_tuple_type) {
313 case EVEX_FV:
314 if ((cur_encoding & VEX_W) == VEX_W) {
315 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
316 } else {
317 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
318 }
319 break;
320
321 case EVEX_HV:
322 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
323 break;
324
325 case EVEX_FVM:
326 break;
327
328 case EVEX_T1S:
329 switch (in_size_in_bits) {
330 case EVEX_8bit:
331 break;
332
333 case EVEX_16bit:
334 mod_idx = 1;
335 break;
336
337 case EVEX_32bit:
338 mod_idx = 2;
339 break;
340
341 case EVEX_64bit:
342 mod_idx = 3;
343 break;
344 }
345 break;
346
347 case EVEX_T1F:
348 case EVEX_T2:
349 case EVEX_T4:
350 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
351 break;
352
353 case EVEX_T8:
354 break;
355
356 case EVEX_HVM:
357 break;
358
359 case EVEX_QVM:
360 break;
361
362 case EVEX_OVM:
363 break;
364
365 case EVEX_M128:
366 break;
367
368 case EVEX_DUP:
369 break;
370
371 default:
372 assert(0, "no valid evex tuple_table entry");
373 break;
374 }
375
376 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
377 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
378 if ((disp % disp_factor) == 0) {
379 int new_disp = disp / disp_factor;
380 if ((-0x80 <= new_disp && new_disp < 0x80)) {
381 disp = new_disp;
382 }
383 } else {
384 return false;
385 }
386 }
387 }
388 return (-0x80 <= disp && disp < 0x80);
389 }
390
391
392 bool Assembler::emit_compressed_disp_byte(int &disp) {
393 int mod_idx = 0;
394 // We will test if the displacement fits the compressed format and if so
395 // apply the compression to the displacment iff the result is8bit.
396 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
397 int evex_encoding = _attributes->get_evex_encoding();
398 int tuple_type = _attributes->get_tuple_type();
399 switch (tuple_type) {
400 case EVEX_FV:
401 if ((evex_encoding & VEX_W) == VEX_W) {
402 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
403 } else {
404 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
405 }
406 break;
407
408 case EVEX_HV:
409 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
410 break;
411
412 case EVEX_FVM:
413 break;
414
415 case EVEX_T1S:
416 switch (_attributes->get_input_size()) {
417 case EVEX_8bit:
418 break;
419
420 case EVEX_16bit:
421 mod_idx = 1;
422 break;
423
424 case EVEX_32bit:
425 mod_idx = 2;
426 break;
427
428 case EVEX_64bit:
429 mod_idx = 3;
430 break;
431 }
432 break;
433
434 case EVEX_T1F:
435 case EVEX_T2:
436 case EVEX_T4:
437 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
438 break;
439
440 case EVEX_T8:
441 break;
442
443 case EVEX_HVM:
444 break;
445
446 case EVEX_QVM:
447 break;
448
449 case EVEX_OVM:
450 break;
451
452 case EVEX_M128:
453 break;
454
455 case EVEX_DUP:
456 break;
457
458 default:
459 assert(0, "no valid evex tuple_table entry");
460 break;
461 }
462
463 int vector_len = _attributes->get_vector_len();
464 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
465 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
466 if ((disp % disp_factor) == 0) {
467 int new_disp = disp / disp_factor;
468 if (is8bit(new_disp)) {
469 disp = new_disp;
470 }
471 } else {
472 return false;
473 }
474 }
475 }
476 return is8bit(disp);
477 }
478
479
480 void Assembler::emit_operand(Register reg, Register base, Register index,
481 Address::ScaleFactor scale, int disp,
482 RelocationHolder const& rspec,
483 int rip_relative_correction) {
484 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
485
486 // Encode the registers as needed in the fields they are used in
487
488 int regenc = encode(reg) << 3;
489 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
490 int baseenc = base->is_valid() ? encode(base) : 0;
491
492 if (base->is_valid()) {
493 if (index->is_valid()) {
494 assert(scale != Address::no_scale, "inconsistent address");
495 // [base + index*scale + disp]
496 if (disp == 0 && rtype == relocInfo::none &&
497 base != rbp LP64_ONLY(&& base != r13)) {
498 // [base + index*scale]
499 // [00 reg 100][ss index base]
500 assert(index != rsp, "illegal addressing mode");
501 emit_int8(0x04 | regenc);
502 emit_int8(scale << 6 | indexenc | baseenc);
503 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
504 // [base + index*scale + imm8]
505 // [01 reg 100][ss index base] imm8
506 assert(index != rsp, "illegal addressing mode");
507 emit_int8(0x44 | regenc);
508 emit_int8(scale << 6 | indexenc | baseenc);
509 emit_int8(disp & 0xFF);
510 } else {
511 // [base + index*scale + disp32]
512 // [10 reg 100][ss index base] disp32
513 assert(index != rsp, "illegal addressing mode");
514 emit_int8(0x84 | regenc);
515 emit_int8(scale << 6 | indexenc | baseenc);
516 emit_data(disp, rspec, disp32_operand);
517 }
518 } else if (base == rsp LP64_ONLY(|| base == r12)) {
519 // [rsp + disp]
520 if (disp == 0 && rtype == relocInfo::none) {
521 // [rsp]
522 // [00 reg 100][00 100 100]
523 emit_int8(0x04 | regenc);
524 emit_int8(0x24);
525 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
526 // [rsp + imm8]
527 // [01 reg 100][00 100 100] disp8
528 emit_int8(0x44 | regenc);
529 emit_int8(0x24);
530 emit_int8(disp & 0xFF);
531 } else {
532 // [rsp + imm32]
533 // [10 reg 100][00 100 100] disp32
534 emit_int8(0x84 | regenc);
535 emit_int8(0x24);
536 emit_data(disp, rspec, disp32_operand);
537 }
538 } else {
539 // [base + disp]
540 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
541 if (disp == 0 && rtype == relocInfo::none &&
542 base != rbp LP64_ONLY(&& base != r13)) {
543 // [base]
544 // [00 reg base]
545 emit_int8(0x00 | regenc | baseenc);
546 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
547 // [base + disp8]
548 // [01 reg base] disp8
549 emit_int8(0x40 | regenc | baseenc);
550 emit_int8(disp & 0xFF);
551 } else {
552 // [base + disp32]
553 // [10 reg base] disp32
554 emit_int8(0x80 | regenc | baseenc);
555 emit_data(disp, rspec, disp32_operand);
556 }
557 }
558 } else {
559 if (index->is_valid()) {
560 assert(scale != Address::no_scale, "inconsistent address");
561 // [index*scale + disp]
562 // [00 reg 100][ss index 101] disp32
563 assert(index != rsp, "illegal addressing mode");
564 emit_int8(0x04 | regenc);
565 emit_int8(scale << 6 | indexenc | 0x05);
566 emit_data(disp, rspec, disp32_operand);
567 } else if (rtype != relocInfo::none ) {
568 // [disp] (64bit) RIP-RELATIVE (32bit) abs
569 // [00 000 101] disp32
570
571 emit_int8(0x05 | regenc);
572 // Note that the RIP-rel. correction applies to the generated
573 // disp field, but _not_ to the target address in the rspec.
574
575 // disp was created by converting the target address minus the pc
576 // at the start of the instruction. That needs more correction here.
577 // intptr_t disp = target - next_ip;
578 assert(inst_mark() != NULL, "must be inside InstructionMark");
579 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
580 int64_t adjusted = disp;
581 // Do rip-rel adjustment for 64bit
582 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
583 assert(is_simm32(adjusted),
584 "must be 32bit offset (RIP relative address)");
585 emit_data((int32_t) adjusted, rspec, disp32_operand);
586
587 } else {
588 // 32bit never did this, did everything as the rip-rel/disp code above
589 // [disp] ABSOLUTE
590 // [00 reg 100][00 100 101] disp32
591 emit_int8(0x04 | regenc);
592 emit_int8(0x25);
593 emit_data(disp, rspec, disp32_operand);
594 }
595 }
596 }
597
598 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
599 Address::ScaleFactor scale, int disp,
600 RelocationHolder const& rspec) {
601 if (UseAVX > 2) {
602 int xreg_enc = reg->encoding();
603 if (xreg_enc > 15) {
604 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
605 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
606 return;
607 }
608 }
609 emit_operand((Register)reg, base, index, scale, disp, rspec);
610 }
611
612 // Secret local extension to Assembler::WhichOperand:
613 #define end_pc_operand (_WhichOperand_limit)
614
615 address Assembler::locate_operand(address inst, WhichOperand which) {
616 // Decode the given instruction, and return the address of
617 // an embedded 32-bit operand word.
618
619 // If "which" is disp32_operand, selects the displacement portion
620 // of an effective address specifier.
621 // If "which" is imm64_operand, selects the trailing immediate constant.
622 // If "which" is call32_operand, selects the displacement of a call or jump.
623 // Caller is responsible for ensuring that there is such an operand,
624 // and that it is 32/64 bits wide.
625
626 // If "which" is end_pc_operand, find the end of the instruction.
627
628 address ip = inst;
629 bool is_64bit = false;
630
631 debug_only(bool has_disp32 = false);
632 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
633
634 again_after_prefix:
635 switch (0xFF & *ip++) {
636
637 // These convenience macros generate groups of "case" labels for the switch.
638 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
639 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
640 case (x)+4: case (x)+5: case (x)+6: case (x)+7
641 #define REP16(x) REP8((x)+0): \
642 case REP8((x)+8)
643
644 case CS_segment:
645 case SS_segment:
646 case DS_segment:
647 case ES_segment:
648 case FS_segment:
649 case GS_segment:
650 // Seems dubious
651 LP64_ONLY(assert(false, "shouldn't have that prefix"));
652 assert(ip == inst+1, "only one prefix allowed");
653 goto again_after_prefix;
654
655 case 0x67:
656 case REX:
657 case REX_B:
658 case REX_X:
659 case REX_XB:
660 case REX_R:
661 case REX_RB:
662 case REX_RX:
663 case REX_RXB:
664 NOT_LP64(assert(false, "64bit prefixes"));
665 goto again_after_prefix;
666
667 case REX_W:
668 case REX_WB:
669 case REX_WX:
670 case REX_WXB:
671 case REX_WR:
672 case REX_WRB:
673 case REX_WRX:
674 case REX_WRXB:
675 NOT_LP64(assert(false, "64bit prefixes"));
676 is_64bit = true;
677 goto again_after_prefix;
678
679 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
680 case 0x88: // movb a, r
681 case 0x89: // movl a, r
682 case 0x8A: // movb r, a
683 case 0x8B: // movl r, a
684 case 0x8F: // popl a
685 debug_only(has_disp32 = true);
686 break;
687
688 case 0x68: // pushq #32
689 if (which == end_pc_operand) {
690 return ip + 4;
691 }
692 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
693 return ip; // not produced by emit_operand
694
695 case 0x66: // movw ... (size prefix)
696 again_after_size_prefix2:
697 switch (0xFF & *ip++) {
698 case REX:
699 case REX_B:
700 case REX_X:
701 case REX_XB:
702 case REX_R:
703 case REX_RB:
704 case REX_RX:
705 case REX_RXB:
706 case REX_W:
707 case REX_WB:
708 case REX_WX:
709 case REX_WXB:
710 case REX_WR:
711 case REX_WRB:
712 case REX_WRX:
713 case REX_WRXB:
714 NOT_LP64(assert(false, "64bit prefix found"));
715 goto again_after_size_prefix2;
716 case 0x8B: // movw r, a
717 case 0x89: // movw a, r
718 debug_only(has_disp32 = true);
719 break;
720 case 0xC7: // movw a, #16
721 debug_only(has_disp32 = true);
722 tail_size = 2; // the imm16
723 break;
724 case 0x0F: // several SSE/SSE2 variants
725 ip--; // reparse the 0x0F
726 goto again_after_prefix;
727 default:
728 ShouldNotReachHere();
729 }
730 break;
731
732 case REP8(0xB8): // movl/q r, #32/#64(oop?)
733 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
734 // these asserts are somewhat nonsensical
735 #ifndef _LP64
736 assert(which == imm_operand || which == disp32_operand,
737 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
738 #else
739 assert((which == call32_operand || which == imm_operand) && is_64bit ||
740 which == narrow_oop_operand && !is_64bit,
741 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
742 #endif // _LP64
743 return ip;
744
745 case 0x69: // imul r, a, #32
746 case 0xC7: // movl a, #32(oop?)
747 tail_size = 4;
748 debug_only(has_disp32 = true); // has both kinds of operands!
749 break;
750
751 case 0x0F: // movx..., etc.
752 switch (0xFF & *ip++) {
753 case 0x3A: // pcmpestri
754 tail_size = 1;
755 case 0x38: // ptest, pmovzxbw
756 ip++; // skip opcode
757 debug_only(has_disp32 = true); // has both kinds of operands!
758 break;
759
760 case 0x70: // pshufd r, r/a, #8
761 debug_only(has_disp32 = true); // has both kinds of operands!
762 case 0x73: // psrldq r, #8
763 tail_size = 1;
764 break;
765
766 case 0x12: // movlps
767 case 0x28: // movaps
768 case 0x2E: // ucomiss
769 case 0x2F: // comiss
770 case 0x54: // andps
771 case 0x55: // andnps
772 case 0x56: // orps
773 case 0x57: // xorps
774 case 0x58: // addpd
775 case 0x59: // mulpd
776 case 0x6E: // movd
777 case 0x7E: // movd
778 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
779 case 0xFE: // paddd
780 debug_only(has_disp32 = true);
781 break;
782
783 case 0xAD: // shrd r, a, %cl
784 case 0xAF: // imul r, a
785 case 0xBE: // movsbl r, a (movsxb)
786 case 0xBF: // movswl r, a (movsxw)
787 case 0xB6: // movzbl r, a (movzxb)
788 case 0xB7: // movzwl r, a (movzxw)
789 case REP16(0x40): // cmovl cc, r, a
790 case 0xB0: // cmpxchgb
791 case 0xB1: // cmpxchg
792 case 0xC1: // xaddl
793 case 0xC7: // cmpxchg8
794 case REP16(0x90): // setcc a
795 debug_only(has_disp32 = true);
796 // fall out of the switch to decode the address
797 break;
798
799 case 0xC4: // pinsrw r, a, #8
800 debug_only(has_disp32 = true);
801 case 0xC5: // pextrw r, r, #8
802 tail_size = 1; // the imm8
803 break;
804
805 case 0xAC: // shrd r, a, #8
806 debug_only(has_disp32 = true);
807 tail_size = 1; // the imm8
808 break;
809
810 case REP16(0x80): // jcc rdisp32
811 if (which == end_pc_operand) return ip + 4;
812 assert(which == call32_operand, "jcc has no disp32 or imm");
813 return ip;
814 default:
815 ShouldNotReachHere();
816 }
817 break;
818
819 case 0x81: // addl a, #32; addl r, #32
820 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
821 // on 32bit in the case of cmpl, the imm might be an oop
822 tail_size = 4;
823 debug_only(has_disp32 = true); // has both kinds of operands!
824 break;
825
826 case 0x83: // addl a, #8; addl r, #8
827 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
828 debug_only(has_disp32 = true); // has both kinds of operands!
829 tail_size = 1;
830 break;
831
832 case 0x9B:
833 switch (0xFF & *ip++) {
834 case 0xD9: // fnstcw a
835 debug_only(has_disp32 = true);
836 break;
837 default:
838 ShouldNotReachHere();
839 }
840 break;
841
842 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
843 case REP4(0x10): // adc...
844 case REP4(0x20): // and...
845 case REP4(0x30): // xor...
846 case REP4(0x08): // or...
847 case REP4(0x18): // sbb...
848 case REP4(0x28): // sub...
849 case 0xF7: // mull a
850 case 0x8D: // lea r, a
851 case 0x87: // xchg r, a
852 case REP4(0x38): // cmp...
853 case 0x85: // test r, a
854 debug_only(has_disp32 = true); // has both kinds of operands!
855 break;
856
857 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
858 case 0xC6: // movb a, #8
859 case 0x80: // cmpb a, #8
860 case 0x6B: // imul r, a, #8
861 debug_only(has_disp32 = true); // has both kinds of operands!
862 tail_size = 1; // the imm8
863 break;
864
865 case 0xC4: // VEX_3bytes
866 case 0xC5: // VEX_2bytes
867 assert((UseAVX > 0), "shouldn't have VEX prefix");
868 assert(ip == inst+1, "no prefixes allowed");
869 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
870 // but they have prefix 0x0F and processed when 0x0F processed above.
871 //
872 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
873 // instructions (these instructions are not supported in 64-bit mode).
874 // To distinguish them bits [7:6] are set in the VEX second byte since
875 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
876 // those VEX bits REX and vvvv bits are inverted.
877 //
878 // Fortunately C2 doesn't generate these instructions so we don't need
879 // to check for them in product version.
880
881 // Check second byte
882 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
883
884 int vex_opcode;
885 // First byte
886 if ((0xFF & *inst) == VEX_3bytes) {
887 vex_opcode = VEX_OPCODE_MASK & *ip;
888 ip++; // third byte
889 is_64bit = ((VEX_W & *ip) == VEX_W);
890 } else {
891 vex_opcode = VEX_OPCODE_0F;
892 }
893 ip++; // opcode
894 // To find the end of instruction (which == end_pc_operand).
895 switch (vex_opcode) {
896 case VEX_OPCODE_0F:
897 switch (0xFF & *ip) {
898 case 0x70: // pshufd r, r/a, #8
899 case 0x71: // ps[rl|ra|ll]w r, #8
900 case 0x72: // ps[rl|ra|ll]d r, #8
901 case 0x73: // ps[rl|ra|ll]q r, #8
902 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
903 case 0xC4: // pinsrw r, r, r/a, #8
904 case 0xC5: // pextrw r/a, r, #8
905 case 0xC6: // shufp[s|d] r, r, r/a, #8
906 tail_size = 1; // the imm8
907 break;
908 }
909 break;
910 case VEX_OPCODE_0F_3A:
911 tail_size = 1;
912 break;
913 }
914 ip++; // skip opcode
915 debug_only(has_disp32 = true); // has both kinds of operands!
916 break;
917
918 case 0x62: // EVEX_4bytes
919 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
920 assert(ip == inst+1, "no prefixes allowed");
921 // no EVEX collisions, all instructions that have 0x62 opcodes
922 // have EVEX versions and are subopcodes of 0x66
923 ip++; // skip P0 and exmaine W in P1
924 is_64bit = ((VEX_W & *ip) == VEX_W);
925 ip++; // move to P2
926 ip++; // skip P2, move to opcode
927 // To find the end of instruction (which == end_pc_operand).
928 switch (0xFF & *ip) {
929 case 0x22: // pinsrd r, r/a, #8
930 case 0x61: // pcmpestri r, r/a, #8
931 case 0x70: // pshufd r, r/a, #8
932 case 0x73: // psrldq r, #8
933 tail_size = 1; // the imm8
934 break;
935 default:
936 break;
937 }
938 ip++; // skip opcode
939 debug_only(has_disp32 = true); // has both kinds of operands!
940 break;
941
942 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
943 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
944 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
945 case 0xDD: // fld_d a; fst_d a; fstp_d a
946 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
947 case 0xDF: // fild_d a; fistp_d a
948 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
949 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
950 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
951 debug_only(has_disp32 = true);
952 break;
953
954 case 0xE8: // call rdisp32
955 case 0xE9: // jmp rdisp32
956 if (which == end_pc_operand) return ip + 4;
957 assert(which == call32_operand, "call has no disp32 or imm");
958 return ip;
959
960 case 0xF0: // Lock
961 assert(os::is_MP(), "only on MP");
962 goto again_after_prefix;
963
964 case 0xF3: // For SSE
965 case 0xF2: // For SSE2
966 switch (0xFF & *ip++) {
967 case REX:
968 case REX_B:
969 case REX_X:
970 case REX_XB:
971 case REX_R:
972 case REX_RB:
973 case REX_RX:
974 case REX_RXB:
975 case REX_W:
976 case REX_WB:
977 case REX_WX:
978 case REX_WXB:
979 case REX_WR:
980 case REX_WRB:
981 case REX_WRX:
982 case REX_WRXB:
983 NOT_LP64(assert(false, "found 64bit prefix"));
984 ip++;
985 default:
986 ip++;
987 }
988 debug_only(has_disp32 = true); // has both kinds of operands!
989 break;
990
991 default:
992 ShouldNotReachHere();
993
994 #undef REP8
995 #undef REP16
996 }
997
998 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
999 #ifdef _LP64
1000 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1001 #else
1002 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1003 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1004 #endif // LP64
1005 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1006
1007 // parse the output of emit_operand
1008 int op2 = 0xFF & *ip++;
1009 int base = op2 & 0x07;
1010 int op3 = -1;
1011 const int b100 = 4;
1012 const int b101 = 5;
1013 if (base == b100 && (op2 >> 6) != 3) {
1014 op3 = 0xFF & *ip++;
1015 base = op3 & 0x07; // refetch the base
1016 }
1017 // now ip points at the disp (if any)
1018
1019 switch (op2 >> 6) {
1020 case 0:
1021 // [00 reg 100][ss index base]
1022 // [00 reg 100][00 100 esp]
1023 // [00 reg base]
1024 // [00 reg 100][ss index 101][disp32]
1025 // [00 reg 101] [disp32]
1026
1027 if (base == b101) {
1028 if (which == disp32_operand)
1029 return ip; // caller wants the disp32
1030 ip += 4; // skip the disp32
1031 }
1032 break;
1033
1034 case 1:
1035 // [01 reg 100][ss index base][disp8]
1036 // [01 reg 100][00 100 esp][disp8]
1037 // [01 reg base] [disp8]
1038 ip += 1; // skip the disp8
1039 break;
1040
1041 case 2:
1042 // [10 reg 100][ss index base][disp32]
1043 // [10 reg 100][00 100 esp][disp32]
1044 // [10 reg base] [disp32]
1045 if (which == disp32_operand)
1046 return ip; // caller wants the disp32
1047 ip += 4; // skip the disp32
1048 break;
1049
1050 case 3:
1051 // [11 reg base] (not a memory addressing mode)
1052 break;
1053 }
1054
1055 if (which == end_pc_operand) {
1056 return ip + tail_size;
1057 }
1058
1059 #ifdef _LP64
1060 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1061 #else
1062 assert(which == imm_operand, "instruction has only an imm field");
1063 #endif // LP64
1064 return ip;
1065 }
1066
1067 address Assembler::locate_next_instruction(address inst) {
1068 // Secretly share code with locate_operand:
1069 return locate_operand(inst, end_pc_operand);
1070 }
1071
1072
1073 #ifdef ASSERT
1074 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1075 address inst = inst_mark();
1076 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1077 address opnd;
1078
1079 Relocation* r = rspec.reloc();
1080 if (r->type() == relocInfo::none) {
1081 return;
1082 } else if (r->is_call() || format == call32_operand) {
1083 // assert(format == imm32_operand, "cannot specify a nonzero format");
1084 opnd = locate_operand(inst, call32_operand);
1085 } else if (r->is_data()) {
1086 assert(format == imm_operand || format == disp32_operand
1087 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1088 opnd = locate_operand(inst, (WhichOperand)format);
1089 } else {
1090 assert(format == imm_operand, "cannot specify a format");
1091 return;
1092 }
1093 assert(opnd == pc(), "must put operand where relocs can find it");
1094 }
1095 #endif // ASSERT
1096
1097 void Assembler::emit_operand32(Register reg, Address adr) {
1098 assert(reg->encoding() < 8, "no extended registers");
1099 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1100 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1101 adr._rspec);
1102 }
1103
1104 void Assembler::emit_operand(Register reg, Address adr,
1105 int rip_relative_correction) {
1106 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1107 adr._rspec,
1108 rip_relative_correction);
1109 }
1110
1111 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1112 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1113 adr._rspec);
1114 }
1115
1116 // MMX operations
1117 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1118 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1119 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1120 }
1121
1122 // work around gcc (3.2.1-7a) bug
1123 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1124 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1125 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1126 }
1127
1128
1129 void Assembler::emit_farith(int b1, int b2, int i) {
1130 assert(isByte(b1) && isByte(b2), "wrong opcode");
1131 assert(0 <= i && i < 8, "illegal stack offset");
1132 emit_int8(b1);
1133 emit_int8(b2 + i);
1134 }
1135
1136
1137 // Now the Assembler instructions (identical for 32/64 bits)
1138
1139 void Assembler::adcl(Address dst, int32_t imm32) {
1140 InstructionMark im(this);
1141 prefix(dst);
1142 emit_arith_operand(0x81, rdx, dst, imm32);
1143 }
1144
1145 void Assembler::adcl(Address dst, Register src) {
1146 InstructionMark im(this);
1147 prefix(dst, src);
1148 emit_int8(0x11);
1149 emit_operand(src, dst);
1150 }
1151
1152 void Assembler::adcl(Register dst, int32_t imm32) {
1153 prefix(dst);
1154 emit_arith(0x81, 0xD0, dst, imm32);
1155 }
1156
1157 void Assembler::adcl(Register dst, Address src) {
1158 InstructionMark im(this);
1159 prefix(src, dst);
1160 emit_int8(0x13);
1161 emit_operand(dst, src);
1162 }
1163
1164 void Assembler::adcl(Register dst, Register src) {
1165 (void) prefix_and_encode(dst->encoding(), src->encoding());
1166 emit_arith(0x13, 0xC0, dst, src);
1167 }
1168
1169 void Assembler::addl(Address dst, int32_t imm32) {
1170 InstructionMark im(this);
1171 prefix(dst);
1172 emit_arith_operand(0x81, rax, dst, imm32);
1173 }
1174
1175 void Assembler::addb(Address dst, int imm8) {
1176 InstructionMark im(this);
1177 prefix(dst);
1178 emit_int8((unsigned char)0x80);
1179 emit_operand(rax, dst, 1);
1180 emit_int8(imm8);
1181 }
1182
1183 void Assembler::addw(Address dst, int imm16) {
1184 InstructionMark im(this);
1185 emit_int8(0x66);
1186 prefix(dst);
1187 emit_int8((unsigned char)0x81);
1188 emit_operand(rax, dst, 2);
1189 emit_int16(imm16);
1190 }
1191
1192 void Assembler::addl(Address dst, Register src) {
1193 InstructionMark im(this);
1194 prefix(dst, src);
1195 emit_int8(0x01);
1196 emit_operand(src, dst);
1197 }
1198
1199 void Assembler::addl(Register dst, int32_t imm32) {
1200 prefix(dst);
1201 emit_arith(0x81, 0xC0, dst, imm32);
1202 }
1203
1204 void Assembler::addl(Register dst, Address src) {
1205 InstructionMark im(this);
1206 prefix(src, dst);
1207 emit_int8(0x03);
1208 emit_operand(dst, src);
1209 }
1210
1211 void Assembler::addl(Register dst, Register src) {
1212 (void) prefix_and_encode(dst->encoding(), src->encoding());
1213 emit_arith(0x03, 0xC0, dst, src);
1214 }
1215
1216 void Assembler::addr_nop_4() {
1217 assert(UseAddressNop, "no CPU support");
1218 // 4 bytes: NOP DWORD PTR [EAX+0]
1219 emit_int8(0x0F);
1220 emit_int8(0x1F);
1221 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1222 emit_int8(0); // 8-bits offset (1 byte)
1223 }
1224
1225 void Assembler::addr_nop_5() {
1226 assert(UseAddressNop, "no CPU support");
1227 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1228 emit_int8(0x0F);
1229 emit_int8(0x1F);
1230 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1231 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1232 emit_int8(0); // 8-bits offset (1 byte)
1233 }
1234
1235 void Assembler::addr_nop_7() {
1236 assert(UseAddressNop, "no CPU support");
1237 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1238 emit_int8(0x0F);
1239 emit_int8(0x1F);
1240 emit_int8((unsigned char)0x80);
1241 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1242 emit_int32(0); // 32-bits offset (4 bytes)
1243 }
1244
1245 void Assembler::addr_nop_8() {
1246 assert(UseAddressNop, "no CPU support");
1247 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1248 emit_int8(0x0F);
1249 emit_int8(0x1F);
1250 emit_int8((unsigned char)0x84);
1251 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1252 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1253 emit_int32(0); // 32-bits offset (4 bytes)
1254 }
1255
1256 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1257 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1258 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1259 attributes.set_rex_vex_w_reverted();
1260 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1261 emit_int8(0x58);
1262 emit_int8((unsigned char)(0xC0 | encode));
1263 }
1264
1265 void Assembler::addsd(XMMRegister dst, Address src) {
1266 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1267 InstructionMark im(this);
1268 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1269 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1270 attributes.set_rex_vex_w_reverted();
1271 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1272 emit_int8(0x58);
1273 emit_operand(dst, src);
1274 }
1275
1276 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1277 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1278 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1279 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1280 emit_int8(0x58);
1281 emit_int8((unsigned char)(0xC0 | encode));
1282 }
1283
1284 void Assembler::addss(XMMRegister dst, Address src) {
1285 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1286 InstructionMark im(this);
1287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1288 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1289 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1290 emit_int8(0x58);
1291 emit_operand(dst, src);
1292 }
1293
1294 void Assembler::aesdec(XMMRegister dst, Address src) {
1295 assert(VM_Version::supports_aes(), "");
1296 InstructionMark im(this);
1297 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1298 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1299 emit_int8((unsigned char)0xDE);
1300 emit_operand(dst, src);
1301 }
1302
1303 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1304 assert(VM_Version::supports_aes(), "");
1305 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1306 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1307 emit_int8((unsigned char)0xDE);
1308 emit_int8(0xC0 | encode);
1309 }
1310
1311 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1312 assert(VM_Version::supports_aes(), "");
1313 InstructionMark im(this);
1314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1315 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1316 emit_int8((unsigned char)0xDF);
1317 emit_operand(dst, src);
1318 }
1319
1320 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1321 assert(VM_Version::supports_aes(), "");
1322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1324 emit_int8((unsigned char)0xDF);
1325 emit_int8((unsigned char)(0xC0 | encode));
1326 }
1327
1328 void Assembler::aesenc(XMMRegister dst, Address src) {
1329 assert(VM_Version::supports_aes(), "");
1330 InstructionMark im(this);
1331 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1332 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1333 emit_int8((unsigned char)0xDC);
1334 emit_operand(dst, src);
1335 }
1336
1337 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1338 assert(VM_Version::supports_aes(), "");
1339 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1340 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1341 emit_int8((unsigned char)0xDC);
1342 emit_int8(0xC0 | encode);
1343 }
1344
1345 void Assembler::aesenclast(XMMRegister dst, Address src) {
1346 assert(VM_Version::supports_aes(), "");
1347 InstructionMark im(this);
1348 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1349 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1350 emit_int8((unsigned char)0xDD);
1351 emit_operand(dst, src);
1352 }
1353
1354 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1355 assert(VM_Version::supports_aes(), "");
1356 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1357 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1358 emit_int8((unsigned char)0xDD);
1359 emit_int8((unsigned char)(0xC0 | encode));
1360 }
1361
1362 void Assembler::andl(Address dst, int32_t imm32) {
1363 InstructionMark im(this);
1364 prefix(dst);
1365 emit_int8((unsigned char)0x81);
1366 emit_operand(rsp, dst, 4);
1367 emit_int32(imm32);
1368 }
1369
1370 void Assembler::andl(Register dst, int32_t imm32) {
1371 prefix(dst);
1372 emit_arith(0x81, 0xE0, dst, imm32);
1373 }
1374
1375 void Assembler::andl(Register dst, Address src) {
1376 InstructionMark im(this);
1377 prefix(src, dst);
1378 emit_int8(0x23);
1379 emit_operand(dst, src);
1380 }
1381
1382 void Assembler::andl(Register dst, Register src) {
1383 (void) prefix_and_encode(dst->encoding(), src->encoding());
1384 emit_arith(0x23, 0xC0, dst, src);
1385 }
1386
1387 void Assembler::andnl(Register dst, Register src1, Register src2) {
1388 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1389 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1390 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1391 emit_int8((unsigned char)0xF2);
1392 emit_int8((unsigned char)(0xC0 | encode));
1393 }
1394
1395 void Assembler::andnl(Register dst, Register src1, Address src2) {
1396 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1397 InstructionMark im(this);
1398 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1399 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1400 emit_int8((unsigned char)0xF2);
1401 emit_operand(dst, src2);
1402 }
1403
1404 void Assembler::bsfl(Register dst, Register src) {
1405 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1406 emit_int8(0x0F);
1407 emit_int8((unsigned char)0xBC);
1408 emit_int8((unsigned char)(0xC0 | encode));
1409 }
1410
1411 void Assembler::bsrl(Register dst, Register src) {
1412 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1413 emit_int8(0x0F);
1414 emit_int8((unsigned char)0xBD);
1415 emit_int8((unsigned char)(0xC0 | encode));
1416 }
1417
1418 void Assembler::bswapl(Register reg) { // bswap
1419 int encode = prefix_and_encode(reg->encoding());
1420 emit_int8(0x0F);
1421 emit_int8((unsigned char)(0xC8 | encode));
1422 }
1423
1424 void Assembler::blsil(Register dst, Register src) {
1425 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1426 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1427 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1428 emit_int8((unsigned char)0xF3);
1429 emit_int8((unsigned char)(0xC0 | encode));
1430 }
1431
1432 void Assembler::blsil(Register dst, Address src) {
1433 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1434 InstructionMark im(this);
1435 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1436 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1437 emit_int8((unsigned char)0xF3);
1438 emit_operand(rbx, src);
1439 }
1440
1441 void Assembler::blsmskl(Register dst, Register src) {
1442 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1443 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1444 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1445 emit_int8((unsigned char)0xF3);
1446 emit_int8((unsigned char)(0xC0 | encode));
1447 }
1448
1449 void Assembler::blsmskl(Register dst, Address src) {
1450 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1451 InstructionMark im(this);
1452 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1453 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1454 emit_int8((unsigned char)0xF3);
1455 emit_operand(rdx, src);
1456 }
1457
1458 void Assembler::blsrl(Register dst, Register src) {
1459 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1460 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1461 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1462 emit_int8((unsigned char)0xF3);
1463 emit_int8((unsigned char)(0xC0 | encode));
1464 }
1465
1466 void Assembler::blsrl(Register dst, Address src) {
1467 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1468 InstructionMark im(this);
1469 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1470 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1471 emit_int8((unsigned char)0xF3);
1472 emit_operand(rcx, src);
1473 }
1474
1475 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1476 // suspect disp32 is always good
1477 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1478
1479 if (L.is_bound()) {
1480 const int long_size = 5;
1481 int offs = (int)( target(L) - pc() );
1482 assert(offs <= 0, "assembler error");
1483 InstructionMark im(this);
1484 // 1110 1000 #32-bit disp
1485 emit_int8((unsigned char)0xE8);
1486 emit_data(offs - long_size, rtype, operand);
1487 } else {
1488 InstructionMark im(this);
1489 // 1110 1000 #32-bit disp
1490 L.add_patch_at(code(), locator());
1491
1492 emit_int8((unsigned char)0xE8);
1493 emit_data(int(0), rtype, operand);
1494 }
1495 }
1496
1497 void Assembler::call(Register dst) {
1498 int encode = prefix_and_encode(dst->encoding());
1499 emit_int8((unsigned char)0xFF);
1500 emit_int8((unsigned char)(0xD0 | encode));
1501 }
1502
1503
1504 void Assembler::call(Address adr) {
1505 InstructionMark im(this);
1506 prefix(adr);
1507 emit_int8((unsigned char)0xFF);
1508 emit_operand(rdx, adr);
1509 }
1510
1511 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1512 assert(entry != NULL, "call most probably wrong");
1513 InstructionMark im(this);
1514 emit_int8((unsigned char)0xE8);
1515 intptr_t disp = entry - (pc() + sizeof(int32_t));
1516 assert(is_simm32(disp), "must be 32bit offset (call2)");
1517 // Technically, should use call32_operand, but this format is
1518 // implied by the fact that we're emitting a call instruction.
1519
1520 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1521 emit_data((int) disp, rspec, operand);
1522 }
1523
1524 void Assembler::cdql() {
1525 emit_int8((unsigned char)0x99);
1526 }
1527
1528 void Assembler::cld() {
1529 emit_int8((unsigned char)0xFC);
1530 }
1531
1532 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1533 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1534 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1535 emit_int8(0x0F);
1536 emit_int8(0x40 | cc);
1537 emit_int8((unsigned char)(0xC0 | encode));
1538 }
1539
1540
1541 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1542 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1543 prefix(src, dst);
1544 emit_int8(0x0F);
1545 emit_int8(0x40 | cc);
1546 emit_operand(dst, src);
1547 }
1548
1549 void Assembler::cmpb(Address dst, int imm8) {
1550 InstructionMark im(this);
1551 prefix(dst);
1552 emit_int8((unsigned char)0x80);
1553 emit_operand(rdi, dst, 1);
1554 emit_int8(imm8);
1555 }
1556
1557 void Assembler::cmpl(Address dst, int32_t imm32) {
1558 InstructionMark im(this);
1559 prefix(dst);
1560 emit_int8((unsigned char)0x81);
1561 emit_operand(rdi, dst, 4);
1562 emit_int32(imm32);
1563 }
1564
1565 void Assembler::cmpl(Register dst, int32_t imm32) {
1566 prefix(dst);
1567 emit_arith(0x81, 0xF8, dst, imm32);
1568 }
1569
1570 void Assembler::cmpl(Register dst, Register src) {
1571 (void) prefix_and_encode(dst->encoding(), src->encoding());
1572 emit_arith(0x3B, 0xC0, dst, src);
1573 }
1574
1575 void Assembler::cmpl(Register dst, Address src) {
1576 InstructionMark im(this);
1577 prefix(src, dst);
1578 emit_int8((unsigned char)0x3B);
1579 emit_operand(dst, src);
1580 }
1581
1582 void Assembler::cmpw(Address dst, int imm16) {
1583 InstructionMark im(this);
1584 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1585 emit_int8(0x66);
1586 emit_int8((unsigned char)0x81);
1587 emit_operand(rdi, dst, 2);
1588 emit_int16(imm16);
1589 }
1590
1591 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1592 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1593 // The ZF is set if the compared values were equal, and cleared otherwise.
1594 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1595 InstructionMark im(this);
1596 prefix(adr, reg);
1597 emit_int8(0x0F);
1598 emit_int8((unsigned char)0xB1);
1599 emit_operand(reg, adr);
1600 }
1601
1602 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1603 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1604 // The ZF is set if the compared values were equal, and cleared otherwise.
1605 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1606 InstructionMark im(this);
1607 prefix(adr, reg, true);
1608 emit_int8(0x0F);
1609 emit_int8((unsigned char)0xB0);
1610 emit_operand(reg, adr);
1611 }
1612
1613 void Assembler::comisd(XMMRegister dst, Address src) {
1614 // NOTE: dbx seems to decode this as comiss even though the
1615 // 0x66 is there. Strangly ucomisd comes out correct
1616 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1617 InstructionMark im(this);
1618 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1619 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1620 attributes.set_rex_vex_w_reverted();
1621 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1622 emit_int8(0x2F);
1623 emit_operand(dst, src);
1624 }
1625
1626 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1627 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1628 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1629 attributes.set_rex_vex_w_reverted();
1630 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1631 emit_int8(0x2F);
1632 emit_int8((unsigned char)(0xC0 | encode));
1633 }
1634
1635 void Assembler::comiss(XMMRegister dst, Address src) {
1636 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1637 InstructionMark im(this);
1638 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1639 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1640 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1641 emit_int8(0x2F);
1642 emit_operand(dst, src);
1643 }
1644
1645 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1646 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1647 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1648 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1649 emit_int8(0x2F);
1650 emit_int8((unsigned char)(0xC0 | encode));
1651 }
1652
1653 void Assembler::cpuid() {
1654 emit_int8(0x0F);
1655 emit_int8((unsigned char)0xA2);
1656 }
1657
1658 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1659 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1660 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1661 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1662 //
1663 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1664 //
1665 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1666 //
1667 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1668 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1669 assert(VM_Version::supports_sse4_2(), "");
1670 int8_t w = 0x01;
1671 Prefix p = Prefix_EMPTY;
1672
1673 emit_int8((int8_t)0xF2);
1674 switch (sizeInBytes) {
1675 case 1:
1676 w = 0;
1677 break;
1678 case 2:
1679 case 4:
1680 break;
1681 LP64_ONLY(case 8:)
1682 // This instruction is not valid in 32 bits
1683 // Note:
1684 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1685 //
1686 // Page B - 72 Vol. 2C says
1687 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1688 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1689 // F0!!!
1690 // while 3 - 208 Vol. 2A
1691 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1692 //
1693 // the 0 on a last bit is reserved for a different flavor of this instruction :
1694 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1695 p = REX_W;
1696 break;
1697 default:
1698 assert(0, "Unsupported value for a sizeInBytes argument");
1699 break;
1700 }
1701 LP64_ONLY(prefix(crc, v, p);)
1702 emit_int8((int8_t)0x0F);
1703 emit_int8(0x38);
1704 emit_int8((int8_t)(0xF0 | w));
1705 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1706 }
1707
1708 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1709 assert(VM_Version::supports_sse4_2(), "");
1710 InstructionMark im(this);
1711 int8_t w = 0x01;
1712 Prefix p = Prefix_EMPTY;
1713
1714 emit_int8((int8_t)0xF2);
1715 switch (sizeInBytes) {
1716 case 1:
1717 w = 0;
1718 break;
1719 case 2:
1720 case 4:
1721 break;
1722 LP64_ONLY(case 8:)
1723 // This instruction is not valid in 32 bits
1724 p = REX_W;
1725 break;
1726 default:
1727 assert(0, "Unsupported value for a sizeInBytes argument");
1728 break;
1729 }
1730 LP64_ONLY(prefix(crc, adr, p);)
1731 emit_int8((int8_t)0x0F);
1732 emit_int8(0x38);
1733 emit_int8((int8_t)(0xF0 | w));
1734 emit_operand(crc, adr);
1735 }
1736
1737 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1739 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1740 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1741 emit_int8((unsigned char)0xE6);
1742 emit_int8((unsigned char)(0xC0 | encode));
1743 }
1744
1745 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1747 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1748 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1749 emit_int8(0x5B);
1750 emit_int8((unsigned char)(0xC0 | encode));
1751 }
1752
1753 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1754 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1755 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1756 attributes.set_rex_vex_w_reverted();
1757 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1758 emit_int8(0x5A);
1759 emit_int8((unsigned char)(0xC0 | encode));
1760 }
1761
1762 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1763 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1764 InstructionMark im(this);
1765 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1766 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1767 attributes.set_rex_vex_w_reverted();
1768 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1769 emit_int8(0x5A);
1770 emit_operand(dst, src);
1771 }
1772
1773 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1774 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1776 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1777 emit_int8(0x2A);
1778 emit_int8((unsigned char)(0xC0 | encode));
1779 }
1780
1781 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1783 InstructionMark im(this);
1784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1785 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1786 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1787 emit_int8(0x2A);
1788 emit_operand(dst, src);
1789 }
1790
1791 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1792 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1793 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1794 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1795 emit_int8(0x2A);
1796 emit_int8((unsigned char)(0xC0 | encode));
1797 }
1798
1799 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1800 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1801 InstructionMark im(this);
1802 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1803 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1804 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x2A);
1806 emit_operand(dst, src);
1807 }
1808
1809 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1810 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1811 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1812 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1813 emit_int8(0x2A);
1814 emit_int8((unsigned char)(0xC0 | encode));
1815 }
1816
1817 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1819 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1820 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1821 emit_int8(0x5A);
1822 emit_int8((unsigned char)(0xC0 | encode));
1823 }
1824
1825 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1826 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1827 InstructionMark im(this);
1828 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1829 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1830 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1831 emit_int8(0x5A);
1832 emit_operand(dst, src);
1833 }
1834
1835
1836 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1839 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1840 emit_int8(0x2C);
1841 emit_int8((unsigned char)(0xC0 | encode));
1842 }
1843
1844 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1845 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1846 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1847 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1848 emit_int8(0x2C);
1849 emit_int8((unsigned char)(0xC0 | encode));
1850 }
1851
1852 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1853 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1854 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1855 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1856 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1857 emit_int8((unsigned char)0xE6);
1858 emit_int8((unsigned char)(0xC0 | encode));
1859 }
1860
1861 void Assembler::decl(Address dst) {
1862 // Don't use it directly. Use MacroAssembler::decrement() instead.
1863 InstructionMark im(this);
1864 prefix(dst);
1865 emit_int8((unsigned char)0xFF);
1866 emit_operand(rcx, dst);
1867 }
1868
1869 void Assembler::divsd(XMMRegister dst, Address src) {
1870 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1871 InstructionMark im(this);
1872 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1873 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1874 attributes.set_rex_vex_w_reverted();
1875 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1876 emit_int8(0x5E);
1877 emit_operand(dst, src);
1878 }
1879
1880 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1881 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1882 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1883 attributes.set_rex_vex_w_reverted();
1884 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1885 emit_int8(0x5E);
1886 emit_int8((unsigned char)(0xC0 | encode));
1887 }
1888
1889 void Assembler::divss(XMMRegister dst, Address src) {
1890 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1891 InstructionMark im(this);
1892 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1893 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1894 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1895 emit_int8(0x5E);
1896 emit_operand(dst, src);
1897 }
1898
1899 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1900 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1901 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1902 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1903 emit_int8(0x5E);
1904 emit_int8((unsigned char)(0xC0 | encode));
1905 }
1906
1907 void Assembler::emms() {
1908 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1909 emit_int8(0x0F);
1910 emit_int8(0x77);
1911 }
1912
1913 void Assembler::hlt() {
1914 emit_int8((unsigned char)0xF4);
1915 }
1916
1917 void Assembler::idivl(Register src) {
1918 int encode = prefix_and_encode(src->encoding());
1919 emit_int8((unsigned char)0xF7);
1920 emit_int8((unsigned char)(0xF8 | encode));
1921 }
1922
1923 void Assembler::divl(Register src) { // Unsigned
1924 int encode = prefix_and_encode(src->encoding());
1925 emit_int8((unsigned char)0xF7);
1926 emit_int8((unsigned char)(0xF0 | encode));
1927 }
1928
1929 void Assembler::imull(Register src) {
1930 int encode = prefix_and_encode(src->encoding());
1931 emit_int8((unsigned char)0xF7);
1932 emit_int8((unsigned char)(0xE8 | encode));
1933 }
1934
1935 void Assembler::imull(Register dst, Register src) {
1936 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1937 emit_int8(0x0F);
1938 emit_int8((unsigned char)0xAF);
1939 emit_int8((unsigned char)(0xC0 | encode));
1940 }
1941
1942
1943 void Assembler::imull(Register dst, Register src, int value) {
1944 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1945 if (is8bit(value)) {
1946 emit_int8(0x6B);
1947 emit_int8((unsigned char)(0xC0 | encode));
1948 emit_int8(value & 0xFF);
1949 } else {
1950 emit_int8(0x69);
1951 emit_int8((unsigned char)(0xC0 | encode));
1952 emit_int32(value);
1953 }
1954 }
1955
1956 void Assembler::imull(Register dst, Address src) {
1957 InstructionMark im(this);
1958 prefix(src, dst);
1959 emit_int8(0x0F);
1960 emit_int8((unsigned char) 0xAF);
1961 emit_operand(dst, src);
1962 }
1963
1964
1965 void Assembler::incl(Address dst) {
1966 // Don't use it directly. Use MacroAssembler::increment() instead.
1967 InstructionMark im(this);
1968 prefix(dst);
1969 emit_int8((unsigned char)0xFF);
1970 emit_operand(rax, dst);
1971 }
1972
1973 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1974 InstructionMark im(this);
1975 assert((0 <= cc) && (cc < 16), "illegal cc");
1976 if (L.is_bound()) {
1977 address dst = target(L);
1978 assert(dst != NULL, "jcc most probably wrong");
1979
1980 const int short_size = 2;
1981 const int long_size = 6;
1982 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1983 if (maybe_short && is8bit(offs - short_size)) {
1984 // 0111 tttn #8-bit disp
1985 emit_int8(0x70 | cc);
1986 emit_int8((offs - short_size) & 0xFF);
1987 } else {
1988 // 0000 1111 1000 tttn #32-bit disp
1989 assert(is_simm32(offs - long_size),
1990 "must be 32bit offset (call4)");
1991 emit_int8(0x0F);
1992 emit_int8((unsigned char)(0x80 | cc));
1993 emit_int32(offs - long_size);
1994 }
1995 } else {
1996 // Note: could eliminate cond. jumps to this jump if condition
1997 // is the same however, seems to be rather unlikely case.
1998 // Note: use jccb() if label to be bound is very close to get
1999 // an 8-bit displacement
2000 L.add_patch_at(code(), locator());
2001 emit_int8(0x0F);
2002 emit_int8((unsigned char)(0x80 | cc));
2003 emit_int32(0);
2004 }
2005 }
2006
2007 void Assembler::jccb(Condition cc, Label& L) {
2008 if (L.is_bound()) {
2009 const int short_size = 2;
2010 address entry = target(L);
2011 #ifdef ASSERT
2012 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2013 intptr_t delta = short_branch_delta();
2014 if (delta != 0) {
2015 dist += (dist < 0 ? (-delta) :delta);
2016 }
2017 assert(is8bit(dist), "Dispacement too large for a short jmp");
2018 #endif
2019 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2020 // 0111 tttn #8-bit disp
2021 emit_int8(0x70 | cc);
2022 emit_int8((offs - short_size) & 0xFF);
2023 } else {
2024 InstructionMark im(this);
2025 L.add_patch_at(code(), locator());
2026 emit_int8(0x70 | cc);
2027 emit_int8(0);
2028 }
2029 }
2030
2031 void Assembler::jmp(Address adr) {
2032 InstructionMark im(this);
2033 prefix(adr);
2034 emit_int8((unsigned char)0xFF);
2035 emit_operand(rsp, adr);
2036 }
2037
2038 void Assembler::jmp(Label& L, bool maybe_short) {
2039 if (L.is_bound()) {
2040 address entry = target(L);
2041 assert(entry != NULL, "jmp most probably wrong");
2042 InstructionMark im(this);
2043 const int short_size = 2;
2044 const int long_size = 5;
2045 intptr_t offs = entry - pc();
2046 if (maybe_short && is8bit(offs - short_size)) {
2047 emit_int8((unsigned char)0xEB);
2048 emit_int8((offs - short_size) & 0xFF);
2049 } else {
2050 emit_int8((unsigned char)0xE9);
2051 emit_int32(offs - long_size);
2052 }
2053 } else {
2054 // By default, forward jumps are always 32-bit displacements, since
2055 // we can't yet know where the label will be bound. If you're sure that
2056 // the forward jump will not run beyond 256 bytes, use jmpb to
2057 // force an 8-bit displacement.
2058 InstructionMark im(this);
2059 L.add_patch_at(code(), locator());
2060 emit_int8((unsigned char)0xE9);
2061 emit_int32(0);
2062 }
2063 }
2064
2065 void Assembler::jmp(Register entry) {
2066 int encode = prefix_and_encode(entry->encoding());
2067 emit_int8((unsigned char)0xFF);
2068 emit_int8((unsigned char)(0xE0 | encode));
2069 }
2070
2071 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2072 InstructionMark im(this);
2073 emit_int8((unsigned char)0xE9);
2074 assert(dest != NULL, "must have a target");
2075 intptr_t disp = dest - (pc() + sizeof(int32_t));
2076 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2077 emit_data(disp, rspec.reloc(), call32_operand);
2078 }
2079
2080 void Assembler::jmpb(Label& L) {
2081 if (L.is_bound()) {
2082 const int short_size = 2;
2083 address entry = target(L);
2084 assert(entry != NULL, "jmp most probably wrong");
2085 #ifdef ASSERT
2086 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2087 intptr_t delta = short_branch_delta();
2088 if (delta != 0) {
2089 dist += (dist < 0 ? (-delta) :delta);
2090 }
2091 assert(is8bit(dist), "Dispacement too large for a short jmp");
2092 #endif
2093 intptr_t offs = entry - pc();
2094 emit_int8((unsigned char)0xEB);
2095 emit_int8((offs - short_size) & 0xFF);
2096 } else {
2097 InstructionMark im(this);
2098 L.add_patch_at(code(), locator());
2099 emit_int8((unsigned char)0xEB);
2100 emit_int8(0);
2101 }
2102 }
2103
2104 void Assembler::ldmxcsr( Address src) {
2105 if (UseAVX > 0 ) {
2106 InstructionMark im(this);
2107 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
2108 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2109 emit_int8((unsigned char)0xAE);
2110 emit_operand(as_Register(2), src);
2111 } else {
2112 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2113 InstructionMark im(this);
2114 prefix(src);
2115 emit_int8(0x0F);
2116 emit_int8((unsigned char)0xAE);
2117 emit_operand(as_Register(2), src);
2118 }
2119 }
2120
2121 void Assembler::leal(Register dst, Address src) {
2122 InstructionMark im(this);
2123 #ifdef _LP64
2124 emit_int8(0x67); // addr32
2125 prefix(src, dst);
2126 #endif // LP64
2127 emit_int8((unsigned char)0x8D);
2128 emit_operand(dst, src);
2129 }
2130
2131 void Assembler::lfence() {
2132 emit_int8(0x0F);
2133 emit_int8((unsigned char)0xAE);
2134 emit_int8((unsigned char)0xE8);
2135 }
2136
2137 void Assembler::lock() {
2138 emit_int8((unsigned char)0xF0);
2139 }
2140
2141 void Assembler::lzcntl(Register dst, Register src) {
2142 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2143 emit_int8((unsigned char)0xF3);
2144 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2145 emit_int8(0x0F);
2146 emit_int8((unsigned char)0xBD);
2147 emit_int8((unsigned char)(0xC0 | encode));
2148 }
2149
2150 // Emit mfence instruction
2151 void Assembler::mfence() {
2152 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2153 emit_int8(0x0F);
2154 emit_int8((unsigned char)0xAE);
2155 emit_int8((unsigned char)0xF0);
2156 }
2157
2158 void Assembler::mov(Register dst, Register src) {
2159 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2160 }
2161
2162 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2164 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2165 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2166 attributes.set_rex_vex_w_reverted();
2167 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2168 emit_int8(0x28);
2169 emit_int8((unsigned char)(0xC0 | encode));
2170 }
2171
2172 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2173 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2174 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2175 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2176 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2177 emit_int8(0x28);
2178 emit_int8((unsigned char)(0xC0 | encode));
2179 }
2180
2181 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2182 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2183 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2184 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2185 emit_int8(0x16);
2186 emit_int8((unsigned char)(0xC0 | encode));
2187 }
2188
2189 void Assembler::movb(Register dst, Address src) {
2190 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2191 InstructionMark im(this);
2192 prefix(src, dst, true);
2193 emit_int8((unsigned char)0x8A);
2194 emit_operand(dst, src);
2195 }
2196
2197 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2198 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2199 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2200 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2201 attributes.set_rex_vex_w_reverted();
2202 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2203 emit_int8(0x12);
2204 emit_int8(0xC0 | encode);
2205 }
2206
2207 void Assembler::kmovbl(KRegister dst, Register src) {
2208 assert(VM_Version::supports_avx512dq(), "");
2209 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2210 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2211 emit_int8((unsigned char)0x92);
2212 emit_int8((unsigned char)(0xC0 | encode));
2213 }
2214
2215 void Assembler::kmovbl(Register dst, KRegister src) {
2216 assert(VM_Version::supports_avx512dq(), "");
2217 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2218 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2219 emit_int8((unsigned char)0x93);
2220 emit_int8((unsigned char)(0xC0 | encode));
2221 }
2222
2223 void Assembler::kmovwl(KRegister dst, Register src) {
2224 assert(VM_Version::supports_evex(), "");
2225 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2226 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2227 emit_int8((unsigned char)0x92);
2228 emit_int8((unsigned char)(0xC0 | encode));
2229 }
2230
2231 void Assembler::kmovwl(Register dst, KRegister src) {
2232 assert(VM_Version::supports_evex(), "");
2233 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2234 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2235 emit_int8((unsigned char)0x93);
2236 emit_int8((unsigned char)(0xC0 | encode));
2237 }
2238
2239 void Assembler::kmovwl(KRegister dst, Address src) {
2240 assert(VM_Version::supports_evex(), "");
2241 InstructionMark im(this);
2242 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2243 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2244 emit_int8((unsigned char)0x90);
2245 emit_operand((Register)dst, src);
2246 }
2247
2248 void Assembler::kmovdl(KRegister dst, Register src) {
2249 assert(VM_Version::supports_avx512bw(), "");
2250 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2251 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2252 emit_int8((unsigned char)0x92);
2253 emit_int8((unsigned char)(0xC0 | encode));
2254 }
2255
2256 void Assembler::kmovdl(Register dst, KRegister src) {
2257 assert(VM_Version::supports_avx512bw(), "");
2258 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2259 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2260 emit_int8((unsigned char)0x93);
2261 emit_int8((unsigned char)(0xC0 | encode));
2262 }
2263
2264 void Assembler::kmovql(KRegister dst, KRegister src) {
2265 assert(VM_Version::supports_avx512bw(), "");
2266 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2267 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2268 emit_int8((unsigned char)0x90);
2269 emit_int8((unsigned char)(0xC0 | encode));
2270 }
2271
2272 void Assembler::kmovql(KRegister dst, Address src) {
2273 assert(VM_Version::supports_avx512bw(), "");
2274 InstructionMark im(this);
2275 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2276 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2277 emit_int8((unsigned char)0x90);
2278 emit_operand((Register)dst, src);
2279 }
2280
2281 void Assembler::kmovql(Address dst, KRegister src) {
2282 assert(VM_Version::supports_avx512bw(), "");
2283 InstructionMark im(this);
2284 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2286 emit_int8((unsigned char)0x90);
2287 emit_operand((Register)src, dst);
2288 }
2289
2290 void Assembler::kmovql(KRegister dst, Register src) {
2291 assert(VM_Version::supports_avx512bw(), "");
2292 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2293 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2294 emit_int8((unsigned char)0x92);
2295 emit_int8((unsigned char)(0xC0 | encode));
2296 }
2297
2298 void Assembler::kmovql(Register dst, KRegister src) {
2299 assert(VM_Version::supports_avx512bw(), "");
2300 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2301 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2302 emit_int8((unsigned char)0x93);
2303 emit_int8((unsigned char)(0xC0 | encode));
2304 }
2305
2306 void Assembler::knotwl(KRegister dst, KRegister src) {
2307 assert(VM_Version::supports_evex(), "");
2308 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2309 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2310 emit_int8((unsigned char)0x44);
2311 emit_int8((unsigned char)(0xC0 | encode));
2312 }
2313
2314 // This instruction produces ZF or CF flags
2315 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2316 assert(VM_Version::supports_avx512dq(), "");
2317 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2318 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2319 emit_int8((unsigned char)0x98);
2320 emit_int8((unsigned char)(0xC0 | encode));
2321 }
2322
2323 // This instruction produces ZF or CF flags
2324 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2325 assert(VM_Version::supports_evex(), "");
2326 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2327 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2328 emit_int8((unsigned char)0x98);
2329 emit_int8((unsigned char)(0xC0 | encode));
2330 }
2331
2332 // This instruction produces ZF or CF flags
2333 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2334 assert(VM_Version::supports_avx512bw(), "");
2335 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2336 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2337 emit_int8((unsigned char)0x98);
2338 emit_int8((unsigned char)(0xC0 | encode));
2339 }
2340
2341 // This instruction produces ZF or CF flags
2342 void Assembler::kortestql(KRegister src1, KRegister src2) {
2343 assert(VM_Version::supports_avx512bw(), "");
2344 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2345 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2346 emit_int8((unsigned char)0x98);
2347 emit_int8((unsigned char)(0xC0 | encode));
2348 }
2349
2350 // This instruction produces ZF or CF flags
2351 void Assembler::ktestql(KRegister src1, KRegister src2) {
2352 assert(VM_Version::supports_avx512bw(), "");
2353 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2354 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2355 emit_int8((unsigned char)0x99);
2356 emit_int8((unsigned char)(0xC0 | encode));
2357 }
2358
2359 void Assembler::ktestq(KRegister src1, KRegister src2) {
2360 assert(VM_Version::supports_avx512bw(), "");
2361 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2362 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2363 emit_int8((unsigned char)0x99);
2364 emit_int8((unsigned char)(0xC0 | encode));
2365 }
2366
2367 void Assembler::ktestd(KRegister src1, KRegister src2) {
2368 assert(VM_Version::supports_avx512bw(), "");
2369 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2370 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2371 emit_int8((unsigned char)0x99);
2372 emit_int8((unsigned char)(0xC0 | encode));
2373 }
2374
2375 void Assembler::movb(Address dst, int imm8) {
2376 InstructionMark im(this);
2377 prefix(dst);
2378 emit_int8((unsigned char)0xC6);
2379 emit_operand(rax, dst, 1);
2380 emit_int8(imm8);
2381 }
2382
2383
2384 void Assembler::movb(Address dst, Register src) {
2385 assert(src->has_byte_register(), "must have byte register");
2386 InstructionMark im(this);
2387 prefix(dst, src, true);
2388 emit_int8((unsigned char)0x88);
2389 emit_operand(src, dst);
2390 }
2391
2392 void Assembler::movdl(XMMRegister dst, Register src) {
2393 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2394 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2395 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2396 emit_int8(0x6E);
2397 emit_int8((unsigned char)(0xC0 | encode));
2398 }
2399
2400 void Assembler::movdl(Register dst, XMMRegister src) {
2401 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2402 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2403 // swap src/dst to get correct prefix
2404 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2405 emit_int8(0x7E);
2406 emit_int8((unsigned char)(0xC0 | encode));
2407 }
2408
2409 void Assembler::movdl(XMMRegister dst, Address src) {
2410 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2411 InstructionMark im(this);
2412 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2413 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2414 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2415 emit_int8(0x6E);
2416 emit_operand(dst, src);
2417 }
2418
2419 void Assembler::movdl(Address dst, XMMRegister src) {
2420 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2421 InstructionMark im(this);
2422 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2423 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2424 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2425 emit_int8(0x7E);
2426 emit_operand(src, dst);
2427 }
2428
2429 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2431 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2432 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2433 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2434 emit_int8(0x6F);
2435 emit_int8((unsigned char)(0xC0 | encode));
2436 }
2437
2438 void Assembler::movdqa(XMMRegister dst, Address src) {
2439 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2440 InstructionMark im(this);
2441 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2442 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2443 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2444 emit_int8(0x6F);
2445 emit_operand(dst, src);
2446 }
2447
2448 void Assembler::movdqu(XMMRegister dst, Address src) {
2449 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2450 InstructionMark im(this);
2451 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2452 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2453 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2454 emit_int8(0x6F);
2455 emit_operand(dst, src);
2456 }
2457
2458 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2459 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2460 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2461 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2462 emit_int8(0x6F);
2463 emit_int8((unsigned char)(0xC0 | encode));
2464 }
2465
2466 void Assembler::movdqu(Address dst, XMMRegister src) {
2467 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2468 InstructionMark im(this);
2469 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2470 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2471 attributes.reset_is_clear_context();
2472 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2473 emit_int8(0x7F);
2474 emit_operand(src, dst);
2475 }
2476
2477 // Move Unaligned 256bit Vector
2478 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2479 assert(UseAVX > 0, "");
2480 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2481 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2482 emit_int8(0x6F);
2483 emit_int8((unsigned char)(0xC0 | encode));
2484 }
2485
2486 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2487 assert(UseAVX > 0, "");
2488 InstructionMark im(this);
2489 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2490 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2491 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2492 emit_int8(0x6F);
2493 emit_operand(dst, src);
2494 }
2495
2496 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2497 assert(UseAVX > 0, "");
2498 InstructionMark im(this);
2499 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2500 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2501 attributes.reset_is_clear_context();
2502 // swap src<->dst for encoding
2503 assert(src != xnoreg, "sanity");
2504 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2505 emit_int8(0x7F);
2506 emit_operand(src, dst);
2507 }
2508
2509 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2510 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2511 assert(VM_Version::supports_evex(), "");
2512 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2513 attributes.set_is_evex_instruction();
2514 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2515 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2516 emit_int8(0x6F);
2517 emit_int8((unsigned char)(0xC0 | encode));
2518 }
2519
2520 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2521 assert(VM_Version::supports_evex(), "");
2522 InstructionMark im(this);
2523 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2524 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2525 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2526 attributes.set_is_evex_instruction();
2527 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2528 emit_int8(0x6F);
2529 emit_operand(dst, src);
2530 }
2531
2532 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2533 assert(VM_Version::supports_evex(), "");
2534 assert(src != xnoreg, "sanity");
2535 InstructionMark im(this);
2536 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2537 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2538 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2539 attributes.set_is_evex_instruction();
2540 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2541 emit_int8(0x7F);
2542 emit_operand(src, dst);
2543 }
2544
2545 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2546 assert(VM_Version::supports_avx512vlbw(), "");
2547 assert(is_vector_masking(), ""); // For stub code use only
2548 InstructionMark im(this);
2549 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2550 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2551 attributes.set_embedded_opmask_register_specifier(mask);
2552 attributes.set_is_evex_instruction();
2553 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2554 emit_int8(0x6F);
2555 emit_operand(dst, src);
2556 }
2557
2558 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2559 assert(VM_Version::supports_evex(), "");
2560 InstructionMark im(this);
2561 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2562 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2563 attributes.set_is_evex_instruction();
2564 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2565 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2566 emit_int8(0x6F);
2567 emit_operand(dst, src);
2568 }
2569
2570 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2571 assert(is_vector_masking(), "");
2572 assert(VM_Version::supports_avx512vlbw(), "");
2573 InstructionMark im(this);
2574 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2575 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2576 attributes.set_embedded_opmask_register_specifier(mask);
2577 attributes.set_is_evex_instruction();
2578 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2579 emit_int8(0x6F);
2580 emit_operand(dst, src);
2581 }
2582
2583 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2584 assert(VM_Version::supports_evex(), "");
2585 assert(src != xnoreg, "sanity");
2586 InstructionMark im(this);
2587 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2588 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2589 attributes.set_is_evex_instruction();
2590 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2591 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2592 emit_int8(0x7F);
2593 emit_operand(src, dst);
2594 }
2595
2596 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2597 assert(VM_Version::supports_avx512vlbw(), "");
2598 assert(src != xnoreg, "sanity");
2599 InstructionMark im(this);
2600 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2601 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2602 attributes.reset_is_clear_context();
2603 attributes.set_embedded_opmask_register_specifier(mask);
2604 attributes.set_is_evex_instruction();
2605 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2606 emit_int8(0x7F);
2607 emit_operand(src, dst);
2608 }
2609
2610 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2611 assert(VM_Version::supports_evex(), "");
2612 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2613 attributes.set_is_evex_instruction();
2614 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2615 emit_int8(0x6F);
2616 emit_int8((unsigned char)(0xC0 | encode));
2617 }
2618
2619 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2620 assert(VM_Version::supports_evex(), "");
2621 InstructionMark im(this);
2622 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2623 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2624 attributes.set_is_evex_instruction();
2625 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2626 emit_int8(0x6F);
2627 emit_operand(dst, src);
2628 }
2629
2630 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2631 assert(VM_Version::supports_evex(), "");
2632 assert(src != xnoreg, "sanity");
2633 InstructionMark im(this);
2634 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2635 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2636 attributes.reset_is_clear_context();
2637 attributes.set_is_evex_instruction();
2638 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2639 emit_int8(0x7F);
2640 emit_operand(src, dst);
2641 }
2642
2643 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2644 assert(VM_Version::supports_evex(), "");
2645 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2646 attributes.set_is_evex_instruction();
2647 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2648 emit_int8(0x6F);
2649 emit_int8((unsigned char)(0xC0 | encode));
2650 }
2651
2652 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2653 assert(VM_Version::supports_evex(), "");
2654 InstructionMark im(this);
2655 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2656 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2657 attributes.set_is_evex_instruction();
2658 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2659 emit_int8(0x6F);
2660 emit_operand(dst, src);
2661 }
2662
2663 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2664 assert(VM_Version::supports_evex(), "");
2665 assert(src != xnoreg, "sanity");
2666 InstructionMark im(this);
2667 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2668 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2669 attributes.reset_is_clear_context();
2670 attributes.set_is_evex_instruction();
2671 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2672 emit_int8(0x7F);
2673 emit_operand(src, dst);
2674 }
2675
2676 // Uses zero extension on 64bit
2677
2678 void Assembler::movl(Register dst, int32_t imm32) {
2679 int encode = prefix_and_encode(dst->encoding());
2680 emit_int8((unsigned char)(0xB8 | encode));
2681 emit_int32(imm32);
2682 }
2683
2684 void Assembler::movl(Register dst, Register src) {
2685 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2686 emit_int8((unsigned char)0x8B);
2687 emit_int8((unsigned char)(0xC0 | encode));
2688 }
2689
2690 void Assembler::movl(Register dst, Address src) {
2691 InstructionMark im(this);
2692 prefix(src, dst);
2693 emit_int8((unsigned char)0x8B);
2694 emit_operand(dst, src);
2695 }
2696
2697 void Assembler::movl(Address dst, int32_t imm32) {
2698 InstructionMark im(this);
2699 prefix(dst);
2700 emit_int8((unsigned char)0xC7);
2701 emit_operand(rax, dst, 4);
2702 emit_int32(imm32);
2703 }
2704
2705 void Assembler::movl(Address dst, Register src) {
2706 InstructionMark im(this);
2707 prefix(dst, src);
2708 emit_int8((unsigned char)0x89);
2709 emit_operand(src, dst);
2710 }
2711
2712 // New cpus require to use movsd and movss to avoid partial register stall
2713 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2714 // The selection is done in MacroAssembler::movdbl() and movflt().
2715 void Assembler::movlpd(XMMRegister dst, Address src) {
2716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2717 InstructionMark im(this);
2718 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2719 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2720 attributes.set_rex_vex_w_reverted();
2721 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2722 emit_int8(0x12);
2723 emit_operand(dst, src);
2724 }
2725
2726 void Assembler::movq( MMXRegister dst, Address src ) {
2727 assert( VM_Version::supports_mmx(), "" );
2728 emit_int8(0x0F);
2729 emit_int8(0x6F);
2730 emit_operand(dst, src);
2731 }
2732
2733 void Assembler::movq( Address dst, MMXRegister src ) {
2734 assert( VM_Version::supports_mmx(), "" );
2735 emit_int8(0x0F);
2736 emit_int8(0x7F);
2737 // workaround gcc (3.2.1-7a) bug
2738 // In that version of gcc with only an emit_operand(MMX, Address)
2739 // gcc will tail jump and try and reverse the parameters completely
2740 // obliterating dst in the process. By having a version available
2741 // that doesn't need to swap the args at the tail jump the bug is
2742 // avoided.
2743 emit_operand(dst, src);
2744 }
2745
2746 void Assembler::movq(XMMRegister dst, Address src) {
2747 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2748 InstructionMark im(this);
2749 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2750 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2751 attributes.set_rex_vex_w_reverted();
2752 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2753 emit_int8(0x7E);
2754 emit_operand(dst, src);
2755 }
2756
2757 void Assembler::movq(Address dst, XMMRegister src) {
2758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2759 InstructionMark im(this);
2760 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2761 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2762 attributes.set_rex_vex_w_reverted();
2763 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2764 emit_int8((unsigned char)0xD6);
2765 emit_operand(src, dst);
2766 }
2767
2768 void Assembler::movsbl(Register dst, Address src) { // movsxb
2769 InstructionMark im(this);
2770 prefix(src, dst);
2771 emit_int8(0x0F);
2772 emit_int8((unsigned char)0xBE);
2773 emit_operand(dst, src);
2774 }
2775
2776 void Assembler::movsbl(Register dst, Register src) { // movsxb
2777 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2778 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2779 emit_int8(0x0F);
2780 emit_int8((unsigned char)0xBE);
2781 emit_int8((unsigned char)(0xC0 | encode));
2782 }
2783
2784 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2785 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2786 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2787 attributes.set_rex_vex_w_reverted();
2788 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2789 emit_int8(0x10);
2790 emit_int8((unsigned char)(0xC0 | encode));
2791 }
2792
2793 void Assembler::movsd(XMMRegister dst, Address src) {
2794 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2795 InstructionMark im(this);
2796 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2797 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2798 attributes.set_rex_vex_w_reverted();
2799 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2800 emit_int8(0x10);
2801 emit_operand(dst, src);
2802 }
2803
2804 void Assembler::movsd(Address dst, XMMRegister src) {
2805 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2806 InstructionMark im(this);
2807 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2808 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2809 attributes.reset_is_clear_context();
2810 attributes.set_rex_vex_w_reverted();
2811 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2812 emit_int8(0x11);
2813 emit_operand(src, dst);
2814 }
2815
2816 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2817 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2818 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2819 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2820 emit_int8(0x10);
2821 emit_int8((unsigned char)(0xC0 | encode));
2822 }
2823
2824 void Assembler::movss(XMMRegister dst, Address src) {
2825 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2826 InstructionMark im(this);
2827 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2828 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2829 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2830 emit_int8(0x10);
2831 emit_operand(dst, src);
2832 }
2833
2834 void Assembler::movss(Address dst, XMMRegister src) {
2835 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2836 InstructionMark im(this);
2837 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2838 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2839 attributes.reset_is_clear_context();
2840 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2841 emit_int8(0x11);
2842 emit_operand(src, dst);
2843 }
2844
2845 void Assembler::movswl(Register dst, Address src) { // movsxw
2846 InstructionMark im(this);
2847 prefix(src, dst);
2848 emit_int8(0x0F);
2849 emit_int8((unsigned char)0xBF);
2850 emit_operand(dst, src);
2851 }
2852
2853 void Assembler::movswl(Register dst, Register src) { // movsxw
2854 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2855 emit_int8(0x0F);
2856 emit_int8((unsigned char)0xBF);
2857 emit_int8((unsigned char)(0xC0 | encode));
2858 }
2859
2860 void Assembler::movw(Address dst, int imm16) {
2861 InstructionMark im(this);
2862
2863 emit_int8(0x66); // switch to 16-bit mode
2864 prefix(dst);
2865 emit_int8((unsigned char)0xC7);
2866 emit_operand(rax, dst, 2);
2867 emit_int16(imm16);
2868 }
2869
2870 void Assembler::movw(Register dst, Address src) {
2871 InstructionMark im(this);
2872 emit_int8(0x66);
2873 prefix(src, dst);
2874 emit_int8((unsigned char)0x8B);
2875 emit_operand(dst, src);
2876 }
2877
2878 void Assembler::movw(Address dst, Register src) {
2879 InstructionMark im(this);
2880 emit_int8(0x66);
2881 prefix(dst, src);
2882 emit_int8((unsigned char)0x89);
2883 emit_operand(src, dst);
2884 }
2885
2886 void Assembler::movzbl(Register dst, Address src) { // movzxb
2887 InstructionMark im(this);
2888 prefix(src, dst);
2889 emit_int8(0x0F);
2890 emit_int8((unsigned char)0xB6);
2891 emit_operand(dst, src);
2892 }
2893
2894 void Assembler::movzbl(Register dst, Register src) { // movzxb
2895 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2896 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2897 emit_int8(0x0F);
2898 emit_int8((unsigned char)0xB6);
2899 emit_int8(0xC0 | encode);
2900 }
2901
2902 void Assembler::movzwl(Register dst, Address src) { // movzxw
2903 InstructionMark im(this);
2904 prefix(src, dst);
2905 emit_int8(0x0F);
2906 emit_int8((unsigned char)0xB7);
2907 emit_operand(dst, src);
2908 }
2909
2910 void Assembler::movzwl(Register dst, Register src) { // movzxw
2911 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2912 emit_int8(0x0F);
2913 emit_int8((unsigned char)0xB7);
2914 emit_int8(0xC0 | encode);
2915 }
2916
2917 void Assembler::mull(Address src) {
2918 InstructionMark im(this);
2919 prefix(src);
2920 emit_int8((unsigned char)0xF7);
2921 emit_operand(rsp, src);
2922 }
2923
2924 void Assembler::mull(Register src) {
2925 int encode = prefix_and_encode(src->encoding());
2926 emit_int8((unsigned char)0xF7);
2927 emit_int8((unsigned char)(0xE0 | encode));
2928 }
2929
2930 void Assembler::mulsd(XMMRegister dst, Address src) {
2931 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2932 InstructionMark im(this);
2933 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2934 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2935 attributes.set_rex_vex_w_reverted();
2936 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2937 emit_int8(0x59);
2938 emit_operand(dst, src);
2939 }
2940
2941 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2942 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2943 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2944 attributes.set_rex_vex_w_reverted();
2945 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2946 emit_int8(0x59);
2947 emit_int8((unsigned char)(0xC0 | encode));
2948 }
2949
2950 void Assembler::mulss(XMMRegister dst, Address src) {
2951 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2952 InstructionMark im(this);
2953 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2954 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2955 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2956 emit_int8(0x59);
2957 emit_operand(dst, src);
2958 }
2959
2960 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2961 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2962 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2963 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2964 emit_int8(0x59);
2965 emit_int8((unsigned char)(0xC0 | encode));
2966 }
2967
2968 void Assembler::negl(Register dst) {
2969 int encode = prefix_and_encode(dst->encoding());
2970 emit_int8((unsigned char)0xF7);
2971 emit_int8((unsigned char)(0xD8 | encode));
2972 }
2973
2974 void Assembler::nop(int i) {
2975 #ifdef ASSERT
2976 assert(i > 0, " ");
2977 // The fancy nops aren't currently recognized by debuggers making it a
2978 // pain to disassemble code while debugging. If asserts are on clearly
2979 // speed is not an issue so simply use the single byte traditional nop
2980 // to do alignment.
2981
2982 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2983 return;
2984
2985 #endif // ASSERT
2986
2987 if (UseAddressNop && VM_Version::is_intel()) {
2988 //
2989 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2990 // 1: 0x90
2991 // 2: 0x66 0x90
2992 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2993 // 4: 0x0F 0x1F 0x40 0x00
2994 // 5: 0x0F 0x1F 0x44 0x00 0x00
2995 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2996 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2997 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2998 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2999 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3000 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3001
3002 // The rest coding is Intel specific - don't use consecutive address nops
3003
3004 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3005 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3006 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3007 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3008
3009 while(i >= 15) {
3010 // For Intel don't generate consecutive addess nops (mix with regular nops)
3011 i -= 15;
3012 emit_int8(0x66); // size prefix
3013 emit_int8(0x66); // size prefix
3014 emit_int8(0x66); // size prefix
3015 addr_nop_8();
3016 emit_int8(0x66); // size prefix
3017 emit_int8(0x66); // size prefix
3018 emit_int8(0x66); // size prefix
3019 emit_int8((unsigned char)0x90);
3020 // nop
3021 }
3022 switch (i) {
3023 case 14:
3024 emit_int8(0x66); // size prefix
3025 case 13:
3026 emit_int8(0x66); // size prefix
3027 case 12:
3028 addr_nop_8();
3029 emit_int8(0x66); // size prefix
3030 emit_int8(0x66); // size prefix
3031 emit_int8(0x66); // size prefix
3032 emit_int8((unsigned char)0x90);
3033 // nop
3034 break;
3035 case 11:
3036 emit_int8(0x66); // size prefix
3037 case 10:
3038 emit_int8(0x66); // size prefix
3039 case 9:
3040 emit_int8(0x66); // size prefix
3041 case 8:
3042 addr_nop_8();
3043 break;
3044 case 7:
3045 addr_nop_7();
3046 break;
3047 case 6:
3048 emit_int8(0x66); // size prefix
3049 case 5:
3050 addr_nop_5();
3051 break;
3052 case 4:
3053 addr_nop_4();
3054 break;
3055 case 3:
3056 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3057 emit_int8(0x66); // size prefix
3058 case 2:
3059 emit_int8(0x66); // size prefix
3060 case 1:
3061 emit_int8((unsigned char)0x90);
3062 // nop
3063 break;
3064 default:
3065 assert(i == 0, " ");
3066 }
3067 return;
3068 }
3069 if (UseAddressNop && VM_Version::is_amd()) {
3070 //
3071 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3072 // 1: 0x90
3073 // 2: 0x66 0x90
3074 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3075 // 4: 0x0F 0x1F 0x40 0x00
3076 // 5: 0x0F 0x1F 0x44 0x00 0x00
3077 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3078 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3079 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3080 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3081 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3082 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3083
3084 // The rest coding is AMD specific - use consecutive address nops
3085
3086 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3087 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3088 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3089 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3090 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3091 // Size prefixes (0x66) are added for larger sizes
3092
3093 while(i >= 22) {
3094 i -= 11;
3095 emit_int8(0x66); // size prefix
3096 emit_int8(0x66); // size prefix
3097 emit_int8(0x66); // size prefix
3098 addr_nop_8();
3099 }
3100 // Generate first nop for size between 21-12
3101 switch (i) {
3102 case 21:
3103 i -= 1;
3104 emit_int8(0x66); // size prefix
3105 case 20:
3106 case 19:
3107 i -= 1;
3108 emit_int8(0x66); // size prefix
3109 case 18:
3110 case 17:
3111 i -= 1;
3112 emit_int8(0x66); // size prefix
3113 case 16:
3114 case 15:
3115 i -= 8;
3116 addr_nop_8();
3117 break;
3118 case 14:
3119 case 13:
3120 i -= 7;
3121 addr_nop_7();
3122 break;
3123 case 12:
3124 i -= 6;
3125 emit_int8(0x66); // size prefix
3126 addr_nop_5();
3127 break;
3128 default:
3129 assert(i < 12, " ");
3130 }
3131
3132 // Generate second nop for size between 11-1
3133 switch (i) {
3134 case 11:
3135 emit_int8(0x66); // size prefix
3136 case 10:
3137 emit_int8(0x66); // size prefix
3138 case 9:
3139 emit_int8(0x66); // size prefix
3140 case 8:
3141 addr_nop_8();
3142 break;
3143 case 7:
3144 addr_nop_7();
3145 break;
3146 case 6:
3147 emit_int8(0x66); // size prefix
3148 case 5:
3149 addr_nop_5();
3150 break;
3151 case 4:
3152 addr_nop_4();
3153 break;
3154 case 3:
3155 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3156 emit_int8(0x66); // size prefix
3157 case 2:
3158 emit_int8(0x66); // size prefix
3159 case 1:
3160 emit_int8((unsigned char)0x90);
3161 // nop
3162 break;
3163 default:
3164 assert(i == 0, " ");
3165 }
3166 return;
3167 }
3168
3169 // Using nops with size prefixes "0x66 0x90".
3170 // From AMD Optimization Guide:
3171 // 1: 0x90
3172 // 2: 0x66 0x90
3173 // 3: 0x66 0x66 0x90
3174 // 4: 0x66 0x66 0x66 0x90
3175 // 5: 0x66 0x66 0x90 0x66 0x90
3176 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3177 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3178 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3179 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3180 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3181 //
3182 while(i > 12) {
3183 i -= 4;
3184 emit_int8(0x66); // size prefix
3185 emit_int8(0x66);
3186 emit_int8(0x66);
3187 emit_int8((unsigned char)0x90);
3188 // nop
3189 }
3190 // 1 - 12 nops
3191 if(i > 8) {
3192 if(i > 9) {
3193 i -= 1;
3194 emit_int8(0x66);
3195 }
3196 i -= 3;
3197 emit_int8(0x66);
3198 emit_int8(0x66);
3199 emit_int8((unsigned char)0x90);
3200 }
3201 // 1 - 8 nops
3202 if(i > 4) {
3203 if(i > 6) {
3204 i -= 1;
3205 emit_int8(0x66);
3206 }
3207 i -= 3;
3208 emit_int8(0x66);
3209 emit_int8(0x66);
3210 emit_int8((unsigned char)0x90);
3211 }
3212 switch (i) {
3213 case 4:
3214 emit_int8(0x66);
3215 case 3:
3216 emit_int8(0x66);
3217 case 2:
3218 emit_int8(0x66);
3219 case 1:
3220 emit_int8((unsigned char)0x90);
3221 break;
3222 default:
3223 assert(i == 0, " ");
3224 }
3225 }
3226
3227 void Assembler::notl(Register dst) {
3228 int encode = prefix_and_encode(dst->encoding());
3229 emit_int8((unsigned char)0xF7);
3230 emit_int8((unsigned char)(0xD0 | encode));
3231 }
3232
3233 void Assembler::orl(Address dst, int32_t imm32) {
3234 InstructionMark im(this);
3235 prefix(dst);
3236 emit_arith_operand(0x81, rcx, dst, imm32);
3237 }
3238
3239 void Assembler::orl(Register dst, int32_t imm32) {
3240 prefix(dst);
3241 emit_arith(0x81, 0xC8, dst, imm32);
3242 }
3243
3244 void Assembler::orl(Register dst, Address src) {
3245 InstructionMark im(this);
3246 prefix(src, dst);
3247 emit_int8(0x0B);
3248 emit_operand(dst, src);
3249 }
3250
3251 void Assembler::orl(Register dst, Register src) {
3252 (void) prefix_and_encode(dst->encoding(), src->encoding());
3253 emit_arith(0x0B, 0xC0, dst, src);
3254 }
3255
3256 void Assembler::orl(Address dst, Register src) {
3257 InstructionMark im(this);
3258 prefix(dst, src);
3259 emit_int8(0x09);
3260 emit_operand(src, dst);
3261 }
3262
3263 void Assembler::packuswb(XMMRegister dst, Address src) {
3264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3265 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3266 InstructionMark im(this);
3267 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3268 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3269 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3270 emit_int8(0x67);
3271 emit_operand(dst, src);
3272 }
3273
3274 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3275 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3276 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3277 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3278 emit_int8(0x67);
3279 emit_int8((unsigned char)(0xC0 | encode));
3280 }
3281
3282 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3283 assert(UseAVX > 0, "some form of AVX must be enabled");
3284 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3285 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3286 emit_int8(0x67);
3287 emit_int8((unsigned char)(0xC0 | encode));
3288 }
3289
3290 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3291 assert(VM_Version::supports_avx2(), "");
3292 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3293 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3294 emit_int8(0x00);
3295 emit_int8(0xC0 | encode);
3296 emit_int8(imm8);
3297 }
3298
3299 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3300 assert(VM_Version::supports_avx2(), "");
3301 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3302 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3303 emit_int8(0x46);
3304 emit_int8(0xC0 | encode);
3305 emit_int8(imm8);
3306 }
3307
3308 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3309 assert(VM_Version::supports_avx(), "");
3310 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3311 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3312 emit_int8(0x06);
3313 emit_int8(0xC0 | encode);
3314 emit_int8(imm8);
3315 }
3316
3317
3318 void Assembler::pause() {
3319 emit_int8((unsigned char)0xF3);
3320 emit_int8((unsigned char)0x90);
3321 }
3322
3323 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3324 assert(VM_Version::supports_sse4_2(), "");
3325 InstructionMark im(this);
3326 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3327 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3328 emit_int8(0x61);
3329 emit_operand(dst, src);
3330 emit_int8(imm8);
3331 }
3332
3333 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3334 assert(VM_Version::supports_sse4_2(), "");
3335 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3336 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3337 emit_int8(0x61);
3338 emit_int8((unsigned char)(0xC0 | encode));
3339 emit_int8(imm8);
3340 }
3341
3342 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3343 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3344 assert(VM_Version::supports_sse2(), "");
3345 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3346 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3347 emit_int8(0x74);
3348 emit_int8((unsigned char)(0xC0 | encode));
3349 }
3350
3351 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3352 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3353 assert(VM_Version::supports_avx(), "");
3354 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3355 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3356 emit_int8(0x74);
3357 emit_int8((unsigned char)(0xC0 | encode));
3358 }
3359
3360 // In this context, kdst is written the mask used to process the equal components
3361 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3362 assert(VM_Version::supports_avx512bw(), "");
3363 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3364 attributes.set_is_evex_instruction();
3365 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3366 emit_int8(0x74);
3367 emit_int8((unsigned char)(0xC0 | encode));
3368 }
3369
3370 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3371 assert(VM_Version::supports_avx512vlbw(), "");
3372 InstructionMark im(this);
3373 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3374 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3375 attributes.set_is_evex_instruction();
3376 int dst_enc = kdst->encoding();
3377 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3378 emit_int8(0x64);
3379 emit_operand(as_Register(dst_enc), src);
3380 }
3381
3382 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3383 assert(is_vector_masking(), "");
3384 assert(VM_Version::supports_avx512vlbw(), "");
3385 InstructionMark im(this);
3386 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3387 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3388 attributes.reset_is_clear_context();
3389 attributes.set_embedded_opmask_register_specifier(mask);
3390 attributes.set_is_evex_instruction();
3391 int dst_enc = kdst->encoding();
3392 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3393 emit_int8(0x64);
3394 emit_operand(as_Register(dst_enc), src);
3395 }
3396
3397 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3398 assert(VM_Version::supports_avx512vlbw(), "");
3399 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3400 attributes.set_is_evex_instruction();
3401 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3402 emit_int8(0x3E);
3403 emit_int8((unsigned char)(0xC0 | encode));
3404 emit_int8(vcc);
3405 }
3406
3407 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3408 assert(is_vector_masking(), "");
3409 assert(VM_Version::supports_avx512vlbw(), "");
3410 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3411 attributes.reset_is_clear_context();
3412 attributes.set_embedded_opmask_register_specifier(mask);
3413 attributes.set_is_evex_instruction();
3414 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3415 emit_int8(0x3E);
3416 emit_int8((unsigned char)(0xC0 | encode));
3417 emit_int8(vcc);
3418 }
3419
3420 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3421 assert(VM_Version::supports_avx512vlbw(), "");
3422 InstructionMark im(this);
3423 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3424 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3425 attributes.set_is_evex_instruction();
3426 int dst_enc = kdst->encoding();
3427 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3428 emit_int8(0x3E);
3429 emit_operand(as_Register(dst_enc), src);
3430 emit_int8(vcc);
3431 }
3432
3433 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3434 assert(VM_Version::supports_avx512bw(), "");
3435 InstructionMark im(this);
3436 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3437 attributes.set_is_evex_instruction();
3438 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3439 int dst_enc = kdst->encoding();
3440 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3441 emit_int8(0x74);
3442 emit_operand(as_Register(dst_enc), src);
3443 }
3444
3445 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3446 assert(VM_Version::supports_avx512vlbw(), "");
3447 assert(is_vector_masking(), ""); // For stub code use only
3448 InstructionMark im(this);
3449 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
3450 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3451 attributes.reset_is_clear_context();
3452 attributes.set_embedded_opmask_register_specifier(mask);
3453 attributes.set_is_evex_instruction();
3454 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3455 emit_int8(0x74);
3456 emit_operand(as_Register(kdst->encoding()), src);
3457 }
3458
3459 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3460 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3461 assert(VM_Version::supports_sse2(), "");
3462 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3463 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3464 emit_int8(0x75);
3465 emit_int8((unsigned char)(0xC0 | encode));
3466 }
3467
3468 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3469 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3470 assert(VM_Version::supports_avx(), "");
3471 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3472 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3473 emit_int8(0x75);
3474 emit_int8((unsigned char)(0xC0 | encode));
3475 }
3476
3477 // In this context, kdst is written the mask used to process the equal components
3478 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3479 assert(VM_Version::supports_avx512bw(), "");
3480 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3481 attributes.set_is_evex_instruction();
3482 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3483 emit_int8(0x75);
3484 emit_int8((unsigned char)(0xC0 | encode));
3485 }
3486
3487 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3488 assert(VM_Version::supports_avx512bw(), "");
3489 InstructionMark im(this);
3490 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3491 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3492 attributes.set_is_evex_instruction();
3493 int dst_enc = kdst->encoding();
3494 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3495 emit_int8(0x75);
3496 emit_operand(as_Register(dst_enc), src);
3497 }
3498
3499 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3500 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3501 assert(VM_Version::supports_sse2(), "");
3502 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3503 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3504 emit_int8(0x76);
3505 emit_int8((unsigned char)(0xC0 | encode));
3506 }
3507
3508 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3509 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3510 assert(VM_Version::supports_avx(), "");
3511 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3512 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3513 emit_int8(0x76);
3514 emit_int8((unsigned char)(0xC0 | encode));
3515 }
3516
3517 // In this context, kdst is written the mask used to process the equal components
3518 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3519 assert(VM_Version::supports_evex(), "");
3520 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3521 attributes.set_is_evex_instruction();
3522 attributes.reset_is_clear_context();
3523 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3524 emit_int8(0x76);
3525 emit_int8((unsigned char)(0xC0 | encode));
3526 }
3527
3528 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3529 assert(VM_Version::supports_evex(), "");
3530 InstructionMark im(this);
3531 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3532 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3533 attributes.reset_is_clear_context();
3534 attributes.set_is_evex_instruction();
3535 int dst_enc = kdst->encoding();
3536 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3537 emit_int8(0x76);
3538 emit_operand(as_Register(dst_enc), src);
3539 }
3540
3541 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3542 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3543 assert(VM_Version::supports_sse4_1(), "");
3544 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3545 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3546 emit_int8(0x29);
3547 emit_int8((unsigned char)(0xC0 | encode));
3548 }
3549
3550 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3551 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3552 assert(VM_Version::supports_avx(), "");
3553 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3554 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3555 emit_int8(0x29);
3556 emit_int8((unsigned char)(0xC0 | encode));
3557 }
3558
3559 // In this context, kdst is written the mask used to process the equal components
3560 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3561 assert(VM_Version::supports_evex(), "");
3562 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3563 attributes.reset_is_clear_context();
3564 attributes.set_is_evex_instruction();
3565 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3566 emit_int8(0x29);
3567 emit_int8((unsigned char)(0xC0 | encode));
3568 }
3569
3570 // In this context, kdst is written the mask used to process the equal components
3571 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3572 assert(VM_Version::supports_evex(), "");
3573 InstructionMark im(this);
3574 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3575 attributes.reset_is_clear_context();
3576 attributes.set_is_evex_instruction();
3577 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3578 int dst_enc = kdst->encoding();
3579 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3580 emit_int8(0x29);
3581 emit_operand(as_Register(dst_enc), src);
3582 }
3583
3584 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3585 assert(VM_Version::supports_sse2(), "");
3586 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3587 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3588 emit_int8((unsigned char)0xD7);
3589 emit_int8((unsigned char)(0xC0 | encode));
3590 }
3591
3592 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3593 assert(VM_Version::supports_avx2(), "");
3594 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3595 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3596 emit_int8((unsigned char)0xD7);
3597 emit_int8((unsigned char)(0xC0 | encode));
3598 }
3599
3600 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3601 assert(VM_Version::supports_sse4_1(), "");
3602 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3603 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3604 emit_int8(0x16);
3605 emit_int8((unsigned char)(0xC0 | encode));
3606 emit_int8(imm8);
3607 }
3608
3609 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3610 assert(VM_Version::supports_sse4_1(), "");
3611 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3612 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3613 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3614 emit_int8(0x16);
3615 emit_operand(src, dst);
3616 emit_int8(imm8);
3617 }
3618
3619 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3620 assert(VM_Version::supports_sse4_1(), "");
3621 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3622 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3623 emit_int8(0x16);
3624 emit_int8((unsigned char)(0xC0 | encode));
3625 emit_int8(imm8);
3626 }
3627
3628 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3629 assert(VM_Version::supports_sse4_1(), "");
3630 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3631 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3632 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3633 emit_int8(0x16);
3634 emit_operand(src, dst);
3635 emit_int8(imm8);
3636 }
3637
3638 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3639 assert(VM_Version::supports_sse2(), "");
3640 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3641 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3642 emit_int8((unsigned char)0xC5);
3643 emit_int8((unsigned char)(0xC0 | encode));
3644 emit_int8(imm8);
3645 }
3646
3647 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3648 assert(VM_Version::supports_sse4_1(), "");
3649 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3650 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3651 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3652 emit_int8((unsigned char)0x15);
3653 emit_operand(src, dst);
3654 emit_int8(imm8);
3655 }
3656
3657 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3658 assert(VM_Version::supports_sse4_1(), "");
3659 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3660 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3661 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3662 emit_int8(0x14);
3663 emit_operand(src, dst);
3664 emit_int8(imm8);
3665 }
3666
3667 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3668 assert(VM_Version::supports_sse4_1(), "");
3669 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3670 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3671 emit_int8(0x22);
3672 emit_int8((unsigned char)(0xC0 | encode));
3673 emit_int8(imm8);
3674 }
3675
3676 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3677 assert(VM_Version::supports_sse4_1(), "");
3678 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3679 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3680 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3681 emit_int8(0x22);
3682 emit_operand(dst,src);
3683 emit_int8(imm8);
3684 }
3685
3686 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3687 assert(VM_Version::supports_sse4_1(), "");
3688 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3689 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3690 emit_int8(0x22);
3691 emit_int8((unsigned char)(0xC0 | encode));
3692 emit_int8(imm8);
3693 }
3694
3695 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3696 assert(VM_Version::supports_sse4_1(), "");
3697 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3698 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3699 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3700 emit_int8(0x22);
3701 emit_operand(dst, src);
3702 emit_int8(imm8);
3703 }
3704
3705 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3706 assert(VM_Version::supports_sse2(), "");
3707 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3708 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3709 emit_int8((unsigned char)0xC4);
3710 emit_int8((unsigned char)(0xC0 | encode));
3711 emit_int8(imm8);
3712 }
3713
3714 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3715 assert(VM_Version::supports_sse2(), "");
3716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3717 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3718 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3719 emit_int8((unsigned char)0xC4);
3720 emit_operand(dst, src);
3721 emit_int8(imm8);
3722 }
3723
3724 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3725 assert(VM_Version::supports_sse4_1(), "");
3726 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3727 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3728 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3729 emit_int8(0x20);
3730 emit_operand(dst, src);
3731 emit_int8(imm8);
3732 }
3733
3734 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3735 assert(VM_Version::supports_sse4_1(), "");
3736 InstructionMark im(this);
3737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3738 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3739 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3740 emit_int8(0x30);
3741 emit_operand(dst, src);
3742 }
3743
3744 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3745 assert(VM_Version::supports_sse4_1(), "");
3746 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3747 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3748 emit_int8(0x30);
3749 emit_int8((unsigned char)(0xC0 | encode));
3750 }
3751
3752 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3753 assert(VM_Version::supports_avx(), "");
3754 InstructionMark im(this);
3755 assert(dst != xnoreg, "sanity");
3756 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3757 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3758 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3759 emit_int8(0x30);
3760 emit_operand(dst, src);
3761 }
3762
3763 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3764 assert(is_vector_masking(), "");
3765 assert(VM_Version::supports_avx512vlbw(), "");
3766 assert(dst != xnoreg, "sanity");
3767 InstructionMark im(this);
3768 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3769 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3770 attributes.set_embedded_opmask_register_specifier(mask);
3771 attributes.set_is_evex_instruction();
3772 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3773 emit_int8(0x30);
3774 emit_operand(dst, src);
3775 }
3776
3777 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3778 assert(VM_Version::supports_avx512vlbw(), "");
3779 assert(src != xnoreg, "sanity");
3780 InstructionMark im(this);
3781 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3782 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3783 attributes.set_is_evex_instruction();
3784 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3785 emit_int8(0x30);
3786 emit_operand(src, dst);
3787 }
3788
3789 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
3790 assert(is_vector_masking(), "");
3791 assert(VM_Version::supports_avx512vlbw(), "");
3792 assert(src != xnoreg, "sanity");
3793 InstructionMark im(this);
3794 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3795 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3796 attributes.reset_is_clear_context();
3797 attributes.set_embedded_opmask_register_specifier(mask);
3798 attributes.set_is_evex_instruction();
3799 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3800 emit_int8(0x30);
3801 emit_operand(src, dst);
3802 }
3803
3804 // generic
3805 void Assembler::pop(Register dst) {
3806 int encode = prefix_and_encode(dst->encoding());
3807 emit_int8(0x58 | encode);
3808 }
3809
3810 void Assembler::popcntl(Register dst, Address src) {
3811 assert(VM_Version::supports_popcnt(), "must support");
3812 InstructionMark im(this);
3813 emit_int8((unsigned char)0xF3);
3814 prefix(src, dst);
3815 emit_int8(0x0F);
3816 emit_int8((unsigned char)0xB8);
3817 emit_operand(dst, src);
3818 }
3819
3820 void Assembler::popcntl(Register dst, Register src) {
3821 assert(VM_Version::supports_popcnt(), "must support");
3822 emit_int8((unsigned char)0xF3);
3823 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3824 emit_int8(0x0F);
3825 emit_int8((unsigned char)0xB8);
3826 emit_int8((unsigned char)(0xC0 | encode));
3827 }
3828
3829 void Assembler::popf() {
3830 emit_int8((unsigned char)0x9D);
3831 }
3832
3833 #ifndef _LP64 // no 32bit push/pop on amd64
3834 void Assembler::popl(Address dst) {
3835 // NOTE: this will adjust stack by 8byte on 64bits
3836 InstructionMark im(this);
3837 prefix(dst);
3838 emit_int8((unsigned char)0x8F);
3839 emit_operand(rax, dst);
3840 }
3841 #endif
3842
3843 void Assembler::prefetch_prefix(Address src) {
3844 prefix(src);
3845 emit_int8(0x0F);
3846 }
3847
3848 void Assembler::prefetchnta(Address src) {
3849 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3850 InstructionMark im(this);
3851 prefetch_prefix(src);
3852 emit_int8(0x18);
3853 emit_operand(rax, src); // 0, src
3854 }
3855
3856 void Assembler::prefetchr(Address src) {
3857 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3858 InstructionMark im(this);
3859 prefetch_prefix(src);
3860 emit_int8(0x0D);
3861 emit_operand(rax, src); // 0, src
3862 }
3863
3864 void Assembler::prefetcht0(Address src) {
3865 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3866 InstructionMark im(this);
3867 prefetch_prefix(src);
3868 emit_int8(0x18);
3869 emit_operand(rcx, src); // 1, src
3870 }
3871
3872 void Assembler::prefetcht1(Address src) {
3873 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3874 InstructionMark im(this);
3875 prefetch_prefix(src);
3876 emit_int8(0x18);
3877 emit_operand(rdx, src); // 2, src
3878 }
3879
3880 void Assembler::prefetcht2(Address src) {
3881 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3882 InstructionMark im(this);
3883 prefetch_prefix(src);
3884 emit_int8(0x18);
3885 emit_operand(rbx, src); // 3, src
3886 }
3887
3888 void Assembler::prefetchw(Address src) {
3889 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3890 InstructionMark im(this);
3891 prefetch_prefix(src);
3892 emit_int8(0x0D);
3893 emit_operand(rcx, src); // 1, src
3894 }
3895
3896 void Assembler::prefix(Prefix p) {
3897 emit_int8(p);
3898 }
3899
3900 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3901 assert(VM_Version::supports_ssse3(), "");
3902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3903 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3904 emit_int8(0x00);
3905 emit_int8((unsigned char)(0xC0 | encode));
3906 }
3907
3908 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3909 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3910 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3911 0, "");
3912 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3913 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3914 emit_int8(0x00);
3915 emit_int8((unsigned char)(0xC0 | encode));
3916 }
3917
3918 void Assembler::pshufb(XMMRegister dst, Address src) {
3919 assert(VM_Version::supports_ssse3(), "");
3920 InstructionMark im(this);
3921 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3922 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3923 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3924 emit_int8(0x00);
3925 emit_operand(dst, src);
3926 }
3927
3928 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3929 assert(isByte(mode), "invalid value");
3930 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3931 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
3932 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3933 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3934 emit_int8(0x70);
3935 emit_int8((unsigned char)(0xC0 | encode));
3936 emit_int8(mode & 0xFF);
3937 }
3938
3939 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
3940 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3941 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3942 0, "");
3943 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3944 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3945 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3946 emit_int8(0x70);
3947 emit_int8((unsigned char)(0xC0 | encode));
3948 emit_int8(mode & 0xFF);
3949 }
3950
3951 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3952 assert(isByte(mode), "invalid value");
3953 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3954 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3955 InstructionMark im(this);
3956 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3957 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3958 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3959 emit_int8(0x70);
3960 emit_operand(dst, src);
3961 emit_int8(mode & 0xFF);
3962 }
3963
3964 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3965 assert(isByte(mode), "invalid value");
3966 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3967 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3968 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3969 emit_int8(0x70);
3970 emit_int8((unsigned char)(0xC0 | encode));
3971 emit_int8(mode & 0xFF);
3972 }
3973
3974 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3975 assert(isByte(mode), "invalid value");
3976 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3977 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3978 InstructionMark im(this);
3979 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3980 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3981 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3982 emit_int8(0x70);
3983 emit_operand(dst, src);
3984 emit_int8(mode & 0xFF);
3985 }
3986
3987 void Assembler::psrldq(XMMRegister dst, int shift) {
3988 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3989 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3990 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3991 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3992 emit_int8(0x73);
3993 emit_int8((unsigned char)(0xC0 | encode));
3994 emit_int8(shift);
3995 }
3996
3997 void Assembler::pslldq(XMMRegister dst, int shift) {
3998 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3999 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4000 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4001 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4002 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4003 emit_int8(0x73);
4004 emit_int8((unsigned char)(0xC0 | encode));
4005 emit_int8(shift);
4006 }
4007
4008 void Assembler::ptest(XMMRegister dst, Address src) {
4009 assert(VM_Version::supports_sse4_1(), "");
4010 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4011 InstructionMark im(this);
4012 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4013 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4014 emit_int8(0x17);
4015 emit_operand(dst, src);
4016 }
4017
4018 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4019 assert(VM_Version::supports_sse4_1(), "");
4020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4021 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4022 emit_int8(0x17);
4023 emit_int8((unsigned char)(0xC0 | encode));
4024 }
4025
4026 void Assembler::vptest(XMMRegister dst, Address src) {
4027 assert(VM_Version::supports_avx(), "");
4028 InstructionMark im(this);
4029 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4030 assert(dst != xnoreg, "sanity");
4031 // swap src<->dst for encoding
4032 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4033 emit_int8(0x17);
4034 emit_operand(dst, src);
4035 }
4036
4037 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4038 assert(VM_Version::supports_avx(), "");
4039 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4040 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4041 emit_int8(0x17);
4042 emit_int8((unsigned char)(0xC0 | encode));
4043 }
4044
4045 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4046 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4047 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4048 InstructionMark im(this);
4049 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4050 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4051 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4052 emit_int8(0x60);
4053 emit_operand(dst, src);
4054 }
4055
4056 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4057 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4058 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4059 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4060 emit_int8(0x60);
4061 emit_int8((unsigned char)(0xC0 | encode));
4062 }
4063
4064 void Assembler::punpckldq(XMMRegister dst, Address src) {
4065 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4066 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4067 InstructionMark im(this);
4068 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4069 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4070 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4071 emit_int8(0x62);
4072 emit_operand(dst, src);
4073 }
4074
4075 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4076 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4077 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4078 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4079 emit_int8(0x62);
4080 emit_int8((unsigned char)(0xC0 | encode));
4081 }
4082
4083 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4084 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4085 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4086 attributes.set_rex_vex_w_reverted();
4087 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4088 emit_int8(0x6C);
4089 emit_int8((unsigned char)(0xC0 | encode));
4090 }
4091
4092 void Assembler::push(int32_t imm32) {
4093 // in 64bits we push 64bits onto the stack but only
4094 // take a 32bit immediate
4095 emit_int8(0x68);
4096 emit_int32(imm32);
4097 }
4098
4099 void Assembler::push(Register src) {
4100 int encode = prefix_and_encode(src->encoding());
4101
4102 emit_int8(0x50 | encode);
4103 }
4104
4105 void Assembler::pushf() {
4106 emit_int8((unsigned char)0x9C);
4107 }
4108
4109 #ifndef _LP64 // no 32bit push/pop on amd64
4110 void Assembler::pushl(Address src) {
4111 // Note this will push 64bit on 64bit
4112 InstructionMark im(this);
4113 prefix(src);
4114 emit_int8((unsigned char)0xFF);
4115 emit_operand(rsi, src);
4116 }
4117 #endif
4118
4119 void Assembler::rcll(Register dst, int imm8) {
4120 assert(isShiftCount(imm8), "illegal shift count");
4121 int encode = prefix_and_encode(dst->encoding());
4122 if (imm8 == 1) {
4123 emit_int8((unsigned char)0xD1);
4124 emit_int8((unsigned char)(0xD0 | encode));
4125 } else {
4126 emit_int8((unsigned char)0xC1);
4127 emit_int8((unsigned char)0xD0 | encode);
4128 emit_int8(imm8);
4129 }
4130 }
4131
4132 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4133 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4134 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4135 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4136 emit_int8(0x53);
4137 emit_int8((unsigned char)(0xC0 | encode));
4138 }
4139
4140 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4141 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4142 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4143 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4144 emit_int8(0x53);
4145 emit_int8((unsigned char)(0xC0 | encode));
4146 }
4147
4148 void Assembler::rdtsc() {
4149 emit_int8((unsigned char)0x0F);
4150 emit_int8((unsigned char)0x31);
4151 }
4152
4153 // copies data from [esi] to [edi] using rcx pointer sized words
4154 // generic
4155 void Assembler::rep_mov() {
4156 emit_int8((unsigned char)0xF3);
4157 // MOVSQ
4158 LP64_ONLY(prefix(REX_W));
4159 emit_int8((unsigned char)0xA5);
4160 }
4161
4162 // sets rcx bytes with rax, value at [edi]
4163 void Assembler::rep_stosb() {
4164 emit_int8((unsigned char)0xF3); // REP
4165 LP64_ONLY(prefix(REX_W));
4166 emit_int8((unsigned char)0xAA); // STOSB
4167 }
4168
4169 // sets rcx pointer sized words with rax, value at [edi]
4170 // generic
4171 void Assembler::rep_stos() {
4172 emit_int8((unsigned char)0xF3); // REP
4173 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4174 emit_int8((unsigned char)0xAB);
4175 }
4176
4177 // scans rcx pointer sized words at [edi] for occurance of rax,
4178 // generic
4179 void Assembler::repne_scan() { // repne_scan
4180 emit_int8((unsigned char)0xF2);
4181 // SCASQ
4182 LP64_ONLY(prefix(REX_W));
4183 emit_int8((unsigned char)0xAF);
4184 }
4185
4186 #ifdef _LP64
4187 // scans rcx 4 byte words at [edi] for occurance of rax,
4188 // generic
4189 void Assembler::repne_scanl() { // repne_scan
4190 emit_int8((unsigned char)0xF2);
4191 // SCASL
4192 emit_int8((unsigned char)0xAF);
4193 }
4194 #endif
4195
4196 void Assembler::ret(int imm16) {
4197 if (imm16 == 0) {
4198 emit_int8((unsigned char)0xC3);
4199 } else {
4200 emit_int8((unsigned char)0xC2);
4201 emit_int16(imm16);
4202 }
4203 }
4204
4205 void Assembler::sahf() {
4206 #ifdef _LP64
4207 // Not supported in 64bit mode
4208 ShouldNotReachHere();
4209 #endif
4210 emit_int8((unsigned char)0x9E);
4211 }
4212
4213 void Assembler::sarl(Register dst, int imm8) {
4214 int encode = prefix_and_encode(dst->encoding());
4215 assert(isShiftCount(imm8), "illegal shift count");
4216 if (imm8 == 1) {
4217 emit_int8((unsigned char)0xD1);
4218 emit_int8((unsigned char)(0xF8 | encode));
4219 } else {
4220 emit_int8((unsigned char)0xC1);
4221 emit_int8((unsigned char)(0xF8 | encode));
4222 emit_int8(imm8);
4223 }
4224 }
4225
4226 void Assembler::sarl(Register dst) {
4227 int encode = prefix_and_encode(dst->encoding());
4228 emit_int8((unsigned char)0xD3);
4229 emit_int8((unsigned char)(0xF8 | encode));
4230 }
4231
4232 void Assembler::sbbl(Address dst, int32_t imm32) {
4233 InstructionMark im(this);
4234 prefix(dst);
4235 emit_arith_operand(0x81, rbx, dst, imm32);
4236 }
4237
4238 void Assembler::sbbl(Register dst, int32_t imm32) {
4239 prefix(dst);
4240 emit_arith(0x81, 0xD8, dst, imm32);
4241 }
4242
4243
4244 void Assembler::sbbl(Register dst, Address src) {
4245 InstructionMark im(this);
4246 prefix(src, dst);
4247 emit_int8(0x1B);
4248 emit_operand(dst, src);
4249 }
4250
4251 void Assembler::sbbl(Register dst, Register src) {
4252 (void) prefix_and_encode(dst->encoding(), src->encoding());
4253 emit_arith(0x1B, 0xC0, dst, src);
4254 }
4255
4256 void Assembler::setb(Condition cc, Register dst) {
4257 assert(0 <= cc && cc < 16, "illegal cc");
4258 int encode = prefix_and_encode(dst->encoding(), true);
4259 emit_int8(0x0F);
4260 emit_int8((unsigned char)0x90 | cc);
4261 emit_int8((unsigned char)(0xC0 | encode));
4262 }
4263
4264 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4265 assert(VM_Version::supports_ssse3(), "");
4266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4267 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4268 emit_int8((unsigned char)0x0F);
4269 emit_int8((unsigned char)(0xC0 | encode));
4270 emit_int8(imm8);
4271 }
4272
4273 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4274 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4275 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4276 0, "");
4277 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4278 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4279 emit_int8((unsigned char)0x0F);
4280 emit_int8((unsigned char)(0xC0 | encode));
4281 emit_int8(imm8);
4282 }
4283
4284 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4285 assert(VM_Version::supports_sse4_1(), "");
4286 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4287 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4288 emit_int8((unsigned char)0x0E);
4289 emit_int8((unsigned char)(0xC0 | encode));
4290 emit_int8(imm8);
4291 }
4292
4293 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4294 assert(VM_Version::supports_sha(), "");
4295 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4296 emit_int8((unsigned char)0xCC);
4297 emit_int8((unsigned char)(0xC0 | encode));
4298 emit_int8((unsigned char)imm8);
4299 }
4300
4301 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4302 assert(VM_Version::supports_sha(), "");
4303 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4304 emit_int8((unsigned char)0xC8);
4305 emit_int8((unsigned char)(0xC0 | encode));
4306 }
4307
4308 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4309 assert(VM_Version::supports_sha(), "");
4310 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4311 emit_int8((unsigned char)0xC9);
4312 emit_int8((unsigned char)(0xC0 | encode));
4313 }
4314
4315 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4316 assert(VM_Version::supports_sha(), "");
4317 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4318 emit_int8((unsigned char)0xCA);
4319 emit_int8((unsigned char)(0xC0 | encode));
4320 }
4321
4322 // xmm0 is implicit additional source to this instruction.
4323 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4324 assert(VM_Version::supports_sha(), "");
4325 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4326 emit_int8((unsigned char)0xCB);
4327 emit_int8((unsigned char)(0xC0 | encode));
4328 }
4329
4330 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4331 assert(VM_Version::supports_sha(), "");
4332 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4333 emit_int8((unsigned char)0xCC);
4334 emit_int8((unsigned char)(0xC0 | encode));
4335 }
4336
4337 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4338 assert(VM_Version::supports_sha(), "");
4339 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4340 emit_int8((unsigned char)0xCD);
4341 emit_int8((unsigned char)(0xC0 | encode));
4342 }
4343
4344
4345 void Assembler::shll(Register dst, int imm8) {
4346 assert(isShiftCount(imm8), "illegal shift count");
4347 int encode = prefix_and_encode(dst->encoding());
4348 if (imm8 == 1 ) {
4349 emit_int8((unsigned char)0xD1);
4350 emit_int8((unsigned char)(0xE0 | encode));
4351 } else {
4352 emit_int8((unsigned char)0xC1);
4353 emit_int8((unsigned char)(0xE0 | encode));
4354 emit_int8(imm8);
4355 }
4356 }
4357
4358 void Assembler::shll(Register dst) {
4359 int encode = prefix_and_encode(dst->encoding());
4360 emit_int8((unsigned char)0xD3);
4361 emit_int8((unsigned char)(0xE0 | encode));
4362 }
4363
4364 void Assembler::shrl(Register dst, int imm8) {
4365 assert(isShiftCount(imm8), "illegal shift count");
4366 int encode = prefix_and_encode(dst->encoding());
4367 emit_int8((unsigned char)0xC1);
4368 emit_int8((unsigned char)(0xE8 | encode));
4369 emit_int8(imm8);
4370 }
4371
4372 void Assembler::shrl(Register dst) {
4373 int encode = prefix_and_encode(dst->encoding());
4374 emit_int8((unsigned char)0xD3);
4375 emit_int8((unsigned char)(0xE8 | encode));
4376 }
4377
4378 // copies a single word from [esi] to [edi]
4379 void Assembler::smovl() {
4380 emit_int8((unsigned char)0xA5);
4381 }
4382
4383 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4384 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4385 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4386 attributes.set_rex_vex_w_reverted();
4387 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4388 emit_int8(0x51);
4389 emit_int8((unsigned char)(0xC0 | encode));
4390 }
4391
4392 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4393 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4394 InstructionMark im(this);
4395 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4396 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4397 attributes.set_rex_vex_w_reverted();
4398 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4399 emit_int8(0x51);
4400 emit_operand(dst, src);
4401 }
4402
4403 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4404 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4406 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4407 emit_int8(0x51);
4408 emit_int8((unsigned char)(0xC0 | encode));
4409 }
4410
4411 void Assembler::std() {
4412 emit_int8((unsigned char)0xFD);
4413 }
4414
4415 void Assembler::sqrtss(XMMRegister dst, Address src) {
4416 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4417 InstructionMark im(this);
4418 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4419 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4420 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4421 emit_int8(0x51);
4422 emit_operand(dst, src);
4423 }
4424
4425 void Assembler::stmxcsr( Address dst) {
4426 if (UseAVX > 0 ) {
4427 assert(VM_Version::supports_avx(), "");
4428 InstructionMark im(this);
4429 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4430 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4431 emit_int8((unsigned char)0xAE);
4432 emit_operand(as_Register(3), dst);
4433 } else {
4434 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4435 InstructionMark im(this);
4436 prefix(dst);
4437 emit_int8(0x0F);
4438 emit_int8((unsigned char)0xAE);
4439 emit_operand(as_Register(3), dst);
4440 }
4441 }
4442
4443 void Assembler::subl(Address dst, int32_t imm32) {
4444 InstructionMark im(this);
4445 prefix(dst);
4446 emit_arith_operand(0x81, rbp, dst, imm32);
4447 }
4448
4449 void Assembler::subl(Address dst, Register src) {
4450 InstructionMark im(this);
4451 prefix(dst, src);
4452 emit_int8(0x29);
4453 emit_operand(src, dst);
4454 }
4455
4456 void Assembler::subl(Register dst, int32_t imm32) {
4457 prefix(dst);
4458 emit_arith(0x81, 0xE8, dst, imm32);
4459 }
4460
4461 // Force generation of a 4 byte immediate value even if it fits into 8bit
4462 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4463 prefix(dst);
4464 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4465 }
4466
4467 void Assembler::subl(Register dst, Address src) {
4468 InstructionMark im(this);
4469 prefix(src, dst);
4470 emit_int8(0x2B);
4471 emit_operand(dst, src);
4472 }
4473
4474 void Assembler::subl(Register dst, Register src) {
4475 (void) prefix_and_encode(dst->encoding(), src->encoding());
4476 emit_arith(0x2B, 0xC0, dst, src);
4477 }
4478
4479 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4480 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4481 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4482 attributes.set_rex_vex_w_reverted();
4483 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4484 emit_int8(0x5C);
4485 emit_int8((unsigned char)(0xC0 | encode));
4486 }
4487
4488 void Assembler::subsd(XMMRegister dst, Address src) {
4489 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4490 InstructionMark im(this);
4491 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4492 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4493 attributes.set_rex_vex_w_reverted();
4494 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4495 emit_int8(0x5C);
4496 emit_operand(dst, src);
4497 }
4498
4499 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4500 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4501 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4502 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4503 emit_int8(0x5C);
4504 emit_int8((unsigned char)(0xC0 | encode));
4505 }
4506
4507 void Assembler::subss(XMMRegister dst, Address src) {
4508 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4509 InstructionMark im(this);
4510 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4511 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4512 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4513 emit_int8(0x5C);
4514 emit_operand(dst, src);
4515 }
4516
4517 void Assembler::testb(Register dst, int imm8) {
4518 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4519 (void) prefix_and_encode(dst->encoding(), true);
4520 emit_arith_b(0xF6, 0xC0, dst, imm8);
4521 }
4522
4523 void Assembler::testb(Address dst, int imm8) {
4524 InstructionMark im(this);
4525 prefix(dst);
4526 emit_int8((unsigned char)0xF6);
4527 emit_operand(rax, dst, 1);
4528 emit_int8(imm8);
4529 }
4530
4531 void Assembler::testl(Register dst, int32_t imm32) {
4532 // not using emit_arith because test
4533 // doesn't support sign-extension of
4534 // 8bit operands
4535 int encode = dst->encoding();
4536 if (encode == 0) {
4537 emit_int8((unsigned char)0xA9);
4538 } else {
4539 encode = prefix_and_encode(encode);
4540 emit_int8((unsigned char)0xF7);
4541 emit_int8((unsigned char)(0xC0 | encode));
4542 }
4543 emit_int32(imm32);
4544 }
4545
4546 void Assembler::testl(Register dst, Register src) {
4547 (void) prefix_and_encode(dst->encoding(), src->encoding());
4548 emit_arith(0x85, 0xC0, dst, src);
4549 }
4550
4551 void Assembler::testl(Register dst, Address src) {
4552 InstructionMark im(this);
4553 prefix(src, dst);
4554 emit_int8((unsigned char)0x85);
4555 emit_operand(dst, src);
4556 }
4557
4558 void Assembler::tzcntl(Register dst, Register src) {
4559 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4560 emit_int8((unsigned char)0xF3);
4561 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4562 emit_int8(0x0F);
4563 emit_int8((unsigned char)0xBC);
4564 emit_int8((unsigned char)0xC0 | encode);
4565 }
4566
4567 void Assembler::tzcntq(Register dst, Register src) {
4568 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4569 emit_int8((unsigned char)0xF3);
4570 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4571 emit_int8(0x0F);
4572 emit_int8((unsigned char)0xBC);
4573 emit_int8((unsigned char)(0xC0 | encode));
4574 }
4575
4576 void Assembler::ucomisd(XMMRegister dst, Address src) {
4577 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4578 InstructionMark im(this);
4579 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4580 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4581 attributes.set_rex_vex_w_reverted();
4582 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4583 emit_int8(0x2E);
4584 emit_operand(dst, src);
4585 }
4586
4587 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4588 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4589 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4590 attributes.set_rex_vex_w_reverted();
4591 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4592 emit_int8(0x2E);
4593 emit_int8((unsigned char)(0xC0 | encode));
4594 }
4595
4596 void Assembler::ucomiss(XMMRegister dst, Address src) {
4597 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4598 InstructionMark im(this);
4599 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4600 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4601 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4602 emit_int8(0x2E);
4603 emit_operand(dst, src);
4604 }
4605
4606 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4607 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4608 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4609 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4610 emit_int8(0x2E);
4611 emit_int8((unsigned char)(0xC0 | encode));
4612 }
4613
4614 void Assembler::xabort(int8_t imm8) {
4615 emit_int8((unsigned char)0xC6);
4616 emit_int8((unsigned char)0xF8);
4617 emit_int8((unsigned char)(imm8 & 0xFF));
4618 }
4619
4620 void Assembler::xaddb(Address dst, Register src) {
4621 InstructionMark im(this);
4622 prefix(dst, src, true);
4623 emit_int8(0x0F);
4624 emit_int8((unsigned char)0xC0);
4625 emit_operand(src, dst);
4626 }
4627
4628 void Assembler::xaddw(Address dst, Register src) {
4629 InstructionMark im(this);
4630 emit_int8(0x66);
4631 prefix(dst, src);
4632 emit_int8(0x0F);
4633 emit_int8((unsigned char)0xC1);
4634 emit_operand(src, dst);
4635 }
4636
4637 void Assembler::xaddl(Address dst, Register src) {
4638 InstructionMark im(this);
4639 prefix(dst, src);
4640 emit_int8(0x0F);
4641 emit_int8((unsigned char)0xC1);
4642 emit_operand(src, dst);
4643 }
4644
4645 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4646 InstructionMark im(this);
4647 relocate(rtype);
4648 if (abort.is_bound()) {
4649 address entry = target(abort);
4650 assert(entry != NULL, "abort entry NULL");
4651 intptr_t offset = entry - pc();
4652 emit_int8((unsigned char)0xC7);
4653 emit_int8((unsigned char)0xF8);
4654 emit_int32(offset - 6); // 2 opcode + 4 address
4655 } else {
4656 abort.add_patch_at(code(), locator());
4657 emit_int8((unsigned char)0xC7);
4658 emit_int8((unsigned char)0xF8);
4659 emit_int32(0);
4660 }
4661 }
4662
4663 void Assembler::xchgb(Register dst, Address src) { // xchg
4664 InstructionMark im(this);
4665 prefix(src, dst, true);
4666 emit_int8((unsigned char)0x86);
4667 emit_operand(dst, src);
4668 }
4669
4670 void Assembler::xchgw(Register dst, Address src) { // xchg
4671 InstructionMark im(this);
4672 emit_int8(0x66);
4673 prefix(src, dst);
4674 emit_int8((unsigned char)0x87);
4675 emit_operand(dst, src);
4676 }
4677
4678 void Assembler::xchgl(Register dst, Address src) { // xchg
4679 InstructionMark im(this);
4680 prefix(src, dst);
4681 emit_int8((unsigned char)0x87);
4682 emit_operand(dst, src);
4683 }
4684
4685 void Assembler::xchgl(Register dst, Register src) {
4686 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4687 emit_int8((unsigned char)0x87);
4688 emit_int8((unsigned char)(0xC0 | encode));
4689 }
4690
4691 void Assembler::xend() {
4692 emit_int8((unsigned char)0x0F);
4693 emit_int8((unsigned char)0x01);
4694 emit_int8((unsigned char)0xD5);
4695 }
4696
4697 void Assembler::xgetbv() {
4698 emit_int8(0x0F);
4699 emit_int8(0x01);
4700 emit_int8((unsigned char)0xD0);
4701 }
4702
4703 void Assembler::xorl(Register dst, int32_t imm32) {
4704 prefix(dst);
4705 emit_arith(0x81, 0xF0, dst, imm32);
4706 }
4707
4708 void Assembler::xorl(Register dst, Address src) {
4709 InstructionMark im(this);
4710 prefix(src, dst);
4711 emit_int8(0x33);
4712 emit_operand(dst, src);
4713 }
4714
4715 void Assembler::xorl(Register dst, Register src) {
4716 (void) prefix_and_encode(dst->encoding(), src->encoding());
4717 emit_arith(0x33, 0xC0, dst, src);
4718 }
4719
4720 void Assembler::xorb(Register dst, Address src) {
4721 InstructionMark im(this);
4722 prefix(src, dst);
4723 emit_int8(0x32);
4724 emit_operand(dst, src);
4725 }
4726
4727 // AVX 3-operands scalar float-point arithmetic instructions
4728
4729 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4730 assert(VM_Version::supports_avx(), "");
4731 InstructionMark im(this);
4732 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4733 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4734 attributes.set_rex_vex_w_reverted();
4735 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4736 emit_int8(0x58);
4737 emit_operand(dst, src);
4738 }
4739
4740 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4741 assert(VM_Version::supports_avx(), "");
4742 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4743 attributes.set_rex_vex_w_reverted();
4744 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4745 emit_int8(0x58);
4746 emit_int8((unsigned char)(0xC0 | encode));
4747 }
4748
4749 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4750 assert(VM_Version::supports_avx(), "");
4751 InstructionMark im(this);
4752 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4753 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4754 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4755 emit_int8(0x58);
4756 emit_operand(dst, src);
4757 }
4758
4759 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4760 assert(VM_Version::supports_avx(), "");
4761 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4762 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4763 emit_int8(0x58);
4764 emit_int8((unsigned char)(0xC0 | encode));
4765 }
4766
4767 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4768 assert(VM_Version::supports_avx(), "");
4769 InstructionMark im(this);
4770 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4771 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4772 attributes.set_rex_vex_w_reverted();
4773 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4774 emit_int8(0x5E);
4775 emit_operand(dst, src);
4776 }
4777
4778 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4779 assert(VM_Version::supports_avx(), "");
4780 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4781 attributes.set_rex_vex_w_reverted();
4782 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4783 emit_int8(0x5E);
4784 emit_int8((unsigned char)(0xC0 | encode));
4785 }
4786
4787 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4788 assert(VM_Version::supports_avx(), "");
4789 InstructionMark im(this);
4790 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4791 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4792 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4793 emit_int8(0x5E);
4794 emit_operand(dst, src);
4795 }
4796
4797 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4798 assert(VM_Version::supports_avx(), "");
4799 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4800 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4801 emit_int8(0x5E);
4802 emit_int8((unsigned char)(0xC0 | encode));
4803 }
4804
4805 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
4806 assert(VM_Version::supports_fma(), "");
4807 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4808 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4809 emit_int8((unsigned char)0xB9);
4810 emit_int8((unsigned char)(0xC0 | encode));
4811 }
4812
4813 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
4814 assert(VM_Version::supports_fma(), "");
4815 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4816 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4817 emit_int8((unsigned char)0xB9);
4818 emit_int8((unsigned char)(0xC0 | encode));
4819 }
4820
4821 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4822 assert(VM_Version::supports_avx(), "");
4823 InstructionMark im(this);
4824 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4825 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4826 attributes.set_rex_vex_w_reverted();
4827 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4828 emit_int8(0x59);
4829 emit_operand(dst, src);
4830 }
4831
4832 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4833 assert(VM_Version::supports_avx(), "");
4834 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4835 attributes.set_rex_vex_w_reverted();
4836 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4837 emit_int8(0x59);
4838 emit_int8((unsigned char)(0xC0 | encode));
4839 }
4840
4841 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4842 assert(VM_Version::supports_avx(), "");
4843 InstructionMark im(this);
4844 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4845 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4846 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4847 emit_int8(0x59);
4848 emit_operand(dst, src);
4849 }
4850
4851 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4852 assert(VM_Version::supports_avx(), "");
4853 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4854 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4855 emit_int8(0x59);
4856 emit_int8((unsigned char)(0xC0 | encode));
4857 }
4858
4859 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4860 assert(VM_Version::supports_avx(), "");
4861 InstructionMark im(this);
4862 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4863 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4864 attributes.set_rex_vex_w_reverted();
4865 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4866 emit_int8(0x5C);
4867 emit_operand(dst, src);
4868 }
4869
4870 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4871 assert(VM_Version::supports_avx(), "");
4872 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4873 attributes.set_rex_vex_w_reverted();
4874 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4875 emit_int8(0x5C);
4876 emit_int8((unsigned char)(0xC0 | encode));
4877 }
4878
4879 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4880 assert(VM_Version::supports_avx(), "");
4881 InstructionMark im(this);
4882 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4883 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4884 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4885 emit_int8(0x5C);
4886 emit_operand(dst, src);
4887 }
4888
4889 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4890 assert(VM_Version::supports_avx(), "");
4891 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4892 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4893 emit_int8(0x5C);
4894 emit_int8((unsigned char)(0xC0 | encode));
4895 }
4896
4897 //====================VECTOR ARITHMETIC=====================================
4898
4899 // Float-point vector arithmetic
4900
4901 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4902 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4903 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4904 attributes.set_rex_vex_w_reverted();
4905 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4906 emit_int8(0x58);
4907 emit_int8((unsigned char)(0xC0 | encode));
4908 }
4909
4910 void Assembler::addpd(XMMRegister dst, Address src) {
4911 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4912 InstructionMark im(this);
4913 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4914 attributes.set_rex_vex_w_reverted();
4915 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4916 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4917 emit_int8(0x58);
4918 emit_operand(dst, src);
4919 }
4920
4921
4922 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4923 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4924 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4925 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4926 emit_int8(0x58);
4927 emit_int8((unsigned char)(0xC0 | encode));
4928 }
4929
4930 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4931 assert(VM_Version::supports_avx(), "");
4932 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4933 attributes.set_rex_vex_w_reverted();
4934 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4935 emit_int8(0x58);
4936 emit_int8((unsigned char)(0xC0 | encode));
4937 }
4938
4939 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4940 assert(VM_Version::supports_avx(), "");
4941 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4942 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4943 emit_int8(0x58);
4944 emit_int8((unsigned char)(0xC0 | encode));
4945 }
4946
4947 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4948 assert(VM_Version::supports_avx(), "");
4949 InstructionMark im(this);
4950 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4951 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4952 attributes.set_rex_vex_w_reverted();
4953 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4954 emit_int8(0x58);
4955 emit_operand(dst, src);
4956 }
4957
4958 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4959 assert(VM_Version::supports_avx(), "");
4960 InstructionMark im(this);
4961 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4962 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4963 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4964 emit_int8(0x58);
4965 emit_operand(dst, src);
4966 }
4967
4968 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4969 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4970 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4971 attributes.set_rex_vex_w_reverted();
4972 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4973 emit_int8(0x5C);
4974 emit_int8((unsigned char)(0xC0 | encode));
4975 }
4976
4977 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4978 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4979 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4980 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4981 emit_int8(0x5C);
4982 emit_int8((unsigned char)(0xC0 | encode));
4983 }
4984
4985 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4986 assert(VM_Version::supports_avx(), "");
4987 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4988 attributes.set_rex_vex_w_reverted();
4989 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4990 emit_int8(0x5C);
4991 emit_int8((unsigned char)(0xC0 | encode));
4992 }
4993
4994 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4995 assert(VM_Version::supports_avx(), "");
4996 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4997 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4998 emit_int8(0x5C);
4999 emit_int8((unsigned char)(0xC0 | encode));
5000 }
5001
5002 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5003 assert(VM_Version::supports_avx(), "");
5004 InstructionMark im(this);
5005 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5006 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5007 attributes.set_rex_vex_w_reverted();
5008 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5009 emit_int8(0x5C);
5010 emit_operand(dst, src);
5011 }
5012
5013 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5014 assert(VM_Version::supports_avx(), "");
5015 InstructionMark im(this);
5016 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5017 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5018 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5019 emit_int8(0x5C);
5020 emit_operand(dst, src);
5021 }
5022
5023 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5024 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5025 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5026 attributes.set_rex_vex_w_reverted();
5027 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5028 emit_int8(0x59);
5029 emit_int8((unsigned char)(0xC0 | encode));
5030 }
5031
5032 void Assembler::mulpd(XMMRegister dst, Address src) {
5033 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5034 InstructionMark im(this);
5035 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5036 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5037 attributes.set_rex_vex_w_reverted();
5038 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5039 emit_int8(0x59);
5040 emit_operand(dst, src);
5041 }
5042
5043 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5045 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5047 emit_int8(0x59);
5048 emit_int8((unsigned char)(0xC0 | encode));
5049 }
5050
5051 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5052 assert(VM_Version::supports_avx(), "");
5053 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5054 attributes.set_rex_vex_w_reverted();
5055 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5056 emit_int8(0x59);
5057 emit_int8((unsigned char)(0xC0 | encode));
5058 }
5059
5060 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5061 assert(VM_Version::supports_avx(), "");
5062 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5063 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5064 emit_int8(0x59);
5065 emit_int8((unsigned char)(0xC0 | encode));
5066 }
5067
5068 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5069 assert(VM_Version::supports_avx(), "");
5070 InstructionMark im(this);
5071 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5072 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5073 attributes.set_rex_vex_w_reverted();
5074 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5075 emit_int8(0x59);
5076 emit_operand(dst, src);
5077 }
5078
5079 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5080 assert(VM_Version::supports_avx(), "");
5081 InstructionMark im(this);
5082 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5083 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5084 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5085 emit_int8(0x59);
5086 emit_operand(dst, src);
5087 }
5088
5089 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5091 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5092 attributes.set_rex_vex_w_reverted();
5093 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5094 emit_int8(0x5E);
5095 emit_int8((unsigned char)(0xC0 | encode));
5096 }
5097
5098 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5099 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5100 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5101 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5102 emit_int8(0x5E);
5103 emit_int8((unsigned char)(0xC0 | encode));
5104 }
5105
5106 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5107 assert(VM_Version::supports_avx(), "");
5108 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5109 attributes.set_rex_vex_w_reverted();
5110 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5111 emit_int8(0x5E);
5112 emit_int8((unsigned char)(0xC0 | encode));
5113 }
5114
5115 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5116 assert(VM_Version::supports_avx(), "");
5117 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5118 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5119 emit_int8(0x5E);
5120 emit_int8((unsigned char)(0xC0 | encode));
5121 }
5122
5123 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5124 assert(VM_Version::supports_avx(), "");
5125 InstructionMark im(this);
5126 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5127 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5128 attributes.set_rex_vex_w_reverted();
5129 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5130 emit_int8(0x5E);
5131 emit_operand(dst, src);
5132 }
5133
5134 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5135 assert(VM_Version::supports_avx(), "");
5136 InstructionMark im(this);
5137 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5138 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5139 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5140 emit_int8(0x5E);
5141 emit_operand(dst, src);
5142 }
5143
5144 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5145 assert(VM_Version::supports_avx(), "");
5146 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5147 attributes.set_rex_vex_w_reverted();
5148 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5149 emit_int8(0x51);
5150 emit_int8((unsigned char)(0xC0 | encode));
5151 }
5152
5153 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5154 assert(VM_Version::supports_avx(), "");
5155 InstructionMark im(this);
5156 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5157 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5158 attributes.set_rex_vex_w_reverted();
5159 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5160 emit_int8(0x51);
5161 emit_operand(dst, src);
5162 }
5163
5164 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5165 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5166 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5167 attributes.set_rex_vex_w_reverted();
5168 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5169 emit_int8(0x54);
5170 emit_int8((unsigned char)(0xC0 | encode));
5171 }
5172
5173 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5174 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5175 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5176 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5177 emit_int8(0x54);
5178 emit_int8((unsigned char)(0xC0 | encode));
5179 }
5180
5181 void Assembler::andps(XMMRegister dst, Address src) {
5182 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5183 InstructionMark im(this);
5184 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5185 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5186 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5187 emit_int8(0x54);
5188 emit_operand(dst, src);
5189 }
5190
5191 void Assembler::andpd(XMMRegister dst, Address src) {
5192 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5193 InstructionMark im(this);
5194 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5195 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5196 attributes.set_rex_vex_w_reverted();
5197 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5198 emit_int8(0x54);
5199 emit_operand(dst, src);
5200 }
5201
5202 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5203 assert(VM_Version::supports_avx(), "");
5204 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5205 attributes.set_rex_vex_w_reverted();
5206 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5207 emit_int8(0x54);
5208 emit_int8((unsigned char)(0xC0 | encode));
5209 }
5210
5211 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5212 assert(VM_Version::supports_avx(), "");
5213 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5214 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5215 emit_int8(0x54);
5216 emit_int8((unsigned char)(0xC0 | encode));
5217 }
5218
5219 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5220 assert(VM_Version::supports_avx(), "");
5221 InstructionMark im(this);
5222 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5223 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5224 attributes.set_rex_vex_w_reverted();
5225 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5226 emit_int8(0x54);
5227 emit_operand(dst, src);
5228 }
5229
5230 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5231 assert(VM_Version::supports_avx(), "");
5232 InstructionMark im(this);
5233 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5234 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5235 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5236 emit_int8(0x54);
5237 emit_operand(dst, src);
5238 }
5239
5240 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5243 attributes.set_rex_vex_w_reverted();
5244 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5245 emit_int8(0x15);
5246 emit_int8((unsigned char)(0xC0 | encode));
5247 }
5248
5249 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5251 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5252 attributes.set_rex_vex_w_reverted();
5253 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5254 emit_int8(0x14);
5255 emit_int8((unsigned char)(0xC0 | encode));
5256 }
5257
5258 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5259 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5260 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5261 attributes.set_rex_vex_w_reverted();
5262 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5263 emit_int8(0x57);
5264 emit_int8((unsigned char)(0xC0 | encode));
5265 }
5266
5267 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5268 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5270 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5271 emit_int8(0x57);
5272 emit_int8((unsigned char)(0xC0 | encode));
5273 }
5274
5275 void Assembler::xorpd(XMMRegister dst, Address src) {
5276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5277 InstructionMark im(this);
5278 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5279 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5280 attributes.set_rex_vex_w_reverted();
5281 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5282 emit_int8(0x57);
5283 emit_operand(dst, src);
5284 }
5285
5286 void Assembler::xorps(XMMRegister dst, Address src) {
5287 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5288 InstructionMark im(this);
5289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5290 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5291 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5292 emit_int8(0x57);
5293 emit_operand(dst, src);
5294 }
5295
5296 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5297 assert(VM_Version::supports_avx(), "");
5298 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5299 attributes.set_rex_vex_w_reverted();
5300 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5301 emit_int8(0x57);
5302 emit_int8((unsigned char)(0xC0 | encode));
5303 }
5304
5305 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5306 assert(VM_Version::supports_avx(), "");
5307 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5308 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5309 emit_int8(0x57);
5310 emit_int8((unsigned char)(0xC0 | encode));
5311 }
5312
5313 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5314 assert(VM_Version::supports_avx(), "");
5315 InstructionMark im(this);
5316 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5317 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5318 attributes.set_rex_vex_w_reverted();
5319 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5320 emit_int8(0x57);
5321 emit_operand(dst, src);
5322 }
5323
5324 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5325 assert(VM_Version::supports_avx(), "");
5326 InstructionMark im(this);
5327 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5328 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5329 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5330 emit_int8(0x57);
5331 emit_operand(dst, src);
5332 }
5333
5334 // Integer vector arithmetic
5335 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5336 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5337 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5338 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5339 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5340 emit_int8(0x01);
5341 emit_int8((unsigned char)(0xC0 | encode));
5342 }
5343
5344 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5345 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5346 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5347 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5348 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5349 emit_int8(0x02);
5350 emit_int8((unsigned char)(0xC0 | encode));
5351 }
5352
5353 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5354 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5355 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5356 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5357 emit_int8((unsigned char)0xFC);
5358 emit_int8((unsigned char)(0xC0 | encode));
5359 }
5360
5361 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5364 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5365 emit_int8((unsigned char)0xFD);
5366 emit_int8((unsigned char)(0xC0 | encode));
5367 }
5368
5369 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5371 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5372 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5373 emit_int8((unsigned char)0xFE);
5374 emit_int8((unsigned char)(0xC0 | encode));
5375 }
5376
5377 void Assembler::paddd(XMMRegister dst, Address src) {
5378 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5379 InstructionMark im(this);
5380 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5381 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5382 emit_int8((unsigned char)0xFE);
5383 emit_operand(dst, src);
5384 }
5385
5386 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5387 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5388 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5389 attributes.set_rex_vex_w_reverted();
5390 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5391 emit_int8((unsigned char)0xD4);
5392 emit_int8((unsigned char)(0xC0 | encode));
5393 }
5394
5395 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5396 assert(VM_Version::supports_sse3(), "");
5397 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5398 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5399 emit_int8(0x01);
5400 emit_int8((unsigned char)(0xC0 | encode));
5401 }
5402
5403 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5404 assert(VM_Version::supports_sse3(), "");
5405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5406 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5407 emit_int8(0x02);
5408 emit_int8((unsigned char)(0xC0 | encode));
5409 }
5410
5411 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5412 assert(UseAVX > 0, "requires some form of AVX");
5413 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5414 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5415 emit_int8((unsigned char)0xFC);
5416 emit_int8((unsigned char)(0xC0 | encode));
5417 }
5418
5419 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5420 assert(UseAVX > 0, "requires some form of AVX");
5421 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5422 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5423 emit_int8((unsigned char)0xFD);
5424 emit_int8((unsigned char)(0xC0 | encode));
5425 }
5426
5427 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5428 assert(UseAVX > 0, "requires some form of AVX");
5429 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5430 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5431 emit_int8((unsigned char)0xFE);
5432 emit_int8((unsigned char)(0xC0 | encode));
5433 }
5434
5435 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5436 assert(UseAVX > 0, "requires some form of AVX");
5437 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5438 attributes.set_rex_vex_w_reverted();
5439 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5440 emit_int8((unsigned char)0xD4);
5441 emit_int8((unsigned char)(0xC0 | encode));
5442 }
5443
5444 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5445 assert(UseAVX > 0, "requires some form of AVX");
5446 InstructionMark im(this);
5447 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5448 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5449 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5450 emit_int8((unsigned char)0xFC);
5451 emit_operand(dst, src);
5452 }
5453
5454 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5455 assert(UseAVX > 0, "requires some form of AVX");
5456 InstructionMark im(this);
5457 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5458 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5459 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5460 emit_int8((unsigned char)0xFD);
5461 emit_operand(dst, src);
5462 }
5463
5464 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5465 assert(UseAVX > 0, "requires some form of AVX");
5466 InstructionMark im(this);
5467 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5468 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5469 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5470 emit_int8((unsigned char)0xFE);
5471 emit_operand(dst, src);
5472 }
5473
5474 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5475 assert(UseAVX > 0, "requires some form of AVX");
5476 InstructionMark im(this);
5477 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5478 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5479 attributes.set_rex_vex_w_reverted();
5480 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5481 emit_int8((unsigned char)0xD4);
5482 emit_operand(dst, src);
5483 }
5484
5485 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5486 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5487 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5488 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5489 emit_int8((unsigned char)0xF8);
5490 emit_int8((unsigned char)(0xC0 | encode));
5491 }
5492
5493 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5495 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5496 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5497 emit_int8((unsigned char)0xF9);
5498 emit_int8((unsigned char)(0xC0 | encode));
5499 }
5500
5501 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5502 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5503 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5504 emit_int8((unsigned char)0xFA);
5505 emit_int8((unsigned char)(0xC0 | encode));
5506 }
5507
5508 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5509 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5510 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5511 attributes.set_rex_vex_w_reverted();
5512 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5513 emit_int8((unsigned char)0xFB);
5514 emit_int8((unsigned char)(0xC0 | encode));
5515 }
5516
5517 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5518 assert(UseAVX > 0, "requires some form of AVX");
5519 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5520 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5521 emit_int8((unsigned char)0xF8);
5522 emit_int8((unsigned char)(0xC0 | encode));
5523 }
5524
5525 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5526 assert(UseAVX > 0, "requires some form of AVX");
5527 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5528 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5529 emit_int8((unsigned char)0xF9);
5530 emit_int8((unsigned char)(0xC0 | encode));
5531 }
5532
5533 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5534 assert(UseAVX > 0, "requires some form of AVX");
5535 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5536 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5537 emit_int8((unsigned char)0xFA);
5538 emit_int8((unsigned char)(0xC0 | encode));
5539 }
5540
5541 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5542 assert(UseAVX > 0, "requires some form of AVX");
5543 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5544 attributes.set_rex_vex_w_reverted();
5545 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5546 emit_int8((unsigned char)0xFB);
5547 emit_int8((unsigned char)(0xC0 | encode));
5548 }
5549
5550 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5551 assert(UseAVX > 0, "requires some form of AVX");
5552 InstructionMark im(this);
5553 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5554 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5555 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5556 emit_int8((unsigned char)0xF8);
5557 emit_operand(dst, src);
5558 }
5559
5560 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5561 assert(UseAVX > 0, "requires some form of AVX");
5562 InstructionMark im(this);
5563 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5564 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5565 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5566 emit_int8((unsigned char)0xF9);
5567 emit_operand(dst, src);
5568 }
5569
5570 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5571 assert(UseAVX > 0, "requires some form of AVX");
5572 InstructionMark im(this);
5573 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5574 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5575 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5576 emit_int8((unsigned char)0xFA);
5577 emit_operand(dst, src);
5578 }
5579
5580 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5581 assert(UseAVX > 0, "requires some form of AVX");
5582 InstructionMark im(this);
5583 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5584 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5585 attributes.set_rex_vex_w_reverted();
5586 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5587 emit_int8((unsigned char)0xFB);
5588 emit_operand(dst, src);
5589 }
5590
5591 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5592 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5593 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5594 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5595 emit_int8((unsigned char)0xD5);
5596 emit_int8((unsigned char)(0xC0 | encode));
5597 }
5598
5599 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5600 assert(VM_Version::supports_sse4_1(), "");
5601 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5602 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5603 emit_int8(0x40);
5604 emit_int8((unsigned char)(0xC0 | encode));
5605 }
5606
5607 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5608 assert(UseAVX > 0, "requires some form of AVX");
5609 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5610 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5611 emit_int8((unsigned char)0xD5);
5612 emit_int8((unsigned char)(0xC0 | encode));
5613 }
5614
5615 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5616 assert(UseAVX > 0, "requires some form of AVX");
5617 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5618 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5619 emit_int8(0x40);
5620 emit_int8((unsigned char)(0xC0 | encode));
5621 }
5622
5623 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5624 assert(UseAVX > 2, "requires some form of EVEX");
5625 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5626 attributes.set_is_evex_instruction();
5627 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5628 emit_int8(0x40);
5629 emit_int8((unsigned char)(0xC0 | encode));
5630 }
5631
5632 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5633 assert(UseAVX > 0, "requires some form of AVX");
5634 InstructionMark im(this);
5635 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5636 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5637 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5638 emit_int8((unsigned char)0xD5);
5639 emit_operand(dst, src);
5640 }
5641
5642 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5643 assert(UseAVX > 0, "requires some form of AVX");
5644 InstructionMark im(this);
5645 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5646 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5647 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5648 emit_int8(0x40);
5649 emit_operand(dst, src);
5650 }
5651
5652 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5653 assert(UseAVX > 2, "requires some form of EVEX");
5654 InstructionMark im(this);
5655 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5656 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5657 attributes.set_is_evex_instruction();
5658 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5659 emit_int8(0x40);
5660 emit_operand(dst, src);
5661 }
5662
5663 // Shift packed integers left by specified number of bits.
5664 void Assembler::psllw(XMMRegister dst, int shift) {
5665 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5666 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5667 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5668 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5669 emit_int8(0x71);
5670 emit_int8((unsigned char)(0xC0 | encode));
5671 emit_int8(shift & 0xFF);
5672 }
5673
5674 void Assembler::pslld(XMMRegister dst, int shift) {
5675 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5676 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5677 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5678 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5679 emit_int8(0x72);
5680 emit_int8((unsigned char)(0xC0 | encode));
5681 emit_int8(shift & 0xFF);
5682 }
5683
5684 void Assembler::psllq(XMMRegister dst, int shift) {
5685 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5686 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5687 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5688 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5689 emit_int8(0x73);
5690 emit_int8((unsigned char)(0xC0 | encode));
5691 emit_int8(shift & 0xFF);
5692 }
5693
5694 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5695 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5696 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5697 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5698 emit_int8((unsigned char)0xF1);
5699 emit_int8((unsigned char)(0xC0 | encode));
5700 }
5701
5702 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5703 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5704 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5705 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5706 emit_int8((unsigned char)0xF2);
5707 emit_int8((unsigned char)(0xC0 | encode));
5708 }
5709
5710 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5712 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5713 attributes.set_rex_vex_w_reverted();
5714 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5715 emit_int8((unsigned char)0xF3);
5716 emit_int8((unsigned char)(0xC0 | encode));
5717 }
5718
5719 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5720 assert(UseAVX > 0, "requires some form of AVX");
5721 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5722 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5723 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5724 emit_int8(0x71);
5725 emit_int8((unsigned char)(0xC0 | encode));
5726 emit_int8(shift & 0xFF);
5727 }
5728
5729 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5730 assert(UseAVX > 0, "requires some form of AVX");
5731 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5732 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5733 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5734 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5735 emit_int8(0x72);
5736 emit_int8((unsigned char)(0xC0 | encode));
5737 emit_int8(shift & 0xFF);
5738 }
5739
5740 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5741 assert(UseAVX > 0, "requires some form of AVX");
5742 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5743 attributes.set_rex_vex_w_reverted();
5744 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5745 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5746 emit_int8(0x73);
5747 emit_int8((unsigned char)(0xC0 | encode));
5748 emit_int8(shift & 0xFF);
5749 }
5750
5751 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5752 assert(UseAVX > 0, "requires some form of AVX");
5753 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5754 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5755 emit_int8((unsigned char)0xF1);
5756 emit_int8((unsigned char)(0xC0 | encode));
5757 }
5758
5759 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5760 assert(UseAVX > 0, "requires some form of AVX");
5761 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5762 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5763 emit_int8((unsigned char)0xF2);
5764 emit_int8((unsigned char)(0xC0 | encode));
5765 }
5766
5767 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5768 assert(UseAVX > 0, "requires some form of AVX");
5769 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5770 attributes.set_rex_vex_w_reverted();
5771 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5772 emit_int8((unsigned char)0xF3);
5773 emit_int8((unsigned char)(0xC0 | encode));
5774 }
5775
5776 // Shift packed integers logically right by specified number of bits.
5777 void Assembler::psrlw(XMMRegister dst, int shift) {
5778 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5779 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5780 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5781 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5782 emit_int8(0x71);
5783 emit_int8((unsigned char)(0xC0 | encode));
5784 emit_int8(shift & 0xFF);
5785 }
5786
5787 void Assembler::psrld(XMMRegister dst, int shift) {
5788 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5789 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5790 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5791 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5792 emit_int8(0x72);
5793 emit_int8((unsigned char)(0xC0 | encode));
5794 emit_int8(shift & 0xFF);
5795 }
5796
5797 void Assembler::psrlq(XMMRegister dst, int shift) {
5798 // Do not confuse it with psrldq SSE2 instruction which
5799 // shifts 128 bit value in xmm register by number of bytes.
5800 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5801 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5802 attributes.set_rex_vex_w_reverted();
5803 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5804 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5805 emit_int8(0x73);
5806 emit_int8((unsigned char)(0xC0 | encode));
5807 emit_int8(shift & 0xFF);
5808 }
5809
5810 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5811 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5813 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5814 emit_int8((unsigned char)0xD1);
5815 emit_int8((unsigned char)(0xC0 | encode));
5816 }
5817
5818 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5819 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5821 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5822 emit_int8((unsigned char)0xD2);
5823 emit_int8((unsigned char)(0xC0 | encode));
5824 }
5825
5826 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5827 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5828 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5829 attributes.set_rex_vex_w_reverted();
5830 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5831 emit_int8((unsigned char)0xD3);
5832 emit_int8((unsigned char)(0xC0 | encode));
5833 }
5834
5835 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5836 assert(UseAVX > 0, "requires some form of AVX");
5837 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5838 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5839 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5840 emit_int8(0x71);
5841 emit_int8((unsigned char)(0xC0 | encode));
5842 emit_int8(shift & 0xFF);
5843 }
5844
5845 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5846 assert(UseAVX > 0, "requires some form of AVX");
5847 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5848 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5849 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5850 emit_int8(0x72);
5851 emit_int8((unsigned char)(0xC0 | encode));
5852 emit_int8(shift & 0xFF);
5853 }
5854
5855 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5856 assert(UseAVX > 0, "requires some form of AVX");
5857 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5858 attributes.set_rex_vex_w_reverted();
5859 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5860 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5861 emit_int8(0x73);
5862 emit_int8((unsigned char)(0xC0 | encode));
5863 emit_int8(shift & 0xFF);
5864 }
5865
5866 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5867 assert(UseAVX > 0, "requires some form of AVX");
5868 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5869 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5870 emit_int8((unsigned char)0xD1);
5871 emit_int8((unsigned char)(0xC0 | encode));
5872 }
5873
5874 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5875 assert(UseAVX > 0, "requires some form of AVX");
5876 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5877 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5878 emit_int8((unsigned char)0xD2);
5879 emit_int8((unsigned char)(0xC0 | encode));
5880 }
5881
5882 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5883 assert(UseAVX > 0, "requires some form of AVX");
5884 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5885 attributes.set_rex_vex_w_reverted();
5886 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5887 emit_int8((unsigned char)0xD3);
5888 emit_int8((unsigned char)(0xC0 | encode));
5889 }
5890
5891 // Shift packed integers arithmetically right by specified number of bits.
5892 void Assembler::psraw(XMMRegister dst, int shift) {
5893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5894 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5895 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5896 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5897 emit_int8(0x71);
5898 emit_int8((unsigned char)(0xC0 | encode));
5899 emit_int8(shift & 0xFF);
5900 }
5901
5902 void Assembler::psrad(XMMRegister dst, int shift) {
5903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5904 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5905 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5906 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5907 emit_int8(0x72);
5908 emit_int8((unsigned char)(0xC0 | encode));
5909 emit_int8(shift & 0xFF);
5910 }
5911
5912 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5913 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5915 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5916 emit_int8((unsigned char)0xE1);
5917 emit_int8((unsigned char)(0xC0 | encode));
5918 }
5919
5920 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5921 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5922 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5923 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5924 emit_int8((unsigned char)0xE2);
5925 emit_int8((unsigned char)(0xC0 | encode));
5926 }
5927
5928 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5929 assert(UseAVX > 0, "requires some form of AVX");
5930 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5931 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5932 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5933 emit_int8(0x71);
5934 emit_int8((unsigned char)(0xC0 | encode));
5935 emit_int8(shift & 0xFF);
5936 }
5937
5938 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5939 assert(UseAVX > 0, "requires some form of AVX");
5940 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5941 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5942 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5943 emit_int8(0x72);
5944 emit_int8((unsigned char)(0xC0 | encode));
5945 emit_int8(shift & 0xFF);
5946 }
5947
5948 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5949 assert(UseAVX > 0, "requires some form of AVX");
5950 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5951 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5952 emit_int8((unsigned char)0xE1);
5953 emit_int8((unsigned char)(0xC0 | encode));
5954 }
5955
5956 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5957 assert(UseAVX > 0, "requires some form of AVX");
5958 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5959 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5960 emit_int8((unsigned char)0xE2);
5961 emit_int8((unsigned char)(0xC0 | encode));
5962 }
5963
5964
5965 // logical operations packed integers
5966 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5967 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5968 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5969 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5970 emit_int8((unsigned char)0xDB);
5971 emit_int8((unsigned char)(0xC0 | encode));
5972 }
5973
5974 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5975 assert(UseAVX > 0, "requires some form of AVX");
5976 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5977 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5978 emit_int8((unsigned char)0xDB);
5979 emit_int8((unsigned char)(0xC0 | encode));
5980 }
5981
5982 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5983 assert(UseAVX > 0, "requires some form of AVX");
5984 InstructionMark im(this);
5985 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5986 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5987 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5988 emit_int8((unsigned char)0xDB);
5989 emit_operand(dst, src);
5990 }
5991
5992 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5993 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5994 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5995 attributes.set_rex_vex_w_reverted();
5996 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5997 emit_int8((unsigned char)0xDF);
5998 emit_int8((unsigned char)(0xC0 | encode));
5999 }
6000
6001 void Assembler::por(XMMRegister dst, XMMRegister src) {
6002 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6003 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6004 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6005 emit_int8((unsigned char)0xEB);
6006 emit_int8((unsigned char)(0xC0 | encode));
6007 }
6008
6009 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6010 assert(UseAVX > 0, "requires some form of AVX");
6011 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6012 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6013 emit_int8((unsigned char)0xEB);
6014 emit_int8((unsigned char)(0xC0 | encode));
6015 }
6016
6017 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6018 assert(UseAVX > 0, "requires some form of AVX");
6019 InstructionMark im(this);
6020 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6021 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6022 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6023 emit_int8((unsigned char)0xEB);
6024 emit_operand(dst, src);
6025 }
6026
6027 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6028 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6029 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6030 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6031 emit_int8((unsigned char)0xEF);
6032 emit_int8((unsigned char)(0xC0 | encode));
6033 }
6034
6035 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6036 assert(UseAVX > 0, "requires some form of AVX");
6037 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6038 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6039 emit_int8((unsigned char)0xEF);
6040 emit_int8((unsigned char)(0xC0 | encode));
6041 }
6042
6043 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6044 assert(UseAVX > 0, "requires some form of AVX");
6045 InstructionMark im(this);
6046 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6047 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6048 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6049 emit_int8((unsigned char)0xEF);
6050 emit_operand(dst, src);
6051 }
6052
6053
6054 // vinserti forms
6055
6056 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6057 assert(VM_Version::supports_avx2(), "");
6058 assert(imm8 <= 0x01, "imm8: %u", imm8);
6059 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6060 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6061 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6062 emit_int8(0x38);
6063 emit_int8((unsigned char)(0xC0 | encode));
6064 // 0x00 - insert into lower 128 bits
6065 // 0x01 - insert into upper 128 bits
6066 emit_int8(imm8 & 0x01);
6067 }
6068
6069 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6070 assert(VM_Version::supports_avx2(), "");
6071 assert(dst != xnoreg, "sanity");
6072 assert(imm8 <= 0x01, "imm8: %u", imm8);
6073 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6074 InstructionMark im(this);
6075 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6076 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6077 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6078 emit_int8(0x38);
6079 emit_operand(dst, src);
6080 // 0x00 - insert into lower 128 bits
6081 // 0x01 - insert into upper 128 bits
6082 emit_int8(imm8 & 0x01);
6083 }
6084
6085 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6086 assert(VM_Version::supports_evex(), "");
6087 assert(imm8 <= 0x03, "imm8: %u", imm8);
6088 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6089 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6090 emit_int8(0x38);
6091 emit_int8((unsigned char)(0xC0 | encode));
6092 // 0x00 - insert into q0 128 bits (0..127)
6093 // 0x01 - insert into q1 128 bits (128..255)
6094 // 0x02 - insert into q2 128 bits (256..383)
6095 // 0x03 - insert into q3 128 bits (384..511)
6096 emit_int8(imm8 & 0x03);
6097 }
6098
6099 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6100 assert(VM_Version::supports_avx(), "");
6101 assert(dst != xnoreg, "sanity");
6102 assert(imm8 <= 0x03, "imm8: %u", imm8);
6103 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6104 InstructionMark im(this);
6105 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6106 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6107 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6108 emit_int8(0x18);
6109 emit_operand(dst, src);
6110 // 0x00 - insert into q0 128 bits (0..127)
6111 // 0x01 - insert into q1 128 bits (128..255)
6112 // 0x02 - insert into q2 128 bits (256..383)
6113 // 0x03 - insert into q3 128 bits (384..511)
6114 emit_int8(imm8 & 0x03);
6115 }
6116
6117 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6118 assert(VM_Version::supports_evex(), "");
6119 assert(imm8 <= 0x01, "imm8: %u", imm8);
6120 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6121 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6122 emit_int8(0x38);
6123 emit_int8((unsigned char)(0xC0 | encode));
6124 // 0x00 - insert into lower 256 bits
6125 // 0x01 - insert into upper 256 bits
6126 emit_int8(imm8 & 0x01);
6127 }
6128
6129
6130 // vinsertf forms
6131
6132 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6133 assert(VM_Version::supports_avx(), "");
6134 assert(imm8 <= 0x01, "imm8: %u", imm8);
6135 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6136 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6137 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6138 emit_int8(0x18);
6139 emit_int8((unsigned char)(0xC0 | encode));
6140 // 0x00 - insert into lower 128 bits
6141 // 0x01 - insert into upper 128 bits
6142 emit_int8(imm8 & 0x01);
6143 }
6144
6145 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6146 assert(VM_Version::supports_avx(), "");
6147 assert(dst != xnoreg, "sanity");
6148 assert(imm8 <= 0x01, "imm8: %u", imm8);
6149 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6150 InstructionMark im(this);
6151 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6152 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6153 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6154 emit_int8(0x18);
6155 emit_operand(dst, src);
6156 // 0x00 - insert into lower 128 bits
6157 // 0x01 - insert into upper 128 bits
6158 emit_int8(imm8 & 0x01);
6159 }
6160
6161 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6162 assert(VM_Version::supports_evex(), "");
6163 assert(imm8 <= 0x03, "imm8: %u", imm8);
6164 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6165 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6166 emit_int8(0x18);
6167 emit_int8((unsigned char)(0xC0 | encode));
6168 // 0x00 - insert into q0 128 bits (0..127)
6169 // 0x01 - insert into q1 128 bits (128..255)
6170 // 0x02 - insert into q2 128 bits (256..383)
6171 // 0x03 - insert into q3 128 bits (384..511)
6172 emit_int8(imm8 & 0x03);
6173 }
6174
6175 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6176 assert(VM_Version::supports_avx(), "");
6177 assert(dst != xnoreg, "sanity");
6178 assert(imm8 <= 0x03, "imm8: %u", imm8);
6179 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6180 InstructionMark im(this);
6181 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6182 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6183 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6184 emit_int8(0x18);
6185 emit_operand(dst, src);
6186 // 0x00 - insert into q0 128 bits (0..127)
6187 // 0x01 - insert into q1 128 bits (128..255)
6188 // 0x02 - insert into q2 128 bits (256..383)
6189 // 0x03 - insert into q3 128 bits (384..511)
6190 emit_int8(imm8 & 0x03);
6191 }
6192
6193 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6194 assert(VM_Version::supports_evex(), "");
6195 assert(imm8 <= 0x01, "imm8: %u", imm8);
6196 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6197 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6198 emit_int8(0x1A);
6199 emit_int8((unsigned char)(0xC0 | encode));
6200 // 0x00 - insert into lower 256 bits
6201 // 0x01 - insert into upper 256 bits
6202 emit_int8(imm8 & 0x01);
6203 }
6204
6205 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6206 assert(VM_Version::supports_evex(), "");
6207 assert(dst != xnoreg, "sanity");
6208 assert(imm8 <= 0x01, "imm8: %u", imm8);
6209 InstructionMark im(this);
6210 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6211 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6212 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6213 emit_int8(0x1A);
6214 emit_operand(dst, src);
6215 // 0x00 - insert into lower 256 bits
6216 // 0x01 - insert into upper 256 bits
6217 emit_int8(imm8 & 0x01);
6218 }
6219
6220
6221 // vextracti forms
6222
6223 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6224 assert(VM_Version::supports_avx(), "");
6225 assert(imm8 <= 0x01, "imm8: %u", imm8);
6226 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6227 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6228 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6229 emit_int8(0x39);
6230 emit_int8((unsigned char)(0xC0 | encode));
6231 // 0x00 - extract from lower 128 bits
6232 // 0x01 - extract from upper 128 bits
6233 emit_int8(imm8 & 0x01);
6234 }
6235
6236 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6237 assert(VM_Version::supports_avx2(), "");
6238 assert(src != xnoreg, "sanity");
6239 assert(imm8 <= 0x01, "imm8: %u", imm8);
6240 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6241 InstructionMark im(this);
6242 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6243 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6244 attributes.reset_is_clear_context();
6245 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6246 emit_int8(0x39);
6247 emit_operand(src, dst);
6248 // 0x00 - extract from lower 128 bits
6249 // 0x01 - extract from upper 128 bits
6250 emit_int8(imm8 & 0x01);
6251 }
6252
6253 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6254 assert(VM_Version::supports_avx(), "");
6255 assert(imm8 <= 0x03, "imm8: %u", imm8);
6256 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6257 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6258 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6259 emit_int8(0x39);
6260 emit_int8((unsigned char)(0xC0 | encode));
6261 // 0x00 - extract from bits 127:0
6262 // 0x01 - extract from bits 255:128
6263 // 0x02 - extract from bits 383:256
6264 // 0x03 - extract from bits 511:384
6265 emit_int8(imm8 & 0x03);
6266 }
6267
6268 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6269 assert(VM_Version::supports_evex(), "");
6270 assert(src != xnoreg, "sanity");
6271 assert(imm8 <= 0x03, "imm8: %u", imm8);
6272 InstructionMark im(this);
6273 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6274 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6275 attributes.reset_is_clear_context();
6276 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6277 emit_int8(0x39);
6278 emit_operand(src, dst);
6279 // 0x00 - extract from bits 127:0
6280 // 0x01 - extract from bits 255:128
6281 // 0x02 - extract from bits 383:256
6282 // 0x03 - extract from bits 511:384
6283 emit_int8(imm8 & 0x03);
6284 }
6285
6286 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6287 assert(VM_Version::supports_avx512dq(), "");
6288 assert(imm8 <= 0x03, "imm8: %u", imm8);
6289 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6290 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6291 emit_int8(0x39);
6292 emit_int8((unsigned char)(0xC0 | encode));
6293 // 0x00 - extract from bits 127:0
6294 // 0x01 - extract from bits 255:128
6295 // 0x02 - extract from bits 383:256
6296 // 0x03 - extract from bits 511:384
6297 emit_int8(imm8 & 0x03);
6298 }
6299
6300 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6301 assert(VM_Version::supports_evex(), "");
6302 assert(imm8 <= 0x01, "imm8: %u", imm8);
6303 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6304 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6305 emit_int8(0x3B);
6306 emit_int8((unsigned char)(0xC0 | encode));
6307 // 0x00 - extract from lower 256 bits
6308 // 0x01 - extract from upper 256 bits
6309 emit_int8(imm8 & 0x01);
6310 }
6311
6312
6313 // vextractf forms
6314
6315 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6316 assert(VM_Version::supports_avx(), "");
6317 assert(imm8 <= 0x01, "imm8: %u", imm8);
6318 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6319 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6320 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6321 emit_int8(0x19);
6322 emit_int8((unsigned char)(0xC0 | encode));
6323 // 0x00 - extract from lower 128 bits
6324 // 0x01 - extract from upper 128 bits
6325 emit_int8(imm8 & 0x01);
6326 }
6327
6328 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6329 assert(VM_Version::supports_avx(), "");
6330 assert(src != xnoreg, "sanity");
6331 assert(imm8 <= 0x01, "imm8: %u", imm8);
6332 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6333 InstructionMark im(this);
6334 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6335 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6336 attributes.reset_is_clear_context();
6337 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6338 emit_int8(0x19);
6339 emit_operand(src, dst);
6340 // 0x00 - extract from lower 128 bits
6341 // 0x01 - extract from upper 128 bits
6342 emit_int8(imm8 & 0x01);
6343 }
6344
6345 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6346 assert(VM_Version::supports_avx(), "");
6347 assert(imm8 <= 0x03, "imm8: %u", imm8);
6348 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6349 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6350 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6351 emit_int8(0x19);
6352 emit_int8((unsigned char)(0xC0 | encode));
6353 // 0x00 - extract from bits 127:0
6354 // 0x01 - extract from bits 255:128
6355 // 0x02 - extract from bits 383:256
6356 // 0x03 - extract from bits 511:384
6357 emit_int8(imm8 & 0x03);
6358 }
6359
6360 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6361 assert(VM_Version::supports_evex(), "");
6362 assert(src != xnoreg, "sanity");
6363 assert(imm8 <= 0x03, "imm8: %u", imm8);
6364 InstructionMark im(this);
6365 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6366 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6367 attributes.reset_is_clear_context();
6368 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6369 emit_int8(0x19);
6370 emit_operand(src, dst);
6371 // 0x00 - extract from bits 127:0
6372 // 0x01 - extract from bits 255:128
6373 // 0x02 - extract from bits 383:256
6374 // 0x03 - extract from bits 511:384
6375 emit_int8(imm8 & 0x03);
6376 }
6377
6378 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6379 assert(VM_Version::supports_avx512dq(), "");
6380 assert(imm8 <= 0x03, "imm8: %u", imm8);
6381 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6382 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6383 emit_int8(0x19);
6384 emit_int8((unsigned char)(0xC0 | encode));
6385 // 0x00 - extract from bits 127:0
6386 // 0x01 - extract from bits 255:128
6387 // 0x02 - extract from bits 383:256
6388 // 0x03 - extract from bits 511:384
6389 emit_int8(imm8 & 0x03);
6390 }
6391
6392 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6393 assert(VM_Version::supports_evex(), "");
6394 assert(imm8 <= 0x01, "imm8: %u", imm8);
6395 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6396 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6397 emit_int8(0x1B);
6398 emit_int8((unsigned char)(0xC0 | encode));
6399 // 0x00 - extract from lower 256 bits
6400 // 0x01 - extract from upper 256 bits
6401 emit_int8(imm8 & 0x01);
6402 }
6403
6404 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6405 assert(VM_Version::supports_evex(), "");
6406 assert(src != xnoreg, "sanity");
6407 assert(imm8 <= 0x01, "imm8: %u", imm8);
6408 InstructionMark im(this);
6409 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6410 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6411 attributes.reset_is_clear_context();
6412 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6413 emit_int8(0x1B);
6414 emit_operand(src, dst);
6415 // 0x00 - extract from lower 256 bits
6416 // 0x01 - extract from upper 256 bits
6417 emit_int8(imm8 & 0x01);
6418 }
6419
6420
6421 // legacy word/dword replicate
6422 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6423 assert(VM_Version::supports_avx2(), "");
6424 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6425 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6426 emit_int8(0x79);
6427 emit_int8((unsigned char)(0xC0 | encode));
6428 }
6429
6430 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6431 assert(VM_Version::supports_avx2(), "");
6432 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6433 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6434 emit_int8(0x58);
6435 emit_int8((unsigned char)(0xC0 | encode));
6436 }
6437
6438
6439 // xmm/mem sourced byte/word/dword/qword replicate
6440
6441 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6442 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6443 assert(VM_Version::supports_evex(), "");
6444 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6445 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6446 emit_int8(0x78);
6447 emit_int8((unsigned char)(0xC0 | encode));
6448 }
6449
6450 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6451 assert(VM_Version::supports_evex(), "");
6452 assert(dst != xnoreg, "sanity");
6453 InstructionMark im(this);
6454 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6455 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6456 // swap src<->dst for encoding
6457 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6458 emit_int8(0x78);
6459 emit_operand(dst, src);
6460 }
6461
6462 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6463 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6464 assert(VM_Version::supports_evex(), "");
6465 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6466 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6467 emit_int8(0x79);
6468 emit_int8((unsigned char)(0xC0 | encode));
6469 }
6470
6471 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6472 assert(VM_Version::supports_evex(), "");
6473 assert(dst != xnoreg, "sanity");
6474 InstructionMark im(this);
6475 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6476 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6477 // swap src<->dst for encoding
6478 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6479 emit_int8(0x79);
6480 emit_operand(dst, src);
6481 }
6482
6483 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6484 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6485 assert(VM_Version::supports_evex(), "");
6486 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6487 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6488 emit_int8(0x58);
6489 emit_int8((unsigned char)(0xC0 | encode));
6490 }
6491
6492 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6493 assert(VM_Version::supports_evex(), "");
6494 assert(dst != xnoreg, "sanity");
6495 InstructionMark im(this);
6496 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6497 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6498 // swap src<->dst for encoding
6499 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6500 emit_int8(0x58);
6501 emit_operand(dst, src);
6502 }
6503
6504 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6505 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6506 assert(VM_Version::supports_evex(), "");
6507 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6508 attributes.set_rex_vex_w_reverted();
6509 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6510 emit_int8(0x59);
6511 emit_int8((unsigned char)(0xC0 | encode));
6512 }
6513
6514 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6515 assert(VM_Version::supports_evex(), "");
6516 assert(dst != xnoreg, "sanity");
6517 InstructionMark im(this);
6518 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6519 attributes.set_rex_vex_w_reverted();
6520 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6521 // swap src<->dst for encoding
6522 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6523 emit_int8(0x59);
6524 emit_operand(dst, src);
6525 }
6526
6527
6528 // scalar single/double precision replicate
6529
6530 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6531 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6532 assert(VM_Version::supports_evex(), "");
6533 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6534 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6535 emit_int8(0x18);
6536 emit_int8((unsigned char)(0xC0 | encode));
6537 }
6538
6539 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6540 assert(VM_Version::supports_evex(), "");
6541 assert(dst != xnoreg, "sanity");
6542 InstructionMark im(this);
6543 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6544 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6545 // swap src<->dst for encoding
6546 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6547 emit_int8(0x18);
6548 emit_operand(dst, src);
6549 }
6550
6551 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6552 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6553 assert(VM_Version::supports_evex(), "");
6554 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6555 attributes.set_rex_vex_w_reverted();
6556 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6557 emit_int8(0x19);
6558 emit_int8((unsigned char)(0xC0 | encode));
6559 }
6560
6561 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6562 assert(VM_Version::supports_evex(), "");
6563 assert(dst != xnoreg, "sanity");
6564 InstructionMark im(this);
6565 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6566 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6567 attributes.set_rex_vex_w_reverted();
6568 // swap src<->dst for encoding
6569 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6570 emit_int8(0x19);
6571 emit_operand(dst, src);
6572 }
6573
6574
6575 // gpr source broadcast forms
6576
6577 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6578 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6579 assert(VM_Version::supports_evex(), "");
6580 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6581 attributes.set_is_evex_instruction();
6582 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6583 emit_int8(0x7A);
6584 emit_int8((unsigned char)(0xC0 | encode));
6585 }
6586
6587 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6588 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6589 assert(VM_Version::supports_evex(), "");
6590 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6591 attributes.set_is_evex_instruction();
6592 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6593 emit_int8(0x7B);
6594 emit_int8((unsigned char)(0xC0 | encode));
6595 }
6596
6597 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6598 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6599 assert(VM_Version::supports_evex(), "");
6600 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6601 attributes.set_is_evex_instruction();
6602 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6603 emit_int8(0x7C);
6604 emit_int8((unsigned char)(0xC0 | encode));
6605 }
6606
6607 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6608 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6609 assert(VM_Version::supports_evex(), "");
6610 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6611 attributes.set_is_evex_instruction();
6612 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6613 emit_int8(0x7C);
6614 emit_int8((unsigned char)(0xC0 | encode));
6615 }
6616
6617
6618 // Carry-Less Multiplication Quadword
6619 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6620 assert(VM_Version::supports_clmul(), "");
6621 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6622 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6623 emit_int8(0x44);
6624 emit_int8((unsigned char)(0xC0 | encode));
6625 emit_int8((unsigned char)mask);
6626 }
6627
6628 // Carry-Less Multiplication Quadword
6629 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6630 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6631 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6632 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6633 emit_int8(0x44);
6634 emit_int8((unsigned char)(0xC0 | encode));
6635 emit_int8((unsigned char)mask);
6636 }
6637
6638 void Assembler::vzeroupper() {
6639 if (VM_Version::supports_vzeroupper()) {
6640 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6641 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6642 emit_int8(0x77);
6643 }
6644 }
6645
6646 #ifndef _LP64
6647 // 32bit only pieces of the assembler
6648
6649 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6650 // NO PREFIX AS NEVER 64BIT
6651 InstructionMark im(this);
6652 emit_int8((unsigned char)0x81);
6653 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6654 emit_data(imm32, rspec, 0);
6655 }
6656
6657 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6658 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6659 InstructionMark im(this);
6660 emit_int8((unsigned char)0x81);
6661 emit_operand(rdi, src1);
6662 emit_data(imm32, rspec, 0);
6663 }
6664
6665 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6666 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6667 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6668 void Assembler::cmpxchg8(Address adr) {
6669 InstructionMark im(this);
6670 emit_int8(0x0F);
6671 emit_int8((unsigned char)0xC7);
6672 emit_operand(rcx, adr);
6673 }
6674
6675 void Assembler::decl(Register dst) {
6676 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6677 emit_int8(0x48 | dst->encoding());
6678 }
6679
6680 #endif // _LP64
6681
6682 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6683
6684 void Assembler::fabs() {
6685 emit_int8((unsigned char)0xD9);
6686 emit_int8((unsigned char)0xE1);
6687 }
6688
6689 void Assembler::fadd(int i) {
6690 emit_farith(0xD8, 0xC0, i);
6691 }
6692
6693 void Assembler::fadd_d(Address src) {
6694 InstructionMark im(this);
6695 emit_int8((unsigned char)0xDC);
6696 emit_operand32(rax, src);
6697 }
6698
6699 void Assembler::fadd_s(Address src) {
6700 InstructionMark im(this);
6701 emit_int8((unsigned char)0xD8);
6702 emit_operand32(rax, src);
6703 }
6704
6705 void Assembler::fadda(int i) {
6706 emit_farith(0xDC, 0xC0, i);
6707 }
6708
6709 void Assembler::faddp(int i) {
6710 emit_farith(0xDE, 0xC0, i);
6711 }
6712
6713 void Assembler::fchs() {
6714 emit_int8((unsigned char)0xD9);
6715 emit_int8((unsigned char)0xE0);
6716 }
6717
6718 void Assembler::fcom(int i) {
6719 emit_farith(0xD8, 0xD0, i);
6720 }
6721
6722 void Assembler::fcomp(int i) {
6723 emit_farith(0xD8, 0xD8, i);
6724 }
6725
6726 void Assembler::fcomp_d(Address src) {
6727 InstructionMark im(this);
6728 emit_int8((unsigned char)0xDC);
6729 emit_operand32(rbx, src);
6730 }
6731
6732 void Assembler::fcomp_s(Address src) {
6733 InstructionMark im(this);
6734 emit_int8((unsigned char)0xD8);
6735 emit_operand32(rbx, src);
6736 }
6737
6738 void Assembler::fcompp() {
6739 emit_int8((unsigned char)0xDE);
6740 emit_int8((unsigned char)0xD9);
6741 }
6742
6743 void Assembler::fcos() {
6744 emit_int8((unsigned char)0xD9);
6745 emit_int8((unsigned char)0xFF);
6746 }
6747
6748 void Assembler::fdecstp() {
6749 emit_int8((unsigned char)0xD9);
6750 emit_int8((unsigned char)0xF6);
6751 }
6752
6753 void Assembler::fdiv(int i) {
6754 emit_farith(0xD8, 0xF0, i);
6755 }
6756
6757 void Assembler::fdiv_d(Address src) {
6758 InstructionMark im(this);
6759 emit_int8((unsigned char)0xDC);
6760 emit_operand32(rsi, src);
6761 }
6762
6763 void Assembler::fdiv_s(Address src) {
6764 InstructionMark im(this);
6765 emit_int8((unsigned char)0xD8);
6766 emit_operand32(rsi, src);
6767 }
6768
6769 void Assembler::fdiva(int i) {
6770 emit_farith(0xDC, 0xF8, i);
6771 }
6772
6773 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6774 // is erroneous for some of the floating-point instructions below.
6775
6776 void Assembler::fdivp(int i) {
6777 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6778 }
6779
6780 void Assembler::fdivr(int i) {
6781 emit_farith(0xD8, 0xF8, i);
6782 }
6783
6784 void Assembler::fdivr_d(Address src) {
6785 InstructionMark im(this);
6786 emit_int8((unsigned char)0xDC);
6787 emit_operand32(rdi, src);
6788 }
6789
6790 void Assembler::fdivr_s(Address src) {
6791 InstructionMark im(this);
6792 emit_int8((unsigned char)0xD8);
6793 emit_operand32(rdi, src);
6794 }
6795
6796 void Assembler::fdivra(int i) {
6797 emit_farith(0xDC, 0xF0, i);
6798 }
6799
6800 void Assembler::fdivrp(int i) {
6801 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6802 }
6803
6804 void Assembler::ffree(int i) {
6805 emit_farith(0xDD, 0xC0, i);
6806 }
6807
6808 void Assembler::fild_d(Address adr) {
6809 InstructionMark im(this);
6810 emit_int8((unsigned char)0xDF);
6811 emit_operand32(rbp, adr);
6812 }
6813
6814 void Assembler::fild_s(Address adr) {
6815 InstructionMark im(this);
6816 emit_int8((unsigned char)0xDB);
6817 emit_operand32(rax, adr);
6818 }
6819
6820 void Assembler::fincstp() {
6821 emit_int8((unsigned char)0xD9);
6822 emit_int8((unsigned char)0xF7);
6823 }
6824
6825 void Assembler::finit() {
6826 emit_int8((unsigned char)0x9B);
6827 emit_int8((unsigned char)0xDB);
6828 emit_int8((unsigned char)0xE3);
6829 }
6830
6831 void Assembler::fist_s(Address adr) {
6832 InstructionMark im(this);
6833 emit_int8((unsigned char)0xDB);
6834 emit_operand32(rdx, adr);
6835 }
6836
6837 void Assembler::fistp_d(Address adr) {
6838 InstructionMark im(this);
6839 emit_int8((unsigned char)0xDF);
6840 emit_operand32(rdi, adr);
6841 }
6842
6843 void Assembler::fistp_s(Address adr) {
6844 InstructionMark im(this);
6845 emit_int8((unsigned char)0xDB);
6846 emit_operand32(rbx, adr);
6847 }
6848
6849 void Assembler::fld1() {
6850 emit_int8((unsigned char)0xD9);
6851 emit_int8((unsigned char)0xE8);
6852 }
6853
6854 void Assembler::fld_d(Address adr) {
6855 InstructionMark im(this);
6856 emit_int8((unsigned char)0xDD);
6857 emit_operand32(rax, adr);
6858 }
6859
6860 void Assembler::fld_s(Address adr) {
6861 InstructionMark im(this);
6862 emit_int8((unsigned char)0xD9);
6863 emit_operand32(rax, adr);
6864 }
6865
6866
6867 void Assembler::fld_s(int index) {
6868 emit_farith(0xD9, 0xC0, index);
6869 }
6870
6871 void Assembler::fld_x(Address adr) {
6872 InstructionMark im(this);
6873 emit_int8((unsigned char)0xDB);
6874 emit_operand32(rbp, adr);
6875 }
6876
6877 void Assembler::fldcw(Address src) {
6878 InstructionMark im(this);
6879 emit_int8((unsigned char)0xD9);
6880 emit_operand32(rbp, src);
6881 }
6882
6883 void Assembler::fldenv(Address src) {
6884 InstructionMark im(this);
6885 emit_int8((unsigned char)0xD9);
6886 emit_operand32(rsp, src);
6887 }
6888
6889 void Assembler::fldlg2() {
6890 emit_int8((unsigned char)0xD9);
6891 emit_int8((unsigned char)0xEC);
6892 }
6893
6894 void Assembler::fldln2() {
6895 emit_int8((unsigned char)0xD9);
6896 emit_int8((unsigned char)0xED);
6897 }
6898
6899 void Assembler::fldz() {
6900 emit_int8((unsigned char)0xD9);
6901 emit_int8((unsigned char)0xEE);
6902 }
6903
6904 void Assembler::flog() {
6905 fldln2();
6906 fxch();
6907 fyl2x();
6908 }
6909
6910 void Assembler::flog10() {
6911 fldlg2();
6912 fxch();
6913 fyl2x();
6914 }
6915
6916 void Assembler::fmul(int i) {
6917 emit_farith(0xD8, 0xC8, i);
6918 }
6919
6920 void Assembler::fmul_d(Address src) {
6921 InstructionMark im(this);
6922 emit_int8((unsigned char)0xDC);
6923 emit_operand32(rcx, src);
6924 }
6925
6926 void Assembler::fmul_s(Address src) {
6927 InstructionMark im(this);
6928 emit_int8((unsigned char)0xD8);
6929 emit_operand32(rcx, src);
6930 }
6931
6932 void Assembler::fmula(int i) {
6933 emit_farith(0xDC, 0xC8, i);
6934 }
6935
6936 void Assembler::fmulp(int i) {
6937 emit_farith(0xDE, 0xC8, i);
6938 }
6939
6940 void Assembler::fnsave(Address dst) {
6941 InstructionMark im(this);
6942 emit_int8((unsigned char)0xDD);
6943 emit_operand32(rsi, dst);
6944 }
6945
6946 void Assembler::fnstcw(Address src) {
6947 InstructionMark im(this);
6948 emit_int8((unsigned char)0x9B);
6949 emit_int8((unsigned char)0xD9);
6950 emit_operand32(rdi, src);
6951 }
6952
6953 void Assembler::fnstsw_ax() {
6954 emit_int8((unsigned char)0xDF);
6955 emit_int8((unsigned char)0xE0);
6956 }
6957
6958 void Assembler::fprem() {
6959 emit_int8((unsigned char)0xD9);
6960 emit_int8((unsigned char)0xF8);
6961 }
6962
6963 void Assembler::fprem1() {
6964 emit_int8((unsigned char)0xD9);
6965 emit_int8((unsigned char)0xF5);
6966 }
6967
6968 void Assembler::frstor(Address src) {
6969 InstructionMark im(this);
6970 emit_int8((unsigned char)0xDD);
6971 emit_operand32(rsp, src);
6972 }
6973
6974 void Assembler::fsin() {
6975 emit_int8((unsigned char)0xD9);
6976 emit_int8((unsigned char)0xFE);
6977 }
6978
6979 void Assembler::fsqrt() {
6980 emit_int8((unsigned char)0xD9);
6981 emit_int8((unsigned char)0xFA);
6982 }
6983
6984 void Assembler::fst_d(Address adr) {
6985 InstructionMark im(this);
6986 emit_int8((unsigned char)0xDD);
6987 emit_operand32(rdx, adr);
6988 }
6989
6990 void Assembler::fst_s(Address adr) {
6991 InstructionMark im(this);
6992 emit_int8((unsigned char)0xD9);
6993 emit_operand32(rdx, adr);
6994 }
6995
6996 void Assembler::fstp_d(Address adr) {
6997 InstructionMark im(this);
6998 emit_int8((unsigned char)0xDD);
6999 emit_operand32(rbx, adr);
7000 }
7001
7002 void Assembler::fstp_d(int index) {
7003 emit_farith(0xDD, 0xD8, index);
7004 }
7005
7006 void Assembler::fstp_s(Address adr) {
7007 InstructionMark im(this);
7008 emit_int8((unsigned char)0xD9);
7009 emit_operand32(rbx, adr);
7010 }
7011
7012 void Assembler::fstp_x(Address adr) {
7013 InstructionMark im(this);
7014 emit_int8((unsigned char)0xDB);
7015 emit_operand32(rdi, adr);
7016 }
7017
7018 void Assembler::fsub(int i) {
7019 emit_farith(0xD8, 0xE0, i);
7020 }
7021
7022 void Assembler::fsub_d(Address src) {
7023 InstructionMark im(this);
7024 emit_int8((unsigned char)0xDC);
7025 emit_operand32(rsp, src);
7026 }
7027
7028 void Assembler::fsub_s(Address src) {
7029 InstructionMark im(this);
7030 emit_int8((unsigned char)0xD8);
7031 emit_operand32(rsp, src);
7032 }
7033
7034 void Assembler::fsuba(int i) {
7035 emit_farith(0xDC, 0xE8, i);
7036 }
7037
7038 void Assembler::fsubp(int i) {
7039 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
7040 }
7041
7042 void Assembler::fsubr(int i) {
7043 emit_farith(0xD8, 0xE8, i);
7044 }
7045
7046 void Assembler::fsubr_d(Address src) {
7047 InstructionMark im(this);
7048 emit_int8((unsigned char)0xDC);
7049 emit_operand32(rbp, src);
7050 }
7051
7052 void Assembler::fsubr_s(Address src) {
7053 InstructionMark im(this);
7054 emit_int8((unsigned char)0xD8);
7055 emit_operand32(rbp, src);
7056 }
7057
7058 void Assembler::fsubra(int i) {
7059 emit_farith(0xDC, 0xE0, i);
7060 }
7061
7062 void Assembler::fsubrp(int i) {
7063 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7064 }
7065
7066 void Assembler::ftan() {
7067 emit_int8((unsigned char)0xD9);
7068 emit_int8((unsigned char)0xF2);
7069 emit_int8((unsigned char)0xDD);
7070 emit_int8((unsigned char)0xD8);
7071 }
7072
7073 void Assembler::ftst() {
7074 emit_int8((unsigned char)0xD9);
7075 emit_int8((unsigned char)0xE4);
7076 }
7077
7078 void Assembler::fucomi(int i) {
7079 // make sure the instruction is supported (introduced for P6, together with cmov)
7080 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7081 emit_farith(0xDB, 0xE8, i);
7082 }
7083
7084 void Assembler::fucomip(int i) {
7085 // make sure the instruction is supported (introduced for P6, together with cmov)
7086 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7087 emit_farith(0xDF, 0xE8, i);
7088 }
7089
7090 void Assembler::fwait() {
7091 emit_int8((unsigned char)0x9B);
7092 }
7093
7094 void Assembler::fxch(int i) {
7095 emit_farith(0xD9, 0xC8, i);
7096 }
7097
7098 void Assembler::fyl2x() {
7099 emit_int8((unsigned char)0xD9);
7100 emit_int8((unsigned char)0xF1);
7101 }
7102
7103 void Assembler::frndint() {
7104 emit_int8((unsigned char)0xD9);
7105 emit_int8((unsigned char)0xFC);
7106 }
7107
7108 void Assembler::f2xm1() {
7109 emit_int8((unsigned char)0xD9);
7110 emit_int8((unsigned char)0xF0);
7111 }
7112
7113 void Assembler::fldl2e() {
7114 emit_int8((unsigned char)0xD9);
7115 emit_int8((unsigned char)0xEA);
7116 }
7117
7118 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7119 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7120 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7121 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7122
7123 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7124 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7125 if (pre > 0) {
7126 emit_int8(simd_pre[pre]);
7127 }
7128 if (rex_w) {
7129 prefixq(adr, xreg);
7130 } else {
7131 prefix(adr, xreg);
7132 }
7133 if (opc > 0) {
7134 emit_int8(0x0F);
7135 int opc2 = simd_opc[opc];
7136 if (opc2 > 0) {
7137 emit_int8(opc2);
7138 }
7139 }
7140 }
7141
7142 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7143 if (pre > 0) {
7144 emit_int8(simd_pre[pre]);
7145 }
7146 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7147 if (opc > 0) {
7148 emit_int8(0x0F);
7149 int opc2 = simd_opc[opc];
7150 if (opc2 > 0) {
7151 emit_int8(opc2);
7152 }
7153 }
7154 return encode;
7155 }
7156
7157
7158 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7159 int vector_len = _attributes->get_vector_len();
7160 bool vex_w = _attributes->is_rex_vex_w();
7161 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7162 prefix(VEX_3bytes);
7163
7164 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7165 byte1 = (~byte1) & 0xE0;
7166 byte1 |= opc;
7167 emit_int8(byte1);
7168
7169 int byte2 = ((~nds_enc) & 0xf) << 3;
7170 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7171 emit_int8(byte2);
7172 } else {
7173 prefix(VEX_2bytes);
7174
7175 int byte1 = vex_r ? VEX_R : 0;
7176 byte1 = (~byte1) & 0x80;
7177 byte1 |= ((~nds_enc) & 0xf) << 3;
7178 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7179 emit_int8(byte1);
7180 }
7181 }
7182
7183 // This is a 4 byte encoding
7184 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7185 // EVEX 0x62 prefix
7186 prefix(EVEX_4bytes);
7187 bool vex_w = _attributes->is_rex_vex_w();
7188 int evex_encoding = (vex_w ? VEX_W : 0);
7189 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7190 _attributes->set_evex_encoding(evex_encoding);
7191
7192 // P0: byte 2, initialized to RXBR`00mm
7193 // instead of not'd
7194 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7195 byte2 = (~byte2) & 0xF0;
7196 // confine opc opcode extensions in mm bits to lower two bits
7197 // of form {0F, 0F_38, 0F_3A}
7198 byte2 |= opc;
7199 emit_int8(byte2);
7200
7201 // P1: byte 3 as Wvvvv1pp
7202 int byte3 = ((~nds_enc) & 0xf) << 3;
7203 // p[10] is always 1
7204 byte3 |= EVEX_F;
7205 byte3 |= (vex_w & 1) << 7;
7206 // confine pre opcode extensions in pp bits to lower two bits
7207 // of form {66, F3, F2}
7208 byte3 |= pre;
7209 emit_int8(byte3);
7210
7211 // P2: byte 4 as zL'Lbv'aaa
7212 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
7213 int byte4 = (_attributes->is_no_reg_mask()) ?
7214 0 :
7215 _attributes->get_embedded_opmask_register_specifier();
7216 // EVEX.v` for extending EVEX.vvvv or VIDX
7217 byte4 |= (evex_v ? 0: EVEX_V);
7218 // third EXEC.b for broadcast actions
7219 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7220 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7221 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7222 // last is EVEX.z for zero/merge actions
7223 if (_attributes->is_no_reg_mask() == false) {
7224 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7225 }
7226 emit_int8(byte4);
7227 }
7228
7229 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7230 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7231 bool vex_b = adr.base_needs_rex();
7232 bool vex_x = adr.index_needs_rex();
7233 set_attributes(attributes);
7234 attributes->set_current_assembler(this);
7235
7236 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7237 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7238 switch (attributes->get_vector_len()) {
7239 case AVX_128bit:
7240 case AVX_256bit:
7241 attributes->set_is_legacy_mode();
7242 break;
7243 }
7244 }
7245
7246 // For pure EVEX check and see if this instruction
7247 // is allowed in legacy mode and has resources which will
7248 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7249 // else that field is set when we encode to EVEX
7250 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7251 !_is_managed && !attributes->is_evex_instruction()) {
7252 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7253 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7254 if (check_register_bank) {
7255 // check nds_enc and xreg_enc for upper bank usage
7256 if (nds_enc < 16 && xreg_enc < 16) {
7257 attributes->set_is_legacy_mode();
7258 }
7259 } else {
7260 attributes->set_is_legacy_mode();
7261 }
7262 }
7263 }
7264
7265 _is_managed = false;
7266 if (UseAVX > 2 && !attributes->is_legacy_mode())
7267 {
7268 bool evex_r = (xreg_enc >= 16);
7269 bool evex_v = (nds_enc >= 16);
7270 attributes->set_is_evex_instruction();
7271 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7272 } else {
7273 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7274 attributes->set_rex_vex_w(false);
7275 }
7276 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7277 }
7278 }
7279
7280 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7281 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7282 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7283 bool vex_x = false;
7284 set_attributes(attributes);
7285 attributes->set_current_assembler(this);
7286 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7287
7288 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7289 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7290 switch (attributes->get_vector_len()) {
7291 case AVX_128bit:
7292 case AVX_256bit:
7293 if (check_register_bank) {
7294 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
7295 // up propagate arithmetic instructions to meet RA requirements
7296 attributes->set_vector_len(AVX_512bit);
7297 } else {
7298 attributes->set_is_legacy_mode();
7299 }
7300 } else {
7301 attributes->set_is_legacy_mode();
7302 }
7303 break;
7304 }
7305 }
7306
7307 // For pure EVEX check and see if this instruction
7308 // is allowed in legacy mode and has resources which will
7309 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7310 // else that field is set when we encode to EVEX
7311 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7312 !_is_managed && !attributes->is_evex_instruction()) {
7313 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7314 if (check_register_bank) {
7315 // check dst_enc, nds_enc and src_enc for upper bank usage
7316 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
7317 attributes->set_is_legacy_mode();
7318 }
7319 } else {
7320 attributes->set_is_legacy_mode();
7321 }
7322 }
7323 }
7324
7325 _is_managed = false;
7326 if (UseAVX > 2 && !attributes->is_legacy_mode())
7327 {
7328 bool evex_r = (dst_enc >= 16);
7329 bool evex_v = (nds_enc >= 16);
7330 // can use vex_x as bank extender on rm encoding
7331 vex_x = (src_enc >= 16);
7332 attributes->set_is_evex_instruction();
7333 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7334 } else {
7335 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7336 attributes->set_rex_vex_w(false);
7337 }
7338 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7339 }
7340
7341 // return modrm byte components for operands
7342 return (((dst_enc & 7) << 3) | (src_enc & 7));
7343 }
7344
7345
7346 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7347 VexOpcode opc, InstructionAttr *attributes) {
7348 if (UseAVX > 0) {
7349 int xreg_enc = xreg->encoding();
7350 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7351 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7352 } else {
7353 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7354 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7355 }
7356 }
7357
7358 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7359 VexOpcode opc, InstructionAttr *attributes) {
7360 int dst_enc = dst->encoding();
7361 int src_enc = src->encoding();
7362 if (UseAVX > 0) {
7363 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7364 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7365 } else {
7366 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7367 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7368 }
7369 }
7370
7371 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7372 assert(VM_Version::supports_avx(), "");
7373 assert(!VM_Version::supports_evex(), "");
7374 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7375 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7376 emit_int8((unsigned char)0xC2);
7377 emit_int8((unsigned char)(0xC0 | encode));
7378 emit_int8((unsigned char)(0xF & cop));
7379 }
7380
7381 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7382 assert(VM_Version::supports_avx(), "");
7383 assert(!VM_Version::supports_evex(), "");
7384 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7385 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7386 emit_int8((unsigned char)0x4B);
7387 emit_int8((unsigned char)(0xC0 | encode));
7388 int src2_enc = src2->encoding();
7389 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7390 }
7391
7392 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
7393 assert(VM_Version::supports_avx2(), "");
7394 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7395 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7396 emit_int8((unsigned char)0x02);
7397 emit_int8((unsigned char)(0xC0 | encode));
7398 emit_int8((unsigned char)imm8);
7399 }
7400
7401 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7402 assert(VM_Version::supports_bmi2(), "");
7403 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7404 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7405 emit_int8((unsigned char)0xF7);
7406 emit_int8((unsigned char)(0xC0 | encode));
7407 }
7408
7409 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7410 assert(VM_Version::supports_bmi2(), "");
7411 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7412 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7413 emit_int8((unsigned char)0xF7);
7414 emit_int8((unsigned char)(0xC0 | encode));
7415 }
7416
7417 #ifndef _LP64
7418
7419 void Assembler::incl(Register dst) {
7420 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7421 emit_int8(0x40 | dst->encoding());
7422 }
7423
7424 void Assembler::lea(Register dst, Address src) {
7425 leal(dst, src);
7426 }
7427
7428 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7429 InstructionMark im(this);
7430 emit_int8((unsigned char)0xC7);
7431 emit_operand(rax, dst);
7432 emit_data((int)imm32, rspec, 0);
7433 }
7434
7435 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7436 InstructionMark im(this);
7437 int encode = prefix_and_encode(dst->encoding());
7438 emit_int8((unsigned char)(0xB8 | encode));
7439 emit_data((int)imm32, rspec, 0);
7440 }
7441
7442 void Assembler::popa() { // 32bit
7443 emit_int8(0x61);
7444 }
7445
7446 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7447 InstructionMark im(this);
7448 emit_int8(0x68);
7449 emit_data(imm32, rspec, 0);
7450 }
7451
7452 void Assembler::pusha() { // 32bit
7453 emit_int8(0x60);
7454 }
7455
7456 void Assembler::set_byte_if_not_zero(Register dst) {
7457 emit_int8(0x0F);
7458 emit_int8((unsigned char)0x95);
7459 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7460 }
7461
7462 void Assembler::shldl(Register dst, Register src) {
7463 emit_int8(0x0F);
7464 emit_int8((unsigned char)0xA5);
7465 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7466 }
7467
7468 // 0F A4 / r ib
7469 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7470 emit_int8(0x0F);
7471 emit_int8((unsigned char)0xA4);
7472 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7473 emit_int8(imm8);
7474 }
7475
7476 void Assembler::shrdl(Register dst, Register src) {
7477 emit_int8(0x0F);
7478 emit_int8((unsigned char)0xAD);
7479 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7480 }
7481
7482 #else // LP64
7483
7484 void Assembler::set_byte_if_not_zero(Register dst) {
7485 int enc = prefix_and_encode(dst->encoding(), true);
7486 emit_int8(0x0F);
7487 emit_int8((unsigned char)0x95);
7488 emit_int8((unsigned char)(0xE0 | enc));
7489 }
7490
7491 // 64bit only pieces of the assembler
7492 // This should only be used by 64bit instructions that can use rip-relative
7493 // it cannot be used by instructions that want an immediate value.
7494
7495 bool Assembler::reachable(AddressLiteral adr) {
7496 int64_t disp;
7497 // None will force a 64bit literal to the code stream. Likely a placeholder
7498 // for something that will be patched later and we need to certain it will
7499 // always be reachable.
7500 if (adr.reloc() == relocInfo::none) {
7501 return false;
7502 }
7503 if (adr.reloc() == relocInfo::internal_word_type) {
7504 // This should be rip relative and easily reachable.
7505 return true;
7506 }
7507 if (adr.reloc() == relocInfo::virtual_call_type ||
7508 adr.reloc() == relocInfo::opt_virtual_call_type ||
7509 adr.reloc() == relocInfo::static_call_type ||
7510 adr.reloc() == relocInfo::static_stub_type ) {
7511 // This should be rip relative within the code cache and easily
7512 // reachable until we get huge code caches. (At which point
7513 // ic code is going to have issues).
7514 return true;
7515 }
7516 if (adr.reloc() != relocInfo::external_word_type &&
7517 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7518 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7519 adr.reloc() != relocInfo::runtime_call_type ) {
7520 return false;
7521 }
7522
7523 // Stress the correction code
7524 if (ForceUnreachable) {
7525 // Must be runtimecall reloc, see if it is in the codecache
7526 // Flipping stuff in the codecache to be unreachable causes issues
7527 // with things like inline caches where the additional instructions
7528 // are not handled.
7529 if (CodeCache::find_blob(adr._target) == NULL) {
7530 return false;
7531 }
7532 }
7533 // For external_word_type/runtime_call_type if it is reachable from where we
7534 // are now (possibly a temp buffer) and where we might end up
7535 // anywhere in the codeCache then we are always reachable.
7536 // This would have to change if we ever save/restore shared code
7537 // to be more pessimistic.
7538 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7539 if (!is_simm32(disp)) return false;
7540 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7541 if (!is_simm32(disp)) return false;
7542
7543 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7544
7545 // Because rip relative is a disp + address_of_next_instruction and we
7546 // don't know the value of address_of_next_instruction we apply a fudge factor
7547 // to make sure we will be ok no matter the size of the instruction we get placed into.
7548 // We don't have to fudge the checks above here because they are already worst case.
7549
7550 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7551 // + 4 because better safe than sorry.
7552 const int fudge = 12 + 4;
7553 if (disp < 0) {
7554 disp -= fudge;
7555 } else {
7556 disp += fudge;
7557 }
7558 return is_simm32(disp);
7559 }
7560
7561 // Check if the polling page is not reachable from the code cache using rip-relative
7562 // addressing.
7563 bool Assembler::is_polling_page_far() {
7564 intptr_t addr = (intptr_t)os::get_polling_page();
7565 return ForceUnreachable ||
7566 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7567 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7568 }
7569
7570 void Assembler::emit_data64(jlong data,
7571 relocInfo::relocType rtype,
7572 int format) {
7573 if (rtype == relocInfo::none) {
7574 emit_int64(data);
7575 } else {
7576 emit_data64(data, Relocation::spec_simple(rtype), format);
7577 }
7578 }
7579
7580 void Assembler::emit_data64(jlong data,
7581 RelocationHolder const& rspec,
7582 int format) {
7583 assert(imm_operand == 0, "default format must be immediate in this file");
7584 assert(imm_operand == format, "must be immediate");
7585 assert(inst_mark() != NULL, "must be inside InstructionMark");
7586 // Do not use AbstractAssembler::relocate, which is not intended for
7587 // embedded words. Instead, relocate to the enclosing instruction.
7588 code_section()->relocate(inst_mark(), rspec, format);
7589 #ifdef ASSERT
7590 check_relocation(rspec, format);
7591 #endif
7592 emit_int64(data);
7593 }
7594
7595 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7596 if (reg_enc >= 8) {
7597 prefix(REX_B);
7598 reg_enc -= 8;
7599 } else if (byteinst && reg_enc >= 4) {
7600 prefix(REX);
7601 }
7602 return reg_enc;
7603 }
7604
7605 int Assembler::prefixq_and_encode(int reg_enc) {
7606 if (reg_enc < 8) {
7607 prefix(REX_W);
7608 } else {
7609 prefix(REX_WB);
7610 reg_enc -= 8;
7611 }
7612 return reg_enc;
7613 }
7614
7615 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7616 if (dst_enc < 8) {
7617 if (src_enc >= 8) {
7618 prefix(REX_B);
7619 src_enc -= 8;
7620 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7621 prefix(REX);
7622 }
7623 } else {
7624 if (src_enc < 8) {
7625 prefix(REX_R);
7626 } else {
7627 prefix(REX_RB);
7628 src_enc -= 8;
7629 }
7630 dst_enc -= 8;
7631 }
7632 return dst_enc << 3 | src_enc;
7633 }
7634
7635 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7636 if (dst_enc < 8) {
7637 if (src_enc < 8) {
7638 prefix(REX_W);
7639 } else {
7640 prefix(REX_WB);
7641 src_enc -= 8;
7642 }
7643 } else {
7644 if (src_enc < 8) {
7645 prefix(REX_WR);
7646 } else {
7647 prefix(REX_WRB);
7648 src_enc -= 8;
7649 }
7650 dst_enc -= 8;
7651 }
7652 return dst_enc << 3 | src_enc;
7653 }
7654
7655 void Assembler::prefix(Register reg) {
7656 if (reg->encoding() >= 8) {
7657 prefix(REX_B);
7658 }
7659 }
7660
7661 void Assembler::prefix(Register dst, Register src, Prefix p) {
7662 if (src->encoding() >= 8) {
7663 p = (Prefix)(p | REX_B);
7664 }
7665 if (dst->encoding() >= 8) {
7666 p = (Prefix)( p | REX_R);
7667 }
7668 if (p != Prefix_EMPTY) {
7669 // do not generate an empty prefix
7670 prefix(p);
7671 }
7672 }
7673
7674 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7675 if (adr.base_needs_rex()) {
7676 if (adr.index_needs_rex()) {
7677 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7678 } else {
7679 prefix(REX_B);
7680 }
7681 } else {
7682 if (adr.index_needs_rex()) {
7683 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7684 }
7685 }
7686 if (dst->encoding() >= 8) {
7687 p = (Prefix)(p | REX_R);
7688 }
7689 if (p != Prefix_EMPTY) {
7690 // do not generate an empty prefix
7691 prefix(p);
7692 }
7693 }
7694
7695 void Assembler::prefix(Address adr) {
7696 if (adr.base_needs_rex()) {
7697 if (adr.index_needs_rex()) {
7698 prefix(REX_XB);
7699 } else {
7700 prefix(REX_B);
7701 }
7702 } else {
7703 if (adr.index_needs_rex()) {
7704 prefix(REX_X);
7705 }
7706 }
7707 }
7708
7709 void Assembler::prefixq(Address adr) {
7710 if (adr.base_needs_rex()) {
7711 if (adr.index_needs_rex()) {
7712 prefix(REX_WXB);
7713 } else {
7714 prefix(REX_WB);
7715 }
7716 } else {
7717 if (adr.index_needs_rex()) {
7718 prefix(REX_WX);
7719 } else {
7720 prefix(REX_W);
7721 }
7722 }
7723 }
7724
7725
7726 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7727 if (reg->encoding() < 8) {
7728 if (adr.base_needs_rex()) {
7729 if (adr.index_needs_rex()) {
7730 prefix(REX_XB);
7731 } else {
7732 prefix(REX_B);
7733 }
7734 } else {
7735 if (adr.index_needs_rex()) {
7736 prefix(REX_X);
7737 } else if (byteinst && reg->encoding() >= 4 ) {
7738 prefix(REX);
7739 }
7740 }
7741 } else {
7742 if (adr.base_needs_rex()) {
7743 if (adr.index_needs_rex()) {
7744 prefix(REX_RXB);
7745 } else {
7746 prefix(REX_RB);
7747 }
7748 } else {
7749 if (adr.index_needs_rex()) {
7750 prefix(REX_RX);
7751 } else {
7752 prefix(REX_R);
7753 }
7754 }
7755 }
7756 }
7757
7758 void Assembler::prefixq(Address adr, Register src) {
7759 if (src->encoding() < 8) {
7760 if (adr.base_needs_rex()) {
7761 if (adr.index_needs_rex()) {
7762 prefix(REX_WXB);
7763 } else {
7764 prefix(REX_WB);
7765 }
7766 } else {
7767 if (adr.index_needs_rex()) {
7768 prefix(REX_WX);
7769 } else {
7770 prefix(REX_W);
7771 }
7772 }
7773 } else {
7774 if (adr.base_needs_rex()) {
7775 if (adr.index_needs_rex()) {
7776 prefix(REX_WRXB);
7777 } else {
7778 prefix(REX_WRB);
7779 }
7780 } else {
7781 if (adr.index_needs_rex()) {
7782 prefix(REX_WRX);
7783 } else {
7784 prefix(REX_WR);
7785 }
7786 }
7787 }
7788 }
7789
7790 void Assembler::prefix(Address adr, XMMRegister reg) {
7791 if (reg->encoding() < 8) {
7792 if (adr.base_needs_rex()) {
7793 if (adr.index_needs_rex()) {
7794 prefix(REX_XB);
7795 } else {
7796 prefix(REX_B);
7797 }
7798 } else {
7799 if (adr.index_needs_rex()) {
7800 prefix(REX_X);
7801 }
7802 }
7803 } else {
7804 if (adr.base_needs_rex()) {
7805 if (adr.index_needs_rex()) {
7806 prefix(REX_RXB);
7807 } else {
7808 prefix(REX_RB);
7809 }
7810 } else {
7811 if (adr.index_needs_rex()) {
7812 prefix(REX_RX);
7813 } else {
7814 prefix(REX_R);
7815 }
7816 }
7817 }
7818 }
7819
7820 void Assembler::prefixq(Address adr, XMMRegister src) {
7821 if (src->encoding() < 8) {
7822 if (adr.base_needs_rex()) {
7823 if (adr.index_needs_rex()) {
7824 prefix(REX_WXB);
7825 } else {
7826 prefix(REX_WB);
7827 }
7828 } else {
7829 if (adr.index_needs_rex()) {
7830 prefix(REX_WX);
7831 } else {
7832 prefix(REX_W);
7833 }
7834 }
7835 } else {
7836 if (adr.base_needs_rex()) {
7837 if (adr.index_needs_rex()) {
7838 prefix(REX_WRXB);
7839 } else {
7840 prefix(REX_WRB);
7841 }
7842 } else {
7843 if (adr.index_needs_rex()) {
7844 prefix(REX_WRX);
7845 } else {
7846 prefix(REX_WR);
7847 }
7848 }
7849 }
7850 }
7851
7852 void Assembler::adcq(Register dst, int32_t imm32) {
7853 (void) prefixq_and_encode(dst->encoding());
7854 emit_arith(0x81, 0xD0, dst, imm32);
7855 }
7856
7857 void Assembler::adcq(Register dst, Address src) {
7858 InstructionMark im(this);
7859 prefixq(src, dst);
7860 emit_int8(0x13);
7861 emit_operand(dst, src);
7862 }
7863
7864 void Assembler::adcq(Register dst, Register src) {
7865 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7866 emit_arith(0x13, 0xC0, dst, src);
7867 }
7868
7869 void Assembler::addq(Address dst, int32_t imm32) {
7870 InstructionMark im(this);
7871 prefixq(dst);
7872 emit_arith_operand(0x81, rax, dst,imm32);
7873 }
7874
7875 void Assembler::addq(Address dst, Register src) {
7876 InstructionMark im(this);
7877 prefixq(dst, src);
7878 emit_int8(0x01);
7879 emit_operand(src, dst);
7880 }
7881
7882 void Assembler::addq(Register dst, int32_t imm32) {
7883 (void) prefixq_and_encode(dst->encoding());
7884 emit_arith(0x81, 0xC0, dst, imm32);
7885 }
7886
7887 void Assembler::addq(Register dst, Address src) {
7888 InstructionMark im(this);
7889 prefixq(src, dst);
7890 emit_int8(0x03);
7891 emit_operand(dst, src);
7892 }
7893
7894 void Assembler::addq(Register dst, Register src) {
7895 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7896 emit_arith(0x03, 0xC0, dst, src);
7897 }
7898
7899 void Assembler::adcxq(Register dst, Register src) {
7900 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7901 emit_int8((unsigned char)0x66);
7902 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7903 emit_int8(0x0F);
7904 emit_int8(0x38);
7905 emit_int8((unsigned char)0xF6);
7906 emit_int8((unsigned char)(0xC0 | encode));
7907 }
7908
7909 void Assembler::adoxq(Register dst, Register src) {
7910 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7911 emit_int8((unsigned char)0xF3);
7912 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7913 emit_int8(0x0F);
7914 emit_int8(0x38);
7915 emit_int8((unsigned char)0xF6);
7916 emit_int8((unsigned char)(0xC0 | encode));
7917 }
7918
7919 void Assembler::andq(Address dst, int32_t imm32) {
7920 InstructionMark im(this);
7921 prefixq(dst);
7922 emit_int8((unsigned char)0x81);
7923 emit_operand(rsp, dst, 4);
7924 emit_int32(imm32);
7925 }
7926
7927 void Assembler::andq(Register dst, int32_t imm32) {
7928 (void) prefixq_and_encode(dst->encoding());
7929 emit_arith(0x81, 0xE0, dst, imm32);
7930 }
7931
7932 void Assembler::andq(Register dst, Address src) {
7933 InstructionMark im(this);
7934 prefixq(src, dst);
7935 emit_int8(0x23);
7936 emit_operand(dst, src);
7937 }
7938
7939 void Assembler::andq(Register dst, Register src) {
7940 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7941 emit_arith(0x23, 0xC0, dst, src);
7942 }
7943
7944 void Assembler::andnq(Register dst, Register src1, Register src2) {
7945 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7946 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7947 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7948 emit_int8((unsigned char)0xF2);
7949 emit_int8((unsigned char)(0xC0 | encode));
7950 }
7951
7952 void Assembler::andnq(Register dst, Register src1, Address src2) {
7953 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7954 InstructionMark im(this);
7955 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7956 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7957 emit_int8((unsigned char)0xF2);
7958 emit_operand(dst, src2);
7959 }
7960
7961 void Assembler::bsfq(Register dst, Register src) {
7962 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7963 emit_int8(0x0F);
7964 emit_int8((unsigned char)0xBC);
7965 emit_int8((unsigned char)(0xC0 | encode));
7966 }
7967
7968 void Assembler::bsrq(Register dst, Register src) {
7969 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7970 emit_int8(0x0F);
7971 emit_int8((unsigned char)0xBD);
7972 emit_int8((unsigned char)(0xC0 | encode));
7973 }
7974
7975 void Assembler::bswapq(Register reg) {
7976 int encode = prefixq_and_encode(reg->encoding());
7977 emit_int8(0x0F);
7978 emit_int8((unsigned char)(0xC8 | encode));
7979 }
7980
7981 void Assembler::blsiq(Register dst, Register src) {
7982 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7983 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7984 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7985 emit_int8((unsigned char)0xF3);
7986 emit_int8((unsigned char)(0xC0 | encode));
7987 }
7988
7989 void Assembler::blsiq(Register dst, Address src) {
7990 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7991 InstructionMark im(this);
7992 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7993 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7994 emit_int8((unsigned char)0xF3);
7995 emit_operand(rbx, src);
7996 }
7997
7998 void Assembler::blsmskq(Register dst, Register src) {
7999 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8000 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8001 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8002 emit_int8((unsigned char)0xF3);
8003 emit_int8((unsigned char)(0xC0 | encode));
8004 }
8005
8006 void Assembler::blsmskq(Register dst, Address src) {
8007 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8008 InstructionMark im(this);
8009 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8010 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8011 emit_int8((unsigned char)0xF3);
8012 emit_operand(rdx, src);
8013 }
8014
8015 void Assembler::blsrq(Register dst, Register src) {
8016 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8017 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8018 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8019 emit_int8((unsigned char)0xF3);
8020 emit_int8((unsigned char)(0xC0 | encode));
8021 }
8022
8023 void Assembler::blsrq(Register dst, Address src) {
8024 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8025 InstructionMark im(this);
8026 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8027 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8028 emit_int8((unsigned char)0xF3);
8029 emit_operand(rcx, src);
8030 }
8031
8032 void Assembler::cdqq() {
8033 prefix(REX_W);
8034 emit_int8((unsigned char)0x99);
8035 }
8036
8037 void Assembler::clflush(Address adr) {
8038 prefix(adr);
8039 emit_int8(0x0F);
8040 emit_int8((unsigned char)0xAE);
8041 emit_operand(rdi, adr);
8042 }
8043
8044 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8045 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8046 emit_int8(0x0F);
8047 emit_int8(0x40 | cc);
8048 emit_int8((unsigned char)(0xC0 | encode));
8049 }
8050
8051 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8052 InstructionMark im(this);
8053 prefixq(src, dst);
8054 emit_int8(0x0F);
8055 emit_int8(0x40 | cc);
8056 emit_operand(dst, src);
8057 }
8058
8059 void Assembler::cmpq(Address dst, int32_t imm32) {
8060 InstructionMark im(this);
8061 prefixq(dst);
8062 emit_int8((unsigned char)0x81);
8063 emit_operand(rdi, dst, 4);
8064 emit_int32(imm32);
8065 }
8066
8067 void Assembler::cmpq(Register dst, int32_t imm32) {
8068 (void) prefixq_and_encode(dst->encoding());
8069 emit_arith(0x81, 0xF8, dst, imm32);
8070 }
8071
8072 void Assembler::cmpq(Address dst, Register src) {
8073 InstructionMark im(this);
8074 prefixq(dst, src);
8075 emit_int8(0x3B);
8076 emit_operand(src, dst);
8077 }
8078
8079 void Assembler::cmpq(Register dst, Register src) {
8080 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8081 emit_arith(0x3B, 0xC0, dst, src);
8082 }
8083
8084 void Assembler::cmpq(Register dst, Address src) {
8085 InstructionMark im(this);
8086 prefixq(src, dst);
8087 emit_int8(0x3B);
8088 emit_operand(dst, src);
8089 }
8090
8091 void Assembler::cmpxchgq(Register reg, Address adr) {
8092 InstructionMark im(this);
8093 prefixq(adr, reg);
8094 emit_int8(0x0F);
8095 emit_int8((unsigned char)0xB1);
8096 emit_operand(reg, adr);
8097 }
8098
8099 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8100 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8101 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8102 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8103 emit_int8(0x2A);
8104 emit_int8((unsigned char)(0xC0 | encode));
8105 }
8106
8107 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8108 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8109 InstructionMark im(this);
8110 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8111 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8112 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8113 emit_int8(0x2A);
8114 emit_operand(dst, src);
8115 }
8116
8117 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8118 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8119 InstructionMark im(this);
8120 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8121 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8122 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8123 emit_int8(0x2A);
8124 emit_operand(dst, src);
8125 }
8126
8127 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8128 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8129 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8130 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8131 emit_int8(0x2C);
8132 emit_int8((unsigned char)(0xC0 | encode));
8133 }
8134
8135 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8136 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8137 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8138 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8139 emit_int8(0x2C);
8140 emit_int8((unsigned char)(0xC0 | encode));
8141 }
8142
8143 void Assembler::decl(Register dst) {
8144 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8145 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8146 int encode = prefix_and_encode(dst->encoding());
8147 emit_int8((unsigned char)0xFF);
8148 emit_int8((unsigned char)(0xC8 | encode));
8149 }
8150
8151 void Assembler::decq(Register dst) {
8152 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8153 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8154 int encode = prefixq_and_encode(dst->encoding());
8155 emit_int8((unsigned char)0xFF);
8156 emit_int8(0xC8 | encode);
8157 }
8158
8159 void Assembler::decq(Address dst) {
8160 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8161 InstructionMark im(this);
8162 prefixq(dst);
8163 emit_int8((unsigned char)0xFF);
8164 emit_operand(rcx, dst);
8165 }
8166
8167 void Assembler::fxrstor(Address src) {
8168 prefixq(src);
8169 emit_int8(0x0F);
8170 emit_int8((unsigned char)0xAE);
8171 emit_operand(as_Register(1), src);
8172 }
8173
8174 void Assembler::xrstor(Address src) {
8175 prefixq(src);
8176 emit_int8(0x0F);
8177 emit_int8((unsigned char)0xAE);
8178 emit_operand(as_Register(5), src);
8179 }
8180
8181 void Assembler::fxsave(Address dst) {
8182 prefixq(dst);
8183 emit_int8(0x0F);
8184 emit_int8((unsigned char)0xAE);
8185 emit_operand(as_Register(0), dst);
8186 }
8187
8188 void Assembler::xsave(Address dst) {
8189 prefixq(dst);
8190 emit_int8(0x0F);
8191 emit_int8((unsigned char)0xAE);
8192 emit_operand(as_Register(4), dst);
8193 }
8194
8195 void Assembler::idivq(Register src) {
8196 int encode = prefixq_and_encode(src->encoding());
8197 emit_int8((unsigned char)0xF7);
8198 emit_int8((unsigned char)(0xF8 | encode));
8199 }
8200
8201 void Assembler::imulq(Register dst, Register src) {
8202 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8203 emit_int8(0x0F);
8204 emit_int8((unsigned char)0xAF);
8205 emit_int8((unsigned char)(0xC0 | encode));
8206 }
8207
8208 void Assembler::imulq(Register dst, Register src, int value) {
8209 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8210 if (is8bit(value)) {
8211 emit_int8(0x6B);
8212 emit_int8((unsigned char)(0xC0 | encode));
8213 emit_int8(value & 0xFF);
8214 } else {
8215 emit_int8(0x69);
8216 emit_int8((unsigned char)(0xC0 | encode));
8217 emit_int32(value);
8218 }
8219 }
8220
8221 void Assembler::imulq(Register dst, Address src) {
8222 InstructionMark im(this);
8223 prefixq(src, dst);
8224 emit_int8(0x0F);
8225 emit_int8((unsigned char) 0xAF);
8226 emit_operand(dst, src);
8227 }
8228
8229 void Assembler::incl(Register dst) {
8230 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8231 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8232 int encode = prefix_and_encode(dst->encoding());
8233 emit_int8((unsigned char)0xFF);
8234 emit_int8((unsigned char)(0xC0 | encode));
8235 }
8236
8237 void Assembler::incq(Register dst) {
8238 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8239 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8240 int encode = prefixq_and_encode(dst->encoding());
8241 emit_int8((unsigned char)0xFF);
8242 emit_int8((unsigned char)(0xC0 | encode));
8243 }
8244
8245 void Assembler::incq(Address dst) {
8246 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8247 InstructionMark im(this);
8248 prefixq(dst);
8249 emit_int8((unsigned char)0xFF);
8250 emit_operand(rax, dst);
8251 }
8252
8253 void Assembler::lea(Register dst, Address src) {
8254 leaq(dst, src);
8255 }
8256
8257 void Assembler::leaq(Register dst, Address src) {
8258 InstructionMark im(this);
8259 prefixq(src, dst);
8260 emit_int8((unsigned char)0x8D);
8261 emit_operand(dst, src);
8262 }
8263
8264 void Assembler::mov64(Register dst, int64_t imm64) {
8265 InstructionMark im(this);
8266 int encode = prefixq_and_encode(dst->encoding());
8267 emit_int8((unsigned char)(0xB8 | encode));
8268 emit_int64(imm64);
8269 }
8270
8271 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8272 InstructionMark im(this);
8273 int encode = prefixq_and_encode(dst->encoding());
8274 emit_int8(0xB8 | encode);
8275 emit_data64(imm64, rspec);
8276 }
8277
8278 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8279 InstructionMark im(this);
8280 int encode = prefix_and_encode(dst->encoding());
8281 emit_int8((unsigned char)(0xB8 | encode));
8282 emit_data((int)imm32, rspec, narrow_oop_operand);
8283 }
8284
8285 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8286 InstructionMark im(this);
8287 prefix(dst);
8288 emit_int8((unsigned char)0xC7);
8289 emit_operand(rax, dst, 4);
8290 emit_data((int)imm32, rspec, narrow_oop_operand);
8291 }
8292
8293 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8294 InstructionMark im(this);
8295 int encode = prefix_and_encode(src1->encoding());
8296 emit_int8((unsigned char)0x81);
8297 emit_int8((unsigned char)(0xF8 | encode));
8298 emit_data((int)imm32, rspec, narrow_oop_operand);
8299 }
8300
8301 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8302 InstructionMark im(this);
8303 prefix(src1);
8304 emit_int8((unsigned char)0x81);
8305 emit_operand(rax, src1, 4);
8306 emit_data((int)imm32, rspec, narrow_oop_operand);
8307 }
8308
8309 void Assembler::lzcntq(Register dst, Register src) {
8310 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8311 emit_int8((unsigned char)0xF3);
8312 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8313 emit_int8(0x0F);
8314 emit_int8((unsigned char)0xBD);
8315 emit_int8((unsigned char)(0xC0 | encode));
8316 }
8317
8318 void Assembler::movdq(XMMRegister dst, Register src) {
8319 // table D-1 says MMX/SSE2
8320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8321 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8322 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8323 emit_int8(0x6E);
8324 emit_int8((unsigned char)(0xC0 | encode));
8325 }
8326
8327 void Assembler::movdq(Register dst, XMMRegister src) {
8328 // table D-1 says MMX/SSE2
8329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8330 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8331 // swap src/dst to get correct prefix
8332 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8333 emit_int8(0x7E);
8334 emit_int8((unsigned char)(0xC0 | encode));
8335 }
8336
8337 void Assembler::movq(Register dst, Register src) {
8338 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8339 emit_int8((unsigned char)0x8B);
8340 emit_int8((unsigned char)(0xC0 | encode));
8341 }
8342
8343 void Assembler::movq(Register dst, Address src) {
8344 InstructionMark im(this);
8345 prefixq(src, dst);
8346 emit_int8((unsigned char)0x8B);
8347 emit_operand(dst, src);
8348 }
8349
8350 void Assembler::movq(Address dst, Register src) {
8351 InstructionMark im(this);
8352 prefixq(dst, src);
8353 emit_int8((unsigned char)0x89);
8354 emit_operand(src, dst);
8355 }
8356
8357 void Assembler::movsbq(Register dst, Address src) {
8358 InstructionMark im(this);
8359 prefixq(src, dst);
8360 emit_int8(0x0F);
8361 emit_int8((unsigned char)0xBE);
8362 emit_operand(dst, src);
8363 }
8364
8365 void Assembler::movsbq(Register dst, Register src) {
8366 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8367 emit_int8(0x0F);
8368 emit_int8((unsigned char)0xBE);
8369 emit_int8((unsigned char)(0xC0 | encode));
8370 }
8371
8372 void Assembler::movslq(Register dst, int32_t imm32) {
8373 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8374 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8375 // as a result we shouldn't use until tested at runtime...
8376 ShouldNotReachHere();
8377 InstructionMark im(this);
8378 int encode = prefixq_and_encode(dst->encoding());
8379 emit_int8((unsigned char)(0xC7 | encode));
8380 emit_int32(imm32);
8381 }
8382
8383 void Assembler::movslq(Address dst, int32_t imm32) {
8384 assert(is_simm32(imm32), "lost bits");
8385 InstructionMark im(this);
8386 prefixq(dst);
8387 emit_int8((unsigned char)0xC7);
8388 emit_operand(rax, dst, 4);
8389 emit_int32(imm32);
8390 }
8391
8392 void Assembler::movslq(Register dst, Address src) {
8393 InstructionMark im(this);
8394 prefixq(src, dst);
8395 emit_int8(0x63);
8396 emit_operand(dst, src);
8397 }
8398
8399 void Assembler::movslq(Register dst, Register src) {
8400 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8401 emit_int8(0x63);
8402 emit_int8((unsigned char)(0xC0 | encode));
8403 }
8404
8405 void Assembler::movswq(Register dst, Address src) {
8406 InstructionMark im(this);
8407 prefixq(src, dst);
8408 emit_int8(0x0F);
8409 emit_int8((unsigned char)0xBF);
8410 emit_operand(dst, src);
8411 }
8412
8413 void Assembler::movswq(Register dst, Register src) {
8414 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8415 emit_int8((unsigned char)0x0F);
8416 emit_int8((unsigned char)0xBF);
8417 emit_int8((unsigned char)(0xC0 | encode));
8418 }
8419
8420 void Assembler::movzbq(Register dst, Address src) {
8421 InstructionMark im(this);
8422 prefixq(src, dst);
8423 emit_int8((unsigned char)0x0F);
8424 emit_int8((unsigned char)0xB6);
8425 emit_operand(dst, src);
8426 }
8427
8428 void Assembler::movzbq(Register dst, Register src) {
8429 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8430 emit_int8(0x0F);
8431 emit_int8((unsigned char)0xB6);
8432 emit_int8(0xC0 | encode);
8433 }
8434
8435 void Assembler::movzwq(Register dst, Address src) {
8436 InstructionMark im(this);
8437 prefixq(src, dst);
8438 emit_int8((unsigned char)0x0F);
8439 emit_int8((unsigned char)0xB7);
8440 emit_operand(dst, src);
8441 }
8442
8443 void Assembler::movzwq(Register dst, Register src) {
8444 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8445 emit_int8((unsigned char)0x0F);
8446 emit_int8((unsigned char)0xB7);
8447 emit_int8((unsigned char)(0xC0 | encode));
8448 }
8449
8450 void Assembler::mulq(Address src) {
8451 InstructionMark im(this);
8452 prefixq(src);
8453 emit_int8((unsigned char)0xF7);
8454 emit_operand(rsp, src);
8455 }
8456
8457 void Assembler::mulq(Register src) {
8458 int encode = prefixq_and_encode(src->encoding());
8459 emit_int8((unsigned char)0xF7);
8460 emit_int8((unsigned char)(0xE0 | encode));
8461 }
8462
8463 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8464 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8465 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8466 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8467 emit_int8((unsigned char)0xF6);
8468 emit_int8((unsigned char)(0xC0 | encode));
8469 }
8470
8471 void Assembler::negq(Register dst) {
8472 int encode = prefixq_and_encode(dst->encoding());
8473 emit_int8((unsigned char)0xF7);
8474 emit_int8((unsigned char)(0xD8 | encode));
8475 }
8476
8477 void Assembler::notq(Register dst) {
8478 int encode = prefixq_and_encode(dst->encoding());
8479 emit_int8((unsigned char)0xF7);
8480 emit_int8((unsigned char)(0xD0 | encode));
8481 }
8482
8483 void Assembler::orq(Address dst, int32_t imm32) {
8484 InstructionMark im(this);
8485 prefixq(dst);
8486 emit_int8((unsigned char)0x81);
8487 emit_operand(rcx, dst, 4);
8488 emit_int32(imm32);
8489 }
8490
8491 void Assembler::orq(Register dst, int32_t imm32) {
8492 (void) prefixq_and_encode(dst->encoding());
8493 emit_arith(0x81, 0xC8, dst, imm32);
8494 }
8495
8496 void Assembler::orq(Register dst, Address src) {
8497 InstructionMark im(this);
8498 prefixq(src, dst);
8499 emit_int8(0x0B);
8500 emit_operand(dst, src);
8501 }
8502
8503 void Assembler::orq(Register dst, Register src) {
8504 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8505 emit_arith(0x0B, 0xC0, dst, src);
8506 }
8507
8508 void Assembler::popa() { // 64bit
8509 movq(r15, Address(rsp, 0));
8510 movq(r14, Address(rsp, wordSize));
8511 movq(r13, Address(rsp, 2 * wordSize));
8512 movq(r12, Address(rsp, 3 * wordSize));
8513 movq(r11, Address(rsp, 4 * wordSize));
8514 movq(r10, Address(rsp, 5 * wordSize));
8515 movq(r9, Address(rsp, 6 * wordSize));
8516 movq(r8, Address(rsp, 7 * wordSize));
8517 movq(rdi, Address(rsp, 8 * wordSize));
8518 movq(rsi, Address(rsp, 9 * wordSize));
8519 movq(rbp, Address(rsp, 10 * wordSize));
8520 // skip rsp
8521 movq(rbx, Address(rsp, 12 * wordSize));
8522 movq(rdx, Address(rsp, 13 * wordSize));
8523 movq(rcx, Address(rsp, 14 * wordSize));
8524 movq(rax, Address(rsp, 15 * wordSize));
8525
8526 addq(rsp, 16 * wordSize);
8527 }
8528
8529 void Assembler::popcntq(Register dst, Address src) {
8530 assert(VM_Version::supports_popcnt(), "must support");
8531 InstructionMark im(this);
8532 emit_int8((unsigned char)0xF3);
8533 prefixq(src, dst);
8534 emit_int8((unsigned char)0x0F);
8535 emit_int8((unsigned char)0xB8);
8536 emit_operand(dst, src);
8537 }
8538
8539 void Assembler::popcntq(Register dst, Register src) {
8540 assert(VM_Version::supports_popcnt(), "must support");
8541 emit_int8((unsigned char)0xF3);
8542 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8543 emit_int8((unsigned char)0x0F);
8544 emit_int8((unsigned char)0xB8);
8545 emit_int8((unsigned char)(0xC0 | encode));
8546 }
8547
8548 void Assembler::popq(Address dst) {
8549 InstructionMark im(this);
8550 prefixq(dst);
8551 emit_int8((unsigned char)0x8F);
8552 emit_operand(rax, dst);
8553 }
8554
8555 void Assembler::pusha() { // 64bit
8556 // we have to store original rsp. ABI says that 128 bytes
8557 // below rsp are local scratch.
8558 movq(Address(rsp, -5 * wordSize), rsp);
8559
8560 subq(rsp, 16 * wordSize);
8561
8562 movq(Address(rsp, 15 * wordSize), rax);
8563 movq(Address(rsp, 14 * wordSize), rcx);
8564 movq(Address(rsp, 13 * wordSize), rdx);
8565 movq(Address(rsp, 12 * wordSize), rbx);
8566 // skip rsp
8567 movq(Address(rsp, 10 * wordSize), rbp);
8568 movq(Address(rsp, 9 * wordSize), rsi);
8569 movq(Address(rsp, 8 * wordSize), rdi);
8570 movq(Address(rsp, 7 * wordSize), r8);
8571 movq(Address(rsp, 6 * wordSize), r9);
8572 movq(Address(rsp, 5 * wordSize), r10);
8573 movq(Address(rsp, 4 * wordSize), r11);
8574 movq(Address(rsp, 3 * wordSize), r12);
8575 movq(Address(rsp, 2 * wordSize), r13);
8576 movq(Address(rsp, wordSize), r14);
8577 movq(Address(rsp, 0), r15);
8578 }
8579
8580 void Assembler::pushq(Address src) {
8581 InstructionMark im(this);
8582 prefixq(src);
8583 emit_int8((unsigned char)0xFF);
8584 emit_operand(rsi, src);
8585 }
8586
8587 void Assembler::rclq(Register dst, int imm8) {
8588 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8589 int encode = prefixq_and_encode(dst->encoding());
8590 if (imm8 == 1) {
8591 emit_int8((unsigned char)0xD1);
8592 emit_int8((unsigned char)(0xD0 | encode));
8593 } else {
8594 emit_int8((unsigned char)0xC1);
8595 emit_int8((unsigned char)(0xD0 | encode));
8596 emit_int8(imm8);
8597 }
8598 }
8599
8600 void Assembler::rcrq(Register dst, int imm8) {
8601 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8602 int encode = prefixq_and_encode(dst->encoding());
8603 if (imm8 == 1) {
8604 emit_int8((unsigned char)0xD1);
8605 emit_int8((unsigned char)(0xD8 | encode));
8606 } else {
8607 emit_int8((unsigned char)0xC1);
8608 emit_int8((unsigned char)(0xD8 | encode));
8609 emit_int8(imm8);
8610 }
8611 }
8612
8613 void Assembler::rorq(Register dst, int imm8) {
8614 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8615 int encode = prefixq_and_encode(dst->encoding());
8616 if (imm8 == 1) {
8617 emit_int8((unsigned char)0xD1);
8618 emit_int8((unsigned char)(0xC8 | encode));
8619 } else {
8620 emit_int8((unsigned char)0xC1);
8621 emit_int8((unsigned char)(0xc8 | encode));
8622 emit_int8(imm8);
8623 }
8624 }
8625
8626 void Assembler::rorxq(Register dst, Register src, int imm8) {
8627 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8628 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8629 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8630 emit_int8((unsigned char)0xF0);
8631 emit_int8((unsigned char)(0xC0 | encode));
8632 emit_int8(imm8);
8633 }
8634
8635 void Assembler::rorxd(Register dst, Register src, int imm8) {
8636 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8637 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8638 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8639 emit_int8((unsigned char)0xF0);
8640 emit_int8((unsigned char)(0xC0 | encode));
8641 emit_int8(imm8);
8642 }
8643
8644 void Assembler::sarq(Register dst, int imm8) {
8645 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8646 int encode = prefixq_and_encode(dst->encoding());
8647 if (imm8 == 1) {
8648 emit_int8((unsigned char)0xD1);
8649 emit_int8((unsigned char)(0xF8 | encode));
8650 } else {
8651 emit_int8((unsigned char)0xC1);
8652 emit_int8((unsigned char)(0xF8 | encode));
8653 emit_int8(imm8);
8654 }
8655 }
8656
8657 void Assembler::sarq(Register dst) {
8658 int encode = prefixq_and_encode(dst->encoding());
8659 emit_int8((unsigned char)0xD3);
8660 emit_int8((unsigned char)(0xF8 | encode));
8661 }
8662
8663 void Assembler::sbbq(Address dst, int32_t imm32) {
8664 InstructionMark im(this);
8665 prefixq(dst);
8666 emit_arith_operand(0x81, rbx, dst, imm32);
8667 }
8668
8669 void Assembler::sbbq(Register dst, int32_t imm32) {
8670 (void) prefixq_and_encode(dst->encoding());
8671 emit_arith(0x81, 0xD8, dst, imm32);
8672 }
8673
8674 void Assembler::sbbq(Register dst, Address src) {
8675 InstructionMark im(this);
8676 prefixq(src, dst);
8677 emit_int8(0x1B);
8678 emit_operand(dst, src);
8679 }
8680
8681 void Assembler::sbbq(Register dst, Register src) {
8682 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8683 emit_arith(0x1B, 0xC0, dst, src);
8684 }
8685
8686 void Assembler::shlq(Register dst, int imm8) {
8687 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8688 int encode = prefixq_and_encode(dst->encoding());
8689 if (imm8 == 1) {
8690 emit_int8((unsigned char)0xD1);
8691 emit_int8((unsigned char)(0xE0 | encode));
8692 } else {
8693 emit_int8((unsigned char)0xC1);
8694 emit_int8((unsigned char)(0xE0 | encode));
8695 emit_int8(imm8);
8696 }
8697 }
8698
8699 void Assembler::shlq(Register dst) {
8700 int encode = prefixq_and_encode(dst->encoding());
8701 emit_int8((unsigned char)0xD3);
8702 emit_int8((unsigned char)(0xE0 | encode));
8703 }
8704
8705 void Assembler::shrq(Register dst, int imm8) {
8706 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8707 int encode = prefixq_and_encode(dst->encoding());
8708 emit_int8((unsigned char)0xC1);
8709 emit_int8((unsigned char)(0xE8 | encode));
8710 emit_int8(imm8);
8711 }
8712
8713 void Assembler::shrq(Register dst) {
8714 int encode = prefixq_and_encode(dst->encoding());
8715 emit_int8((unsigned char)0xD3);
8716 emit_int8(0xE8 | encode);
8717 }
8718
8719 void Assembler::subq(Address dst, int32_t imm32) {
8720 InstructionMark im(this);
8721 prefixq(dst);
8722 emit_arith_operand(0x81, rbp, dst, imm32);
8723 }
8724
8725 void Assembler::subq(Address dst, Register src) {
8726 InstructionMark im(this);
8727 prefixq(dst, src);
8728 emit_int8(0x29);
8729 emit_operand(src, dst);
8730 }
8731
8732 void Assembler::subq(Register dst, int32_t imm32) {
8733 (void) prefixq_and_encode(dst->encoding());
8734 emit_arith(0x81, 0xE8, dst, imm32);
8735 }
8736
8737 // Force generation of a 4 byte immediate value even if it fits into 8bit
8738 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8739 (void) prefixq_and_encode(dst->encoding());
8740 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8741 }
8742
8743 void Assembler::subq(Register dst, Address src) {
8744 InstructionMark im(this);
8745 prefixq(src, dst);
8746 emit_int8(0x2B);
8747 emit_operand(dst, src);
8748 }
8749
8750 void Assembler::subq(Register dst, Register src) {
8751 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8752 emit_arith(0x2B, 0xC0, dst, src);
8753 }
8754
8755 void Assembler::testq(Register dst, int32_t imm32) {
8756 // not using emit_arith because test
8757 // doesn't support sign-extension of
8758 // 8bit operands
8759 int encode = dst->encoding();
8760 if (encode == 0) {
8761 prefix(REX_W);
8762 emit_int8((unsigned char)0xA9);
8763 } else {
8764 encode = prefixq_and_encode(encode);
8765 emit_int8((unsigned char)0xF7);
8766 emit_int8((unsigned char)(0xC0 | encode));
8767 }
8768 emit_int32(imm32);
8769 }
8770
8771 void Assembler::testq(Register dst, Register src) {
8772 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8773 emit_arith(0x85, 0xC0, dst, src);
8774 }
8775
8776 void Assembler::xaddq(Address dst, Register src) {
8777 InstructionMark im(this);
8778 prefixq(dst, src);
8779 emit_int8(0x0F);
8780 emit_int8((unsigned char)0xC1);
8781 emit_operand(src, dst);
8782 }
8783
8784 void Assembler::xchgq(Register dst, Address src) {
8785 InstructionMark im(this);
8786 prefixq(src, dst);
8787 emit_int8((unsigned char)0x87);
8788 emit_operand(dst, src);
8789 }
8790
8791 void Assembler::xchgq(Register dst, Register src) {
8792 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8793 emit_int8((unsigned char)0x87);
8794 emit_int8((unsigned char)(0xc0 | encode));
8795 }
8796
8797 void Assembler::xorq(Register dst, Register src) {
8798 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8799 emit_arith(0x33, 0xC0, dst, src);
8800 }
8801
8802 void Assembler::xorq(Register dst, Address src) {
8803 InstructionMark im(this);
8804 prefixq(src, dst);
8805 emit_int8(0x33);
8806 emit_operand(dst, src);
8807 }
8808
8809 #endif // !LP64