1 //
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   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
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   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
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  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // SPARC Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 register %{
  32 //----------Architecture Description Register Definitions----------------------
  33 // General Registers
  34 // "reg_def"  name ( register save type, C convention save type,
  35 //                   ideal register type, encoding, vm name );
  36 // Register Save Types:
  37 //
  38 // NS  = No-Save:       The register allocator assumes that these registers
  39 //                      can be used without saving upon entry to the method, &
  40 //                      that they do not need to be saved at call sites.
  41 //
  42 // SOC = Save-On-Call:  The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method,
  44 //                      but that they must be saved at call sites.
  45 //
  46 // SOE = Save-On-Entry: The register allocator assumes that these registers
  47 //                      must be saved before using them upon entry to the
  48 //                      method, but they do not need to be saved at call
  49 //                      sites.
  50 //
  51 // AS  = Always-Save:   The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, & that they must be saved at call sites.
  54 //
  55 // Ideal Register Type is used to determine how to save & restore a
  56 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  57 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  58 //
  59 // The encoding number is the actual bit-pattern placed into the opcodes.
  60 
  61 
  62 // ----------------------------
  63 // Integer/Long Registers
  64 // ----------------------------
  65 
  66 // Need to expose the hi/lo aspect of 64-bit registers
  67 // This register set is used for both the 64-bit build and
  68 // the 32-bit build with 1-register longs.
  69 
  70 // Global Registers 0-7
  71 reg_def R_G0H( NS,  NS, Op_RegI,128, G0->as_VMReg()->next());
  72 reg_def R_G0 ( NS,  NS, Op_RegI,  0, G0->as_VMReg());
  73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
  74 reg_def R_G1 (SOC, SOC, Op_RegI,  1, G1->as_VMReg());
  75 reg_def R_G2H( NS,  NS, Op_RegI,130, G2->as_VMReg()->next());
  76 reg_def R_G2 ( NS,  NS, Op_RegI,  2, G2->as_VMReg());
  77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
  78 reg_def R_G3 (SOC, SOC, Op_RegI,  3, G3->as_VMReg());
  79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
  80 reg_def R_G4 (SOC, SOC, Op_RegI,  4, G4->as_VMReg());
  81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
  82 reg_def R_G5 (SOC, SOC, Op_RegI,  5, G5->as_VMReg());
  83 reg_def R_G6H( NS,  NS, Op_RegI,134, G6->as_VMReg()->next());
  84 reg_def R_G6 ( NS,  NS, Op_RegI,  6, G6->as_VMReg());
  85 reg_def R_G7H( NS,  NS, Op_RegI,135, G7->as_VMReg()->next());
  86 reg_def R_G7 ( NS,  NS, Op_RegI,  7, G7->as_VMReg());
  87 
  88 // Output Registers 0-7
  89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
  90 reg_def R_O0 (SOC, SOC, Op_RegI,  8, O0->as_VMReg());
  91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
  92 reg_def R_O1 (SOC, SOC, Op_RegI,  9, O1->as_VMReg());
  93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
  94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
  95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
  96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
  97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
  98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
  99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
 101 reg_def R_SPH( NS,  NS, Op_RegI,142, SP->as_VMReg()->next());
 102 reg_def R_SP ( NS,  NS, Op_RegI, 14, SP->as_VMReg());
 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
 105 
 106 // Local Registers 0-7
 107 reg_def R_L0H( NS,  NS, Op_RegI,144, L0->as_VMReg()->next());
 108 reg_def R_L0 ( NS,  NS, Op_RegI, 16, L0->as_VMReg());
 109 reg_def R_L1H( NS,  NS, Op_RegI,145, L1->as_VMReg()->next());
 110 reg_def R_L1 ( NS,  NS, Op_RegI, 17, L1->as_VMReg());
 111 reg_def R_L2H( NS,  NS, Op_RegI,146, L2->as_VMReg()->next());
 112 reg_def R_L2 ( NS,  NS, Op_RegI, 18, L2->as_VMReg());
 113 reg_def R_L3H( NS,  NS, Op_RegI,147, L3->as_VMReg()->next());
 114 reg_def R_L3 ( NS,  NS, Op_RegI, 19, L3->as_VMReg());
 115 reg_def R_L4H( NS,  NS, Op_RegI,148, L4->as_VMReg()->next());
 116 reg_def R_L4 ( NS,  NS, Op_RegI, 20, L4->as_VMReg());
 117 reg_def R_L5H( NS,  NS, Op_RegI,149, L5->as_VMReg()->next());
 118 reg_def R_L5 ( NS,  NS, Op_RegI, 21, L5->as_VMReg());
 119 reg_def R_L6H( NS,  NS, Op_RegI,150, L6->as_VMReg()->next());
 120 reg_def R_L6 ( NS,  NS, Op_RegI, 22, L6->as_VMReg());
 121 reg_def R_L7H( NS,  NS, Op_RegI,151, L7->as_VMReg()->next());
 122 reg_def R_L7 ( NS,  NS, Op_RegI, 23, L7->as_VMReg());
 123 
 124 // Input Registers 0-7
 125 reg_def R_I0H( NS,  NS, Op_RegI,152, I0->as_VMReg()->next());
 126 reg_def R_I0 ( NS,  NS, Op_RegI, 24, I0->as_VMReg());
 127 reg_def R_I1H( NS,  NS, Op_RegI,153, I1->as_VMReg()->next());
 128 reg_def R_I1 ( NS,  NS, Op_RegI, 25, I1->as_VMReg());
 129 reg_def R_I2H( NS,  NS, Op_RegI,154, I2->as_VMReg()->next());
 130 reg_def R_I2 ( NS,  NS, Op_RegI, 26, I2->as_VMReg());
 131 reg_def R_I3H( NS,  NS, Op_RegI,155, I3->as_VMReg()->next());
 132 reg_def R_I3 ( NS,  NS, Op_RegI, 27, I3->as_VMReg());
 133 reg_def R_I4H( NS,  NS, Op_RegI,156, I4->as_VMReg()->next());
 134 reg_def R_I4 ( NS,  NS, Op_RegI, 28, I4->as_VMReg());
 135 reg_def R_I5H( NS,  NS, Op_RegI,157, I5->as_VMReg()->next());
 136 reg_def R_I5 ( NS,  NS, Op_RegI, 29, I5->as_VMReg());
 137 reg_def R_FPH( NS,  NS, Op_RegI,158, FP->as_VMReg()->next());
 138 reg_def R_FP ( NS,  NS, Op_RegI, 30, FP->as_VMReg());
 139 reg_def R_I7H( NS,  NS, Op_RegI,159, I7->as_VMReg()->next());
 140 reg_def R_I7 ( NS,  NS, Op_RegI, 31, I7->as_VMReg());
 141 
 142 // ----------------------------
 143 // Float/Double Registers
 144 // ----------------------------
 145 
 146 // Float Registers
 147 reg_def R_F0 ( SOC, SOC, Op_RegF,  0, F0->as_VMReg());
 148 reg_def R_F1 ( SOC, SOC, Op_RegF,  1, F1->as_VMReg());
 149 reg_def R_F2 ( SOC, SOC, Op_RegF,  2, F2->as_VMReg());
 150 reg_def R_F3 ( SOC, SOC, Op_RegF,  3, F3->as_VMReg());
 151 reg_def R_F4 ( SOC, SOC, Op_RegF,  4, F4->as_VMReg());
 152 reg_def R_F5 ( SOC, SOC, Op_RegF,  5, F5->as_VMReg());
 153 reg_def R_F6 ( SOC, SOC, Op_RegF,  6, F6->as_VMReg());
 154 reg_def R_F7 ( SOC, SOC, Op_RegF,  7, F7->as_VMReg());
 155 reg_def R_F8 ( SOC, SOC, Op_RegF,  8, F8->as_VMReg());
 156 reg_def R_F9 ( SOC, SOC, Op_RegF,  9, F9->as_VMReg());
 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
 179 
 180 // Double Registers
 181 // The rules of ADL require that double registers be defined in pairs.
 182 // Each pair must be two 32-bit values, but not necessarily a pair of
 183 // single float registers.  In each pair, ADLC-assigned register numbers
 184 // must be adjacent, with the lower number even.  Finally, when the
 185 // CPU stores such a register pair to memory, the word associated with
 186 // the lower ADLC-assigned number must be stored to the lower address.
 187 
 188 // These definitions specify the actual bit encodings of the sparc
 189 // double fp register numbers.  FloatRegisterImpl in register_sparc.hpp
 190 // wants 0-63, so we have to convert every time we want to use fp regs
 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
 192 // 255 is a flag meaning "don't go here".
 193 // I believe we can't handle callee-save doubles D32 and up until
 194 // the place in the sparc stack crawler that asserts on the 255 is
 195 // fixed up.
 196 reg_def R_D32 (SOC, SOC, Op_RegD,  1, F32->as_VMReg());
 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
 198 reg_def R_D34 (SOC, SOC, Op_RegD,  3, F34->as_VMReg());
 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
 200 reg_def R_D36 (SOC, SOC, Op_RegD,  5, F36->as_VMReg());
 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
 202 reg_def R_D38 (SOC, SOC, Op_RegD,  7, F38->as_VMReg());
 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
 204 reg_def R_D40 (SOC, SOC, Op_RegD,  9, F40->as_VMReg());
 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
 228 
 229 
 230 // ----------------------------
 231 // Special Registers
 232 // Condition Codes Flag Registers
 233 // I tried to break out ICC and XCC but it's not very pretty.
 234 // Every Sparc instruction which defs/kills one also kills the other.
 235 // Hence every compare instruction which defs one kind of flags ends
 236 // up needing a kill of the other.
 237 reg_def CCR (SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 238 
 239 reg_def FCC0(SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 240 reg_def FCC1(SOC, SOC,  Op_RegFlags, 1, VMRegImpl::Bad());
 241 reg_def FCC2(SOC, SOC,  Op_RegFlags, 2, VMRegImpl::Bad());
 242 reg_def FCC3(SOC, SOC,  Op_RegFlags, 3, VMRegImpl::Bad());
 243 
 244 // ----------------------------
 245 // Specify the enum values for the registers.  These enums are only used by the
 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
 247 // for visibility to the rest of the vm. The order of this enum influences the
 248 // register allocator so having the freedom to set this order and not be stuck
 249 // with the order that is natural for the rest of the vm is worth it.
 250 alloc_class chunk0(
 251   R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
 252   R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
 253   R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
 254   R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
 255 
 256 // Note that a register is not allocatable unless it is also mentioned
 257 // in a widely-used reg_class below.  Thus, R_G7 and R_G0 are outside i_reg.
 258 
 259 alloc_class chunk1(
 260   // The first registers listed here are those most likely to be used
 261   // as temporaries.  We move F0..F7 away from the front of the list,
 262   // to reduce the likelihood of interferences with parameters and
 263   // return values.  Likewise, we avoid using F0/F1 for parameters,
 264   // since they are used for return values.
 265   // This FPU fine-tuning is worth about 1% on the SPEC geomean.
 266   R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 267   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
 268   R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
 269   R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
 270   R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
 271   R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 272   R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
 273   R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
 274 
 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
 276 
 277 //----------Architecture Description Register Classes--------------------------
 278 // Several register classes are automatically defined based upon information in
 279 // this architecture description.
 280 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 283 //
 284 
 285 // G0 is not included in integer class since it has special meaning.
 286 reg_class g0_reg(R_G0);
 287 
 288 // ----------------------------
 289 // Integer Register Classes
 290 // ----------------------------
 291 // Exclusions from i_reg:
 292 // R_G0: hardwired zero
 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
 294 // R_G6: reserved by Solaris ABI to tools
 295 // R_G7: reserved by Solaris ABI to libthread
 296 // R_O7: Used as a temp in many encodings
 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 298 
 299 // Class for all integer registers, except the G registers.  This is used for
 300 // encodings which use G registers as temps.  The regular inputs to such
 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
 302 // will not put an input into a temp register.
 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 304 
 305 reg_class g1_regI(R_G1);
 306 reg_class g3_regI(R_G3);
 307 reg_class g4_regI(R_G4);
 308 reg_class o0_regI(R_O0);
 309 reg_class o7_regI(R_O7);
 310 
 311 // ----------------------------
 312 // Pointer Register Classes
 313 // ----------------------------
 314 #ifdef _LP64
 315 // 64-bit build means 64-bit pointers means hi/lo pairs
 316 reg_class ptr_reg(            R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 317                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 318                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 319                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 320 // Lock encodings use G3 and G4 internally
 321 reg_class lock_ptr_reg(       R_G1H,R_G1,                                     R_G5H,R_G5,
 322                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 323                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 324                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 325 // Special class for storeP instructions, which can store SP or RPC to TLS.
 326 // It is also used for memory addressing, allowing direct TLS addressing.
 327 reg_class sp_ptr_reg(         R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 328                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
 329                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 330                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 332 // We use it to save R_G2 across calls out of Java.
 333 reg_class l7_regP(R_L7H,R_L7);
 334 
 335 // Other special pointer regs
 336 reg_class g1_regP(R_G1H,R_G1);
 337 reg_class g2_regP(R_G2H,R_G2);
 338 reg_class g3_regP(R_G3H,R_G3);
 339 reg_class g4_regP(R_G4H,R_G4);
 340 reg_class g5_regP(R_G5H,R_G5);
 341 reg_class i0_regP(R_I0H,R_I0);
 342 reg_class o0_regP(R_O0H,R_O0);
 343 reg_class o1_regP(R_O1H,R_O1);
 344 reg_class o2_regP(R_O2H,R_O2);
 345 reg_class o7_regP(R_O7H,R_O7);
 346 
 347 #else // _LP64
 348 // 32-bit build means 32-bit pointers means 1 register.
 349 reg_class ptr_reg(     R_G1,     R_G3,R_G4,R_G5,
 350                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 351                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 352                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 353 // Lock encodings use G3 and G4 internally
 354 reg_class lock_ptr_reg(R_G1,               R_G5,
 355                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 356                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 357                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 358 // Special class for storeP instructions, which can store SP or RPC to TLS.
 359 // It is also used for memory addressing, allowing direct TLS addressing.
 360 reg_class sp_ptr_reg(  R_G1,R_G2,R_G3,R_G4,R_G5,
 361                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
 362                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 363                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 365 // We use it to save R_G2 across calls out of Java.
 366 reg_class l7_regP(R_L7);
 367 
 368 // Other special pointer regs
 369 reg_class g1_regP(R_G1);
 370 reg_class g2_regP(R_G2);
 371 reg_class g3_regP(R_G3);
 372 reg_class g4_regP(R_G4);
 373 reg_class g5_regP(R_G5);
 374 reg_class i0_regP(R_I0);
 375 reg_class o0_regP(R_O0);
 376 reg_class o1_regP(R_O1);
 377 reg_class o2_regP(R_O2);
 378 reg_class o7_regP(R_O7);
 379 #endif // _LP64
 380 
 381 
 382 // ----------------------------
 383 // Long Register Classes
 384 // ----------------------------
 385 // Longs in 1 register.  Aligned adjacent hi/lo pairs.
 386 // Note:  O7 is never in this class; it is sometimes used as an encoding temp.
 387 reg_class long_reg(             R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
 388                    ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
 389 #ifdef _LP64
 390 // 64-bit, longs in 1 register: use all 64-bit integer registers
 391 // 32-bit, longs in 1 register: cannot use I's and L's.  Restrict to O's and G's.
 392                    ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
 393                    ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
 394 #endif // _LP64
 395                   );
 396 
 397 reg_class g1_regL(R_G1H,R_G1);
 398 reg_class g3_regL(R_G3H,R_G3);
 399 reg_class o2_regL(R_O2H,R_O2);
 400 reg_class o7_regL(R_O7H,R_O7);
 401 
 402 // ----------------------------
 403 // Special Class for Condition Code Flags Register
 404 reg_class int_flags(CCR);
 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
 406 reg_class float_flag0(FCC0);
 407 
 408 
 409 // ----------------------------
 410 // Float Point Register Classes
 411 // ----------------------------
 412 // Skip F30/F31, they are reserved for mem-mem copies
 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 414 
 415 // Paired floating point registers--they show up in the same order as the floats,
 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 418                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
 419                    /* Use extra V9 double registers; this AD file does not support V8 */
 420                    R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 421                    R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
 422                    );
 423 
 424 // Paired floating point registers--they show up in the same order as the floats,
 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 426 // This class is usable for mis-aligned loads as happen in I2C adapters.
 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 428                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 429 %}
 430 
 431 //----------DEFINITION BLOCK---------------------------------------------------
 432 // Define name --> value mappings to inform the ADLC of an integer valued name
 433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 434 // Format:
 435 //        int_def  <name>         ( <int_value>, <expression>);
 436 // Generated Code in ad_<arch>.hpp
 437 //        #define  <name>   (<expression>)
 438 //        // value == <int_value>
 439 // Generated code in ad_<arch>.cpp adlc_verification()
 440 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 441 //
 442 definitions %{
 443 // The default cost (of an ALU instruction).
 444   int_def DEFAULT_COST      (    100,     100);
 445   int_def HUGE_COST         (1000000, 1000000);
 446 
 447 // Memory refs are twice as expensive as run-of-the-mill.
 448   int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);
 449 
 450 // Branches are even more expensive.
 451   int_def BRANCH_COST       (    300, DEFAULT_COST * 3);
 452   int_def CALL_COST         (    300, DEFAULT_COST * 3);
 453 %}
 454 
 455 
 456 //----------SOURCE BLOCK-------------------------------------------------------
 457 // This is a block of C++ code which provides values, functions, and
 458 // definitions necessary in the rest of the architecture description
 459 source_hpp %{
 460 // Header information of the source block.
 461 // Method declarations/definitions which are used outside
 462 // the ad-scope can conveniently be defined here.
 463 //
 464 // To keep related declarations/definitions/uses close together,
 465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 466 
 467 // Must be visible to the DFA in dfa_sparc.cpp
 468 extern bool can_branch_register( Node *bol, Node *cmp );
 469 
 470 extern bool use_block_zeroing(Node* count);
 471 
 472 // Macros to extract hi & lo halves from a long pair.
 473 // G0 is not part of any long pair, so assert on that.
 474 // Prevents accidentally using G1 instead of G0.
 475 #define LONG_HI_REG(x) (x)
 476 #define LONG_LO_REG(x) (x)
 477 
 478 class CallStubImpl {
 479 
 480   //--------------------------------------------------------------
 481   //---<  Used for optimization in Compile::Shorten_branches  >---
 482   //--------------------------------------------------------------
 483 
 484  public:
 485   // Size of call trampoline stub.
 486   static uint size_call_trampoline() {
 487     return 0; // no call trampolines on this platform
 488   }
 489 
 490   // number of relocations needed by a call trampoline stub
 491   static uint reloc_call_trampoline() {
 492     return 0; // no call trampolines on this platform
 493   }
 494 };
 495 
 496 class HandlerImpl {
 497 
 498  public:
 499 
 500   static int emit_exception_handler(CodeBuffer &cbuf);
 501   static int emit_deopt_handler(CodeBuffer& cbuf);
 502 
 503   static uint size_exception_handler() {
 504     if (TraceJumps) {
 505       return (400); // just a guess
 506     }
 507     return ( NativeJump::instruction_size ); // sethi;jmp;nop
 508   }
 509 
 510   static uint size_deopt_handler() {
 511     if (TraceJumps) {
 512       return (400); // just a guess
 513     }
 514     return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore
 515   }
 516 };
 517 
 518 %}
 519 
 520 source %{
 521 #define __ _masm.
 522 
 523 // tertiary op of a LoadP or StoreP encoding
 524 #define REGP_OP true
 525 
 526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
 527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
 528 static Register reg_to_register_object(int register_encoding);
 529 
 530 // Used by the DFA in dfa_sparc.cpp.
 531 // Check for being able to use a V9 branch-on-register.  Requires a
 532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
 533 // extended.  Doesn't work following an integer ADD, for example, because of
 534 // overflow (-1 incremented yields 0 plus a carry in the high-order word).  On
 535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
 536 // replace them with zero, which could become sign-extension in a different OS
 537 // release.  There's no obvious reason why an interrupt will ever fill these
 538 // bits with non-zero junk (the registers are reloaded with standard LD
 539 // instructions which either zero-fill or sign-fill).
 540 bool can_branch_register( Node *bol, Node *cmp ) {
 541   if( !BranchOnRegister ) return false;
 542 #ifdef _LP64
 543   if( cmp->Opcode() == Op_CmpP )
 544     return true;  // No problems with pointer compares
 545 #endif
 546   if( cmp->Opcode() == Op_CmpL )
 547     return true;  // No problems with long compares
 548 
 549   if( !SparcV9RegsHiBitsZero ) return false;
 550   if( bol->as_Bool()->_test._test != BoolTest::ne &&
 551       bol->as_Bool()->_test._test != BoolTest::eq )
 552      return false;
 553 
 554   // Check for comparing against a 'safe' value.  Any operation which
 555   // clears out the high word is safe.  Thus, loads and certain shifts
 556   // are safe, as are non-negative constants.  Any operation which
 557   // preserves zero bits in the high word is safe as long as each of its
 558   // inputs are safe.  Thus, phis and bitwise booleans are safe if their
 559   // inputs are safe.  At present, the only important case to recognize
 560   // seems to be loads.  Constants should fold away, and shifts &
 561   // logicals can use the 'cc' forms.
 562   Node *x = cmp->in(1);
 563   if( x->is_Load() ) return true;
 564   if( x->is_Phi() ) {
 565     for( uint i = 1; i < x->req(); i++ )
 566       if( !x->in(i)->is_Load() )
 567         return false;
 568     return true;
 569   }
 570   return false;
 571 }
 572 
 573 bool use_block_zeroing(Node* count) {
 574   // Use BIS for zeroing if count is not constant
 575   // or it is >= BlockZeroingLowLimit.
 576   return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
 577 }
 578 
 579 // ****************************************************************************
 580 
 581 // REQUIRED FUNCTIONALITY
 582 
 583 // !!!!! Special hack to get all type of calls to specify the byte offset
 584 //       from the start of the call to the point where the return address
 585 //       will point.
 586 //       The "return address" is the address of the call instruction, plus 8.
 587 
 588 int MachCallStaticJavaNode::ret_addr_offset() {
 589   int offset = NativeCall::instruction_size;  // call; delay slot
 590   if (_method_handle_invoke)
 591     offset += 4;  // restore SP
 592   return offset;
 593 }
 594 
 595 int MachCallDynamicJavaNode::ret_addr_offset() {
 596   int vtable_index = this->_vtable_index;
 597   if (vtable_index < 0) {
 598     // must be invalid_vtable_index, not nonvirtual_vtable_index
 599     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 600     return (NativeMovConstReg::instruction_size +
 601            NativeCall::instruction_size);  // sethi; setlo; call; delay slot
 602   } else {
 603     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 604     int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
 605     int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
 606     int klass_load_size;
 607     if (UseCompressedClassPointers) {
 608       assert(Universe::heap() != NULL, "java heap should be initialized");
 609       klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
 610     } else {
 611       klass_load_size = 1*BytesPerInstWord;
 612     }
 613     if (Assembler::is_simm13(v_off)) {
 614       return klass_load_size +
 615              (2*BytesPerInstWord +           // ld_ptr, ld_ptr
 616              NativeCall::instruction_size);  // call; delay slot
 617     } else {
 618       return klass_load_size +
 619              (4*BytesPerInstWord +           // set_hi, set, ld_ptr, ld_ptr
 620              NativeCall::instruction_size);  // call; delay slot
 621     }
 622   }
 623 }
 624 
 625 int MachCallRuntimeNode::ret_addr_offset() {
 626 #ifdef _LP64
 627   if (MacroAssembler::is_far_target(entry_point())) {
 628     return NativeFarCall::instruction_size;
 629   } else {
 630     return NativeCall::instruction_size;
 631   }
 632 #else
 633   return NativeCall::instruction_size;  // call; delay slot
 634 #endif
 635 }
 636 
 637 // Indicate if the safepoint node needs the polling page as an input.
 638 // Since Sparc does not have absolute addressing, it does.
 639 bool SafePointNode::needs_polling_address_input() {
 640   return true;
 641 }
 642 
 643 // emit an interrupt that is caught by the debugger (for debugging compiler)
 644 void emit_break(CodeBuffer &cbuf) {
 645   MacroAssembler _masm(&cbuf);
 646   __ breakpoint_trap();
 647 }
 648 
 649 #ifndef PRODUCT
 650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
 651   st->print("TA");
 652 }
 653 #endif
 654 
 655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 656   emit_break(cbuf);
 657 }
 658 
 659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 660   return MachNode::size(ra_);
 661 }
 662 
 663 // Traceable jump
 664 void  emit_jmpl(CodeBuffer &cbuf, int jump_target) {
 665   MacroAssembler _masm(&cbuf);
 666   Register rdest = reg_to_register_object(jump_target);
 667   __ JMP(rdest, 0);
 668   __ delayed()->nop();
 669 }
 670 
 671 // Traceable jump and set exception pc
 672 void  emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
 673   MacroAssembler _masm(&cbuf);
 674   Register rdest = reg_to_register_object(jump_target);
 675   __ JMP(rdest, 0);
 676   __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
 677 }
 678 
 679 void emit_nop(CodeBuffer &cbuf) {
 680   MacroAssembler _masm(&cbuf);
 681   __ nop();
 682 }
 683 
 684 void emit_illtrap(CodeBuffer &cbuf) {
 685   MacroAssembler _masm(&cbuf);
 686   __ illtrap(0);
 687 }
 688 
 689 
 690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
 691   assert(n->rule() != loadUB_rule, "");
 692 
 693   intptr_t offset = 0;
 694   const TypePtr *adr_type = TYPE_PTR_SENTINAL;  // Check for base==RegI, disp==immP
 695   const Node* addr = n->get_base_and_disp(offset, adr_type);
 696   assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
 697   assert(addr != NULL && addr != (Node*)-1, "invalid addr");
 698   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 699   atype = atype->add_offset(offset);
 700   assert(disp32 == offset, "wrong disp32");
 701   return atype->_offset;
 702 }
 703 
 704 
 705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
 706   assert(n->rule() != loadUB_rule, "");
 707 
 708   intptr_t offset = 0;
 709   Node* addr = n->in(2);
 710   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 711   if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
 712     Node* a = addr->in(2/*AddPNode::Address*/);
 713     Node* o = addr->in(3/*AddPNode::Offset*/);
 714     offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
 715     atype = a->bottom_type()->is_ptr()->add_offset(offset);
 716     assert(atype->isa_oop_ptr(), "still an oop");
 717   }
 718   offset = atype->is_ptr()->_offset;
 719   if (offset != Type::OffsetBot)  offset += disp32;
 720   return offset;
 721 }
 722 
 723 static inline jdouble replicate_immI(int con, int count, int width) {
 724   // Load a constant replicated "count" times with width "width"
 725   assert(count*width == 8 && width <= 4, "sanity");
 726   int bit_width = width * 8;
 727   jlong val = con;
 728   val &= (((jlong) 1) << bit_width) - 1;  // mask off sign bits
 729   for (int i = 0; i < count - 1; i++) {
 730     val |= (val << bit_width);
 731   }
 732   jdouble dval = *((jdouble*) &val);  // coerce to double type
 733   return dval;
 734 }
 735 
 736 static inline jdouble replicate_immF(float con) {
 737   // Replicate float con 2 times and pack into vector.
 738   int val = *((int*)&con);
 739   jlong lval = val;
 740   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
 741   jdouble dval = *((jdouble*) &lval);  // coerce to double type
 742   return dval;
 743 }
 744 
 745 // Standard Sparc opcode form2 field breakdown
 746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
 747   f0 &= (1<<19)-1;     // Mask displacement to 19 bits
 748   int op = (f30 << 30) |
 749            (f29 << 29) |
 750            (f25 << 25) |
 751            (f22 << 22) |
 752            (f20 << 20) |
 753            (f19 << 19) |
 754            (f0  <<  0);
 755   cbuf.insts()->emit_int32(op);
 756 }
 757 
 758 // Standard Sparc opcode form2 field breakdown
 759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
 760   f0 >>= 10;           // Drop 10 bits
 761   f0 &= (1<<22)-1;     // Mask displacement to 22 bits
 762   int op = (f30 << 30) |
 763            (f25 << 25) |
 764            (f22 << 22) |
 765            (f0  <<  0);
 766   cbuf.insts()->emit_int32(op);
 767 }
 768 
 769 // Standard Sparc opcode form3 field breakdown
 770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
 771   int op = (f30 << 30) |
 772            (f25 << 25) |
 773            (f19 << 19) |
 774            (f14 << 14) |
 775            (f5  <<  5) |
 776            (f0  <<  0);
 777   cbuf.insts()->emit_int32(op);
 778 }
 779 
 780 // Standard Sparc opcode form3 field breakdown
 781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
 782   simm13 &= (1<<13)-1; // Mask to 13 bits
 783   int op = (f30 << 30) |
 784            (f25 << 25) |
 785            (f19 << 19) |
 786            (f14 << 14) |
 787            (1   << 13) | // bit to indicate immediate-mode
 788            (simm13<<0);
 789   cbuf.insts()->emit_int32(op);
 790 }
 791 
 792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
 793   simm10 &= (1<<10)-1; // Mask to 10 bits
 794   emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
 795 }
 796 
 797 #ifdef ASSERT
 798 // Helper function for VerifyOops in emit_form3_mem_reg
 799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
 800   warning("VerifyOops encountered unexpected instruction:");
 801   n->dump(2);
 802   warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
 803 }
 804 #endif
 805 
 806 
 807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
 808                         int src1_enc, int disp32, int src2_enc, int dst_enc) {
 809 
 810 #ifdef ASSERT
 811   // The following code implements the +VerifyOops feature.
 812   // It verifies oop values which are loaded into or stored out of
 813   // the current method activation.  +VerifyOops complements techniques
 814   // like ScavengeALot, because it eagerly inspects oops in transit,
 815   // as they enter or leave the stack, as opposed to ScavengeALot,
 816   // which inspects oops "at rest", in the stack or heap, at safepoints.
 817   // For this reason, +VerifyOops can sometimes detect bugs very close
 818   // to their point of creation.  It can also serve as a cross-check
 819   // on the validity of oop maps, when used toegether with ScavengeALot.
 820 
 821   // It would be good to verify oops at other points, especially
 822   // when an oop is used as a base pointer for a load or store.
 823   // This is presently difficult, because it is hard to know when
 824   // a base address is biased or not.  (If we had such information,
 825   // it would be easy and useful to make a two-argument version of
 826   // verify_oop which unbiases the base, and performs verification.)
 827 
 828   assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
 829   bool is_verified_oop_base  = false;
 830   bool is_verified_oop_load  = false;
 831   bool is_verified_oop_store = false;
 832   int tmp_enc = -1;
 833   if (VerifyOops && src1_enc != R_SP_enc) {
 834     // classify the op, mainly for an assert check
 835     int st_op = 0, ld_op = 0;
 836     switch (primary) {
 837     case Assembler::stb_op3:  st_op = Op_StoreB; break;
 838     case Assembler::sth_op3:  st_op = Op_StoreC; break;
 839     case Assembler::stx_op3:  // may become StoreP or stay StoreI or StoreD0
 840     case Assembler::stw_op3:  st_op = Op_StoreI; break;
 841     case Assembler::std_op3:  st_op = Op_StoreL; break;
 842     case Assembler::stf_op3:  st_op = Op_StoreF; break;
 843     case Assembler::stdf_op3: st_op = Op_StoreD; break;
 844 
 845     case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
 846     case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
 847     case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
 848     case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
 849     case Assembler::ldx_op3:  // may become LoadP or stay LoadI
 850     case Assembler::ldsw_op3: // may become LoadP or stay LoadI
 851     case Assembler::lduw_op3: ld_op = Op_LoadI; break;
 852     case Assembler::ldd_op3:  ld_op = Op_LoadL; break;
 853     case Assembler::ldf_op3:  ld_op = Op_LoadF; break;
 854     case Assembler::lddf_op3: ld_op = Op_LoadD; break;
 855     case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
 856 
 857     default: ShouldNotReachHere();
 858     }
 859     if (tertiary == REGP_OP) {
 860       if      (st_op == Op_StoreI)  st_op = Op_StoreP;
 861       else if (ld_op == Op_LoadI)   ld_op = Op_LoadP;
 862       else                          ShouldNotReachHere();
 863       if (st_op) {
 864         // a store
 865         // inputs are (0:control, 1:memory, 2:address, 3:value)
 866         Node* n2 = n->in(3);
 867         if (n2 != NULL) {
 868           const Type* t = n2->bottom_type();
 869           is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 870         }
 871       } else {
 872         // a load
 873         const Type* t = n->bottom_type();
 874         is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 875       }
 876     }
 877 
 878     if (ld_op) {
 879       // a Load
 880       // inputs are (0:control, 1:memory, 2:address)
 881       if (!(n->ideal_Opcode()==ld_op)       && // Following are special cases
 882           !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
 883           !(n->ideal_Opcode()==Op_LoadI     && ld_op==Op_LoadF) &&
 884           !(n->ideal_Opcode()==Op_LoadF     && ld_op==Op_LoadI) &&
 885           !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
 886           !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
 887           !(n->ideal_Opcode()==Op_LoadL     && ld_op==Op_LoadI) &&
 888           !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
 889           !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
 890           !(n->ideal_Opcode()==Op_ConvI2F   && ld_op==Op_LoadF) &&
 891           !(n->ideal_Opcode()==Op_ConvI2D   && ld_op==Op_LoadF) &&
 892           !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
 893           !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
 894           !(n->rule() == loadUB_rule)) {
 895         verify_oops_warning(n, n->ideal_Opcode(), ld_op);
 896       }
 897     } else if (st_op) {
 898       // a Store
 899       // inputs are (0:control, 1:memory, 2:address, 3:value)
 900       if (!(n->ideal_Opcode()==st_op)    && // Following are special cases
 901           !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
 902           !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
 903           !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
 904           !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
 905           !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
 906           !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
 907         verify_oops_warning(n, n->ideal_Opcode(), st_op);
 908       }
 909     }
 910 
 911     if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
 912       Node* addr = n->in(2);
 913       if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
 914         const TypeOopPtr* atype = addr->bottom_type()->isa_instptr();  // %%% oopptr?
 915         if (atype != NULL) {
 916           intptr_t offset = get_offset_from_base(n, atype, disp32);
 917           intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
 918           if (offset != offset_2) {
 919             get_offset_from_base(n, atype, disp32);
 920             get_offset_from_base_2(n, atype, disp32);
 921           }
 922           assert(offset == offset_2, "different offsets");
 923           if (offset == disp32) {
 924             // we now know that src1 is a true oop pointer
 925             is_verified_oop_base = true;
 926             if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
 927               if( primary == Assembler::ldd_op3 ) {
 928                 is_verified_oop_base = false; // Cannot 'ldd' into O7
 929               } else {
 930                 tmp_enc = dst_enc;
 931                 dst_enc = R_O7_enc; // Load into O7; preserve source oop
 932                 assert(src1_enc != dst_enc, "");
 933               }
 934             }
 935           }
 936           if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
 937                        || offset == oopDesc::mark_offset_in_bytes())) {
 938                       // loading the mark should not be allowed either, but
 939                       // we don't check this since it conflicts with InlineObjectHash
 940                       // usage of LoadINode to get the mark. We could keep the
 941                       // check if we create a new LoadMarkNode
 942             // but do not verify the object before its header is initialized
 943             ShouldNotReachHere();
 944           }
 945         }
 946       }
 947     }
 948   }
 949 #endif
 950 
 951   uint instr = (Assembler::ldst_op << 30)
 952              | (dst_enc        << 25)
 953              | (primary        << 19)
 954              | (src1_enc       << 14);
 955 
 956   uint index = src2_enc;
 957   int disp = disp32;
 958 
 959   if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
 960     disp += STACK_BIAS;
 961     // Check that stack offset fits, load into O7 if not
 962     if (!Assembler::is_simm13(disp)) {
 963       MacroAssembler _masm(&cbuf);
 964       __ set(disp, O7);
 965       if (index != R_G0_enc) {
 966         __ add(O7, reg_to_register_object(index), O7);
 967       }
 968       index = R_O7_enc;
 969       disp = 0;
 970     }
 971   }
 972 
 973   if( disp == 0 ) {
 974     // use reg-reg form
 975     // bit 13 is already zero
 976     instr |= index;
 977   } else {
 978     // use reg-imm form
 979     instr |= 0x00002000;          // set bit 13 to one
 980     instr |= disp & 0x1FFF;
 981   }
 982 
 983   cbuf.insts()->emit_int32(instr);
 984 
 985 #ifdef ASSERT
 986   if (VerifyOops) {
 987     MacroAssembler _masm(&cbuf);
 988     if (is_verified_oop_base) {
 989       __ verify_oop(reg_to_register_object(src1_enc));
 990     }
 991     if (is_verified_oop_store) {
 992       __ verify_oop(reg_to_register_object(dst_enc));
 993     }
 994     if (tmp_enc != -1) {
 995       __ mov(O7, reg_to_register_object(tmp_enc));
 996     }
 997     if (is_verified_oop_load) {
 998       __ verify_oop(reg_to_register_object(dst_enc));
 999     }
1000   }
1001 #endif
1002 }
1003 
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1005   // The method which records debug information at every safepoint
1006   // expects the call to be the first instruction in the snippet as
1007   // it creates a PcDesc structure which tracks the offset of a call
1008   // from the start of the codeBlob. This offset is computed as
1009   // code_end() - code_begin() of the code which has been emitted
1010   // so far.
1011   // In this particular case we have skirted around the problem by
1012   // putting the "mov" instruction in the delay slot but the problem
1013   // may bite us again at some other point and a cleaner/generic
1014   // solution using relocations would be needed.
1015   MacroAssembler _masm(&cbuf);
1016   __ set_inst_mark();
1017 
1018   // We flush the current window just so that there is a valid stack copy
1019   // the fact that the current window becomes active again instantly is
1020   // not a problem there is nothing live in it.
1021 
1022 #ifdef ASSERT
1023   int startpos = __ offset();
1024 #endif /* ASSERT */
1025 
1026   __ call((address)entry_point, rspec);
1027 
1028   if (preserve_g2)   __ delayed()->mov(G2, L7);
1029   else __ delayed()->nop();
1030 
1031   if (preserve_g2)   __ mov(L7, G2);
1032 
1033 #ifdef ASSERT
1034   if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036     // Trash argument dump slots.
1037     __ set(0xb0b8ac0db0b8ac0d, G1);
1038     __ mov(G1, G5);
1039     __ stx(G1, SP, STACK_BIAS + 0x80);
1040     __ stx(G1, SP, STACK_BIAS + 0x88);
1041     __ stx(G1, SP, STACK_BIAS + 0x90);
1042     __ stx(G1, SP, STACK_BIAS + 0x98);
1043     __ stx(G1, SP, STACK_BIAS + 0xA0);
1044     __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046     // this is also a native call, so smash the first 7 stack locations,
1047     // and the various registers
1048 
1049     // Note:  [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050     // while [SP+0x44..0x58] are the argument dump slots.
1051     __ set((intptr_t)0xbaadf00d, G1);
1052     __ mov(G1, G5);
1053     __ sllx(G1, 32, G1);
1054     __ or3(G1, G5, G1);
1055     __ mov(G1, G5);
1056     __ stx(G1, SP, 0x40);
1057     __ stx(G1, SP, 0x48);
1058     __ stx(G1, SP, 0x50);
1059     __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061   }
1062 #endif /*ASSERT*/
1063 }
1064 
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) {  }
1068 void emit_hi(CodeBuffer &cbuf, int val) {  }
1069 
1070 
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073 
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075   if (UseRDPCForConstantTableBase) {
1076     // The table base offset might be less but then it fits into
1077     // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078     return Assembler::min_simm13();
1079   } else {
1080     int offset = -(size() / 2);
1081     if (!Assembler::is_simm13(offset)) {
1082       offset = Assembler::min_simm13();
1083     }
1084     return offset;
1085   }
1086 }
1087 
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090   ShouldNotReachHere();
1091 }
1092 
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094   Compile* C = ra_->C;
1095   Compile::ConstantTable& constant_table = C->constant_table();
1096   MacroAssembler _masm(&cbuf);
1097 
1098   Register r = as_Register(ra_->get_encode(this));
1099   CodeSection* consts_section = __ code()->consts();
1100   int consts_size = consts_section->align_at_start(consts_section->size());
1101   assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102 
1103   if (UseRDPCForConstantTableBase) {
1104     // For the following RDPC logic to work correctly the consts
1105     // section must be allocated right before the insts section.  This
1106     // assert checks for that.  The layout and the SECT_* constants
1107     // are defined in src/share/vm/asm/codeBuffer.hpp.
1108     assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109     int insts_offset = __ offset();
1110 
1111     // Layout:
1112     //
1113     // |----------- consts section ------------|----------- insts section -----------...
1114     // |------ constant table -----|- padding -|------------------x----
1115     //                                                            \ current PC (RDPC instruction)
1116     // |<------------- consts_size ----------->|<- insts_offset ->|
1117     //                                                            \ table base
1118     // The table base offset is later added to the load displacement
1119     // so it has to be negative.
1120     int table_base_offset = -(consts_size + insts_offset);
1121     int disp;
1122 
1123     // If the displacement from the current PC to the constant table
1124     // base fits into simm13 we set the constant table base to the
1125     // current PC.
1126     if (Assembler::is_simm13(table_base_offset)) {
1127       constant_table.set_table_base_offset(table_base_offset);
1128       disp = 0;
1129     } else {
1130       // Otherwise we set the constant table base offset to the
1131       // maximum negative displacement of load instructions to keep
1132       // the disp as small as possible:
1133       //
1134       // |<------------- consts_size ----------->|<- insts_offset ->|
1135       // |<--------- min_simm13 --------->|<-------- disp --------->|
1136       //                                  \ table base
1137       table_base_offset = Assembler::min_simm13();
1138       constant_table.set_table_base_offset(table_base_offset);
1139       disp = (consts_size + insts_offset) + table_base_offset;
1140     }
1141 
1142     __ rdpc(r);
1143 
1144     if (disp != 0) {
1145       assert(r != O7, "need temporary");
1146       __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147     }
1148   }
1149   else {
1150     // Materialize the constant table base.
1151     address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152     RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153     AddressLiteral base(baseaddr, rspec);
1154     __ set(base, r);
1155   }
1156 }
1157 
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159   if (UseRDPCForConstantTableBase) {
1160     // This is really the worst case but generally it's only 1 instruction.
1161     return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162   } else {
1163     return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164   }
1165 }
1166 
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169   char reg[128];
1170   ra_->dump_register(this, reg);
1171   if (UseRDPCForConstantTableBase) {
1172     st->print("RDPC   %s\t! constant table base", reg);
1173   } else {
1174     st->print("SET    &constanttable,%s\t! constant table base", reg);
1175   }
1176 }
1177 #endif
1178 
1179 
1180 //=============================================================================
1181 
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184   Compile* C = ra_->C;
1185 
1186   for (int i = 0; i < OptoPrologueNops; i++) {
1187     st->print_cr("NOP"); st->print("\t");
1188   }
1189 
1190   if( VerifyThread ) {
1191     st->print_cr("Verify_Thread"); st->print("\t");
1192   }
1193 
1194   size_t framesize = C->frame_size_in_bytes();
1195   int bangsize = C->bang_size_in_bytes();
1196 
1197   // Calls to C2R adapters often do not accept exceptional returns.
1198   // We require that their callers must bang for them.  But be careful, because
1199   // some VM calls (such as call site linkage) can use several kilobytes of
1200   // stack.  But the stack safety zone should account for that.
1201   // See bugs 4446381, 4468289, 4497237.
1202   if (C->need_stack_bang(bangsize)) {
1203     st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204   }
1205 
1206   if (Assembler::is_simm13(-framesize)) {
1207     st->print   ("SAVE   R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208   } else {
1209     st->print_cr("SETHI  R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210     st->print_cr("ADD    R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211     st->print   ("SAVE   R_SP,R_G3,R_SP");
1212   }
1213 
1214 }
1215 #endif
1216 
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218   Compile* C = ra_->C;
1219   MacroAssembler _masm(&cbuf);
1220 
1221   for (int i = 0; i < OptoPrologueNops; i++) {
1222     __ nop();
1223   }
1224 
1225   __ verify_thread();
1226 
1227   size_t framesize = C->frame_size_in_bytes();
1228   assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229   assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230   int bangsize = C->bang_size_in_bytes();
1231 
1232   // Calls to C2R adapters often do not accept exceptional returns.
1233   // We require that their callers must bang for them.  But be careful, because
1234   // some VM calls (such as call site linkage) can use several kilobytes of
1235   // stack.  But the stack safety zone should account for that.
1236   // See bugs 4446381, 4468289, 4497237.
1237   if (C->need_stack_bang(bangsize)) {
1238     __ generate_stack_overflow_check(bangsize);
1239   }
1240 
1241   if (Assembler::is_simm13(-framesize)) {
1242     __ save(SP, -framesize, SP);
1243   } else {
1244     __ sethi(-framesize & ~0x3ff, G3);
1245     __ add(G3, -framesize & 0x3ff, G3);
1246     __ save(SP, G3, SP);
1247   }
1248   C->set_frame_complete( __ offset() );
1249 
1250   if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251     // NOTE: We set the table base offset here because users might be
1252     // emitted before MachConstantBaseNode.
1253     Compile::ConstantTable& constant_table = C->constant_table();
1254     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255   }
1256 }
1257 
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259   return MachNode::size(ra_);
1260 }
1261 
1262 int MachPrologNode::reloc() const {
1263   return 10; // a large enough number
1264 }
1265 
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269   Compile* C = ra_->C;
1270 
1271   if(do_polling() && ra_->C->is_method_compilation()) {
1272     st->print("SETHI  #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274     st->print("LDX    [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276     st->print("LDUW   [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278   }
1279 
1280   if(do_polling()) {
1281     if (UseCBCond && !ra_->C->is_method_compilation()) {
1282       st->print("NOP\n\t");
1283     }
1284     st->print("RET\n\t");
1285   }
1286 
1287   st->print("RESTORE");
1288 }
1289 #endif
1290 
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292   MacroAssembler _masm(&cbuf);
1293   Compile* C = ra_->C;
1294 
1295   __ verify_thread();
1296 
1297   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1298     __ reserved_stack_check();
1299   }
1300 
1301   // If this does safepoint polling, then do it here
1302   if(do_polling() && ra_->C->is_method_compilation()) {
1303     AddressLiteral polling_page(os::get_polling_page());
1304     __ sethi(polling_page, L0);
1305     __ relocate(relocInfo::poll_return_type);
1306     __ ld_ptr(L0, 0, G0);
1307   }
1308 
1309   // If this is a return, then stuff the restore in the delay slot
1310   if(do_polling()) {
1311     if (UseCBCond && !ra_->C->is_method_compilation()) {
1312       // Insert extra padding for the case when the epilogue is preceded by
1313       // a cbcond jump, which can't be followed by a CTI instruction
1314       __ nop();
1315     }
1316     __ ret();
1317     __ delayed()->restore();
1318   } else {
1319     __ restore();
1320   }
1321 }
1322 
1323 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1324   return MachNode::size(ra_);
1325 }
1326 
1327 int MachEpilogNode::reloc() const {
1328   return 16; // a large enough number
1329 }
1330 
1331 const Pipeline * MachEpilogNode::pipeline() const {
1332   return MachNode::pipeline_class();
1333 }
1334 
1335 int MachEpilogNode::safepoint_offset() const {
1336   assert( do_polling(), "no return for this epilog node");
1337   return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1338 }
1339 
1340 //=============================================================================
1341 
1342 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1343 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1344 static enum RC rc_class( OptoReg::Name reg ) {
1345   if (!OptoReg::is_valid(reg)) return rc_bad;
1346   if (OptoReg::is_stack(reg)) return rc_stack;
1347   VMReg r = OptoReg::as_VMReg(reg);
1348   if (r->is_Register()) return rc_int;
1349   assert(r->is_FloatRegister(), "must be");
1350   return rc_float;
1351 }
1352 
1353 #ifndef PRODUCT
1354 ATTRIBUTE_PRINTF(2, 3)
1355 static void print_helper(outputStream* st, const char* format, ...) {
1356   if (st->position() > 0) {
1357     st->cr();
1358     st->sp();
1359   }
1360   va_list ap;
1361   va_start(ap, format);
1362   st->vprint(format, ap);
1363   va_end(ap);
1364 }
1365 #endif // !PRODUCT
1366 
1367 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1368   if (cbuf) {
1369     emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1370   }
1371 #ifndef PRODUCT
1372   else {
1373     if (is_load) {
1374       print_helper(st, "%s   [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1375     } else {
1376       print_helper(st, "%s   R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1377     }
1378   }
1379 #endif
1380 }
1381 
1382 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1383   if (cbuf) {
1384     emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1385   }
1386 #ifndef PRODUCT
1387   else {
1388     print_helper(st, "%s  R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1389   }
1390 #endif
1391 }
1392 
1393 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1394                                                   CodeBuffer *cbuf,
1395                                                   PhaseRegAlloc *ra_,
1396                                                   outputStream* st) {
1397   // Get registers to move
1398   OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1399   OptoReg::Name src_first  = ra_->get_reg_first(mach->in(1));
1400   OptoReg::Name dst_second = ra_->get_reg_second(mach);
1401   OptoReg::Name dst_first  = ra_->get_reg_first(mach);
1402 
1403   enum RC src_second_rc = rc_class(src_second);
1404   enum RC src_first_rc  = rc_class(src_first);
1405   enum RC dst_second_rc = rc_class(dst_second);
1406   enum RC dst_first_rc  = rc_class(dst_first);
1407 
1408   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1409 
1410   if (src_first == dst_first && src_second == dst_second) {
1411     return; // Self copy, no move
1412   }
1413 
1414   // --------------------------------------
1415   // Check for mem-mem move.  Load into unused float registers and fall into
1416   // the float-store case.
1417   if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1418     int offset = ra_->reg2offset(src_first);
1419     // Further check for aligned-adjacent pair, so we can use a double load
1420     if ((src_first&1) == 0 && src_first+1 == src_second) {
1421       src_second    = OptoReg::Name(R_F31_num);
1422       src_second_rc = rc_float;
1423       impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1424     } else {
1425       impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1426     }
1427     src_first    = OptoReg::Name(R_F30_num);
1428     src_first_rc = rc_float;
1429   }
1430 
1431   if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1432     int offset = ra_->reg2offset(src_second);
1433     impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1434     src_second    = OptoReg::Name(R_F31_num);
1435     src_second_rc = rc_float;
1436   }
1437 
1438   // --------------------------------------
1439   // Check for float->int copy; requires a trip through memory
1440   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1441     int offset = frame::register_save_words*wordSize;
1442     if (cbuf) {
1443       emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1444       impl_helper(mach, cbuf, ra_, false, offset, src_first,  Assembler::stf_op3, "STF ", st);
1445       impl_helper(mach, cbuf, ra_,  true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1446       emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1447     }
1448 #ifndef PRODUCT
1449     else {
1450       print_helper(st, "SUB    R_SP,16,R_SP");
1451       impl_helper(mach, cbuf, ra_, false, offset, src_first,  Assembler::stf_op3, "STF ", st);
1452       impl_helper(mach, cbuf, ra_,  true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1453       print_helper(st, "ADD    R_SP,16,R_SP");
1454     }
1455 #endif
1456   }
1457 
1458   // Check for float->int copy on T4
1459   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1460     // Further check for aligned-adjacent pair, so we can use a double move
1461     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1462       impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1463       return;
1464     }
1465     impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1466   }
1467   // Check for int->float copy on T4
1468   if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1469     // Further check for aligned-adjacent pair, so we can use a double move
1470     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1471       impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1472       return;
1473     }
1474     impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1475   }
1476 
1477   // --------------------------------------
1478   // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1479   // In such cases, I have to do the big-endian swap.  For aligned targets, the
1480   // hardware does the flop for me.  Doubles are always aligned, so no problem
1481   // there.  Misaligned sources only come from native-long-returns (handled
1482   // special below).
1483 #ifndef _LP64
1484   if (src_first_rc == rc_int &&     // source is already big-endian
1485       src_second_rc != rc_bad &&    // 64-bit move
1486       ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst
1487     assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned");
1488     // Do the big-endian flop.
1489     OptoReg::Name tmp    = dst_first   ; dst_first    = dst_second   ; dst_second    = tmp   ;
1490     enum RC       tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1491   }
1492 #endif
1493 
1494   // --------------------------------------
1495   // Check for integer reg-reg copy
1496   if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1497 #ifndef _LP64
1498     if (src_first == R_O0_num && src_second == R_O1_num) {  // Check for the evil O0/O1 native long-return case
1499       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1500       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1501       //       operand contains the least significant word of the 64-bit value and vice versa.
1502       OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1503       assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1504       // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1505       if ( cbuf ) {
1506         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020);
1507         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000);
1508         emit3       (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]);
1509 #ifndef PRODUCT
1510       } else {
1511         print_helper(st, "SLLX   R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1512         print_helper(st, "SRL    R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1513         print_helper(st, "OR     R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1514 #endif
1515       }
1516       return;
1517     } else if (dst_first == R_I0_num && dst_second == R_I1_num) {
1518       // returning a long value in I0/I1
1519       // a SpillCopy must be able to target a return instruction's reg_class
1520       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1521       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1522       //       operand contains the least significant word of the 64-bit value and vice versa.
1523       OptoReg::Name tdest = dst_first;
1524 
1525       if (src_first == dst_first) {
1526         tdest = OptoReg::Name(R_O7_num);
1527       }
1528 
1529       if (cbuf) {
1530         assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1531         // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1532         // ShrL_reg_imm6
1533         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000);
1534         // ShrR_reg_imm6  src, 0, dst
1535         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000);
1536         if (tdest != dst_first) {
1537           emit3     (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]);
1538         }
1539       }
1540 #ifndef PRODUCT
1541       else {
1542         print_helper(st, "SRLX   R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1543         print_helper(st, "SRL    R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1544         if (tdest != dst_first) {
1545           print_helper(st, "MOV    R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1546         }
1547       }
1548 #endif // PRODUCT
1549       return size+8;
1550     }
1551 #endif // !_LP64
1552     // Else normal reg-reg copy
1553     assert(src_second != dst_first, "smashed second before evacuating it");
1554     impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV  ", st);
1555     assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1556     // This moves an aligned adjacent pair.
1557     // See if we are done.
1558     if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1559       return;
1560     }
1561   }
1562 
1563   // Check for integer store
1564   if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1565     int offset = ra_->reg2offset(dst_first);
1566     // Further check for aligned-adjacent pair, so we can use a double store
1567     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1568       impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1569       return;
1570     }
1571     impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1572   }
1573 
1574   // Check for integer load
1575   if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1576     int offset = ra_->reg2offset(src_first);
1577     // Further check for aligned-adjacent pair, so we can use a double load
1578     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1579       impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1580       return;
1581     }
1582     impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1583   }
1584 
1585   // Check for float reg-reg copy
1586   if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1587     // Further check for aligned-adjacent pair, so we can use a double move
1588     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1589       impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1590       return;
1591     }
1592     impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1593   }
1594 
1595   // Check for float store
1596   if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1597     int offset = ra_->reg2offset(dst_first);
1598     // Further check for aligned-adjacent pair, so we can use a double store
1599     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1600       impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1601       return;
1602     }
1603     impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1604   }
1605 
1606   // Check for float load
1607   if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1608     int offset = ra_->reg2offset(src_first);
1609     // Further check for aligned-adjacent pair, so we can use a double load
1610     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1611       impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1612       return;
1613     }
1614     impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1615   }
1616 
1617   // --------------------------------------------------------------------
1618   // Check for hi bits still needing moving.  Only happens for misaligned
1619   // arguments to native calls.
1620   if (src_second == dst_second) {
1621     return; // Self copy; no move
1622   }
1623   assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1624 
1625 #ifndef _LP64
1626   // In the LP64 build, all registers can be moved as aligned/adjacent
1627   // pairs, so there's never any need to move the high bits separately.
1628   // The 32-bit builds have to deal with the 32-bit ABI which can force
1629   // all sorts of silly alignment problems.
1630 
1631   // Check for integer reg-reg copy.  Hi bits are stuck up in the top
1632   // 32-bits of a 64-bit register, but are needed in low bits of another
1633   // register (else it's a hi-bits-to-hi-bits copy which should have
1634   // happened already as part of a 64-bit move)
1635   if (src_second_rc == rc_int && dst_second_rc == rc_int) {
1636     assert((src_second & 1) == 1, "its the evil O0/O1 native return case");
1637     assert((dst_second & 1) == 0, "should have moved with 1 64-bit move");
1638     // Shift src_second down to dst_second's low bits.
1639     if (cbuf) {
1640       emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1641 #ifndef PRODUCT
1642     } else  {
1643       print_helper(st, "SRLX   R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second));
1644 #endif
1645     }
1646     return;
1647   }
1648 
1649   // Check for high word integer store.  Must down-shift the hi bits
1650   // into a temp register, then fall into the case of storing int bits.
1651   if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) {
1652     // Shift src_second down to dst_second's low bits.
1653     if (cbuf) {
1654       emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1655 #ifndef PRODUCT
1656     } else {
1657       print_helper(st, "SRLX   R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num));
1658 #endif
1659     }
1660     src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1661   }
1662 
1663   // Check for high word integer load
1664   if (dst_second_rc == rc_int && src_second_rc == rc_stack)
1665     return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st);
1666 
1667   // Check for high word integer store
1668   if (src_second_rc == rc_int && dst_second_rc == rc_stack)
1669     return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st);
1670 
1671   // Check for high word float store
1672   if (src_second_rc == rc_float && dst_second_rc == rc_stack)
1673     return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st);
1674 
1675 #endif // !_LP64
1676 
1677   Unimplemented();
1678 }
1679 
1680 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1681                                        PhaseRegAlloc *ra_,
1682                                        bool do_size,
1683                                        outputStream* st) const {
1684   assert(!do_size, "not supported");
1685   mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1686   return 0;
1687 }
1688 
1689 #ifndef PRODUCT
1690 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1691   implementation( NULL, ra_, false, st );
1692 }
1693 #endif
1694 
1695 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1696   implementation( &cbuf, ra_, false, NULL );
1697 }
1698 
1699 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1700   return MachNode::size(ra_);
1701 }
1702 
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1706   st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1707 }
1708 #endif
1709 
1710 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1711   MacroAssembler _masm(&cbuf);
1712   for (int i = 0; i < _count; i += 1) {
1713     __ nop();
1714   }
1715 }
1716 
1717 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1718   return 4 * _count;
1719 }
1720 
1721 
1722 //=============================================================================
1723 #ifndef PRODUCT
1724 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1725   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1726   int reg = ra_->get_reg_first(this);
1727   st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1728 }
1729 #endif
1730 
1731 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1732   MacroAssembler _masm(&cbuf);
1733   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1734   int reg = ra_->get_encode(this);
1735 
1736   if (Assembler::is_simm13(offset)) {
1737      __ add(SP, offset, reg_to_register_object(reg));
1738   } else {
1739      __ set(offset, O7);
1740      __ add(SP, O7, reg_to_register_object(reg));
1741   }
1742 }
1743 
1744 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1745   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1746   assert(ra_ == ra_->C->regalloc(), "sanity");
1747   return ra_->C->scratch_emit_size(this);
1748 }
1749 
1750 //=============================================================================
1751 #ifndef PRODUCT
1752 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1753   st->print_cr("\nUEP:");
1754 #ifdef    _LP64
1755   if (UseCompressedClassPointers) {
1756     assert(Universe::heap() != NULL, "java heap should be initialized");
1757     st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1758     if (Universe::narrow_klass_base() != 0) {
1759       st->print_cr("\tSET    Universe::narrow_klass_base,R_G6_heap_base");
1760       if (Universe::narrow_klass_shift() != 0) {
1761         st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
1762       }
1763       st->print_cr("\tADD    R_G5,R_G6_heap_base,R_G5");
1764       st->print_cr("\tSET    Universe::narrow_ptrs_base,R_G6_heap_base");
1765     } else {
1766       st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
1767     }
1768   } else {
1769     st->print_cr("\tLDX    [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1770   }
1771   st->print_cr("\tCMP    R_G5,R_G3" );
1772   st->print   ("\tTne    xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1773 #else  // _LP64
1774   st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1775   st->print_cr("\tCMP    R_G5,R_G3" );
1776   st->print   ("\tTne    icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1777 #endif // _LP64
1778 }
1779 #endif
1780 
1781 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1782   MacroAssembler _masm(&cbuf);
1783   Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());
1784   Register temp_reg   = G3;
1785   assert( G5_ic_reg != temp_reg, "conflicting registers" );
1786 
1787   // Load klass from receiver
1788   __ load_klass(O0, temp_reg);
1789   // Compare against expected klass
1790   __ cmp(temp_reg, G5_ic_reg);
1791   // Branch to miss code, checks xcc or icc depending
1792   __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1793 }
1794 
1795 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1796   return MachNode::size(ra_);
1797 }
1798 
1799 
1800 //=============================================================================
1801 
1802 
1803 // Emit exception handler code.
1804 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1805   Register temp_reg = G3;
1806   AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1807   MacroAssembler _masm(&cbuf);
1808 
1809   address base = __ start_a_stub(size_exception_handler());
1810   if (base == NULL) {
1811     ciEnv::current()->record_failure("CodeCache is full");
1812     return 0;  // CodeBuffer::expand failed
1813   }
1814 
1815   int offset = __ offset();
1816 
1817   __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1818   __ delayed()->nop();
1819 
1820   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1821 
1822   __ end_a_stub();
1823 
1824   return offset;
1825 }
1826 
1827 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1828   // Can't use any of the current frame's registers as we may have deopted
1829   // at a poll and everything (including G3) can be live.
1830   Register temp_reg = L0;
1831   AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1832   MacroAssembler _masm(&cbuf);
1833 
1834   address base = __ start_a_stub(size_deopt_handler());
1835   if (base == NULL) {
1836     ciEnv::current()->record_failure("CodeCache is full");
1837     return 0;  // CodeBuffer::expand failed
1838   }
1839 
1840   int offset = __ offset();
1841   __ save_frame(0);
1842   __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1843   __ delayed()->restore();
1844 
1845   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1846 
1847   __ end_a_stub();
1848   return offset;
1849 
1850 }
1851 
1852 // Given a register encoding, produce a Integer Register object
1853 static Register reg_to_register_object(int register_encoding) {
1854   assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1855   return as_Register(register_encoding);
1856 }
1857 
1858 // Given a register encoding, produce a single-precision Float Register object
1859 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1860   assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1861   return as_SingleFloatRegister(register_encoding);
1862 }
1863 
1864 // Given a register encoding, produce a double-precision Float Register object
1865 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1866   assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1867   assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1868   return as_DoubleFloatRegister(register_encoding);
1869 }
1870 
1871 const bool Matcher::match_rule_supported(int opcode) {
1872   if (!has_match_rule(opcode))
1873     return false;
1874 
1875   switch (opcode) {
1876   case Op_CountLeadingZerosI:
1877   case Op_CountLeadingZerosL:
1878   case Op_CountTrailingZerosI:
1879   case Op_CountTrailingZerosL:
1880   case Op_PopCountI:
1881   case Op_PopCountL:
1882     if (!UsePopCountInstruction)
1883       return false;
1884   case Op_CompareAndSwapL:
1885 #ifdef _LP64
1886   case Op_CompareAndSwapP:
1887 #endif
1888     if (!VM_Version::supports_cx8())
1889       return false;
1890     break;
1891   }
1892 
1893   return true;  // Per default match rules are supported.
1894 }
1895 
1896 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1897 
1898   // TODO
1899   // identify extra cases that we might want to provide match rules for
1900   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1901   bool ret_value = match_rule_supported(opcode);
1902   // Add rules here.
1903 
1904   return ret_value;  // Per default match rules are supported.
1905 }
1906 
1907 const bool Matcher::has_predicated_vectors(void) {
1908   return false;
1909 }
1910 
1911 const int Matcher::float_pressure(int default_pressure_threshold) {
1912   return default_pressure_threshold;
1913 }
1914 
1915 int Matcher::regnum_to_fpu_offset(int regnum) {
1916   return regnum - 32; // The FP registers are in the second chunk
1917 }
1918 
1919 #ifdef ASSERT
1920 address last_rethrow = NULL;  // debugging aid for Rethrow encoding
1921 #endif
1922 
1923 // Vector width in bytes
1924 const int Matcher::vector_width_in_bytes(BasicType bt) {
1925   assert(MaxVectorSize == 8, "");
1926   return 8;
1927 }
1928 
1929 // Vector ideal reg
1930 const Opcodes Matcher::vector_ideal_reg(int size) {
1931   assert(MaxVectorSize == 8, "");
1932   return Opcodes::Op_RegD;
1933 }
1934 
1935 const Opcodes Matcher::vector_shift_count_ideal_reg(int size) {
1936   fatal("vector shift is not supported");
1937   return Opcodes::NotAMachineReg;
1938 }
1939 
1940 // Limits on vector size (number of elements) loaded into vector.
1941 const int Matcher::max_vector_size(const BasicType bt) {
1942   assert(is_java_primitive(bt), "only primitive type vectors");
1943   return vector_width_in_bytes(bt)/type2aelembytes(bt);
1944 }
1945 
1946 const int Matcher::min_vector_size(const BasicType bt) {
1947   return max_vector_size(bt); // Same as max.
1948 }
1949 
1950 // SPARC doesn't support misaligned vectors store/load.
1951 const bool Matcher::misaligned_vectors_ok() {
1952   return false;
1953 }
1954 
1955 // Current (2013) SPARC platforms need to read original key
1956 // to construct decryption expanded key
1957 const bool Matcher::pass_original_key_for_aes() {
1958   return true;
1959 }
1960 
1961 // USII supports fxtof through the whole range of number, USIII doesn't
1962 const bool Matcher::convL2FSupported(void) {
1963   return VM_Version::has_fast_fxtof();
1964 }
1965 
1966 // Is this branch offset short enough that a short branch can be used?
1967 //
1968 // NOTE: If the platform does not provide any short branch variants, then
1969 //       this method should return false for offset 0.
1970 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1971   // The passed offset is relative to address of the branch.
1972   // Don't need to adjust the offset.
1973   return UseCBCond && Assembler::is_simm12(offset);
1974 }
1975 
1976 const bool Matcher::isSimpleConstant64(jlong value) {
1977   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1978   // Depends on optimizations in MacroAssembler::setx.
1979   int hi = (int)(value >> 32);
1980   int lo = (int)(value & ~0);
1981   return (hi == 0) || (hi == -1) || (lo == 0);
1982 }
1983 
1984 // No scaling for the parameter the ClearArray node.
1985 const bool Matcher::init_array_count_is_in_bytes = true;
1986 
1987 // No additional cost for CMOVL.
1988 const int Matcher::long_cmove_cost() { return 0; }
1989 
1990 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1991 const int Matcher::float_cmove_cost() {
1992   return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1993 }
1994 
1995 // Does the CPU require late expand (see block.cpp for description of late expand)?
1996 const bool Matcher::require_postalloc_expand = false;
1997 
1998 // Do we need to mask the count passed to shift instructions or does
1999 // the cpu only look at the lower 5/6 bits anyway?
2000 const bool Matcher::need_masked_shift_count = false;
2001 
2002 bool Matcher::narrow_oop_use_complex_address() {
2003   NOT_LP64(ShouldNotCallThis());
2004   assert(UseCompressedOops, "only for compressed oops code");
2005   return false;
2006 }
2007 
2008 bool Matcher::narrow_klass_use_complex_address() {
2009   NOT_LP64(ShouldNotCallThis());
2010   assert(UseCompressedClassPointers, "only for compressed klass code");
2011   return false;
2012 }
2013 
2014 // Is it better to copy float constants, or load them directly from memory?
2015 // Intel can load a float constant from a direct address, requiring no
2016 // extra registers.  Most RISCs will have to materialize an address into a
2017 // register first, so they would do better to copy the constant from stack.
2018 const bool Matcher::rematerialize_float_constants = false;
2019 
2020 // If CPU can load and store mis-aligned doubles directly then no fixup is
2021 // needed.  Else we split the double into 2 integer pieces and move it
2022 // piece-by-piece.  Only happens when passing doubles into C code as the
2023 // Java calling convention forces doubles to be aligned.
2024 #ifdef _LP64
2025 const bool Matcher::misaligned_doubles_ok = true;
2026 #else
2027 const bool Matcher::misaligned_doubles_ok = false;
2028 #endif
2029 
2030 // No-op on SPARC.
2031 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2032 }
2033 
2034 // Advertise here if the CPU requires explicit rounding operations
2035 // to implement the UseStrictFP mode.
2036 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2037 
2038 // Are floats converted to double when stored to stack during deoptimization?
2039 // Sparc does not handle callee-save floats.
2040 bool Matcher::float_in_double() { return false; }
2041 
2042 // Do ints take an entire long register or just half?
2043 // Note that we if-def off of _LP64.
2044 // The relevant question is how the int is callee-saved.  In _LP64
2045 // the whole long is written but de-opt'ing will have to extract
2046 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2047 #ifdef _LP64
2048 const bool Matcher::int_in_long = true;
2049 #else
2050 const bool Matcher::int_in_long = false;
2051 #endif
2052 
2053 // Return whether or not this register is ever used as an argument.  This
2054 // function is used on startup to build the trampoline stubs in generateOptoStub.
2055 // Registers not mentioned will be killed by the VM call in the trampoline, and
2056 // arguments in those registers not be available to the callee.
2057 bool Matcher::can_be_java_arg( int reg ) {
2058   // Standard sparc 6 args in registers
2059   if( reg == R_I0_num ||
2060       reg == R_I1_num ||
2061       reg == R_I2_num ||
2062       reg == R_I3_num ||
2063       reg == R_I4_num ||
2064       reg == R_I5_num ) return true;
2065 #ifdef _LP64
2066   // 64-bit builds can pass 64-bit pointers and longs in
2067   // the high I registers
2068   if( reg == R_I0H_num ||
2069       reg == R_I1H_num ||
2070       reg == R_I2H_num ||
2071       reg == R_I3H_num ||
2072       reg == R_I4H_num ||
2073       reg == R_I5H_num ) return true;
2074 
2075   if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2076     return true;
2077   }
2078 
2079 #else
2080   // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2081   // Longs cannot be passed in O regs, because O regs become I regs
2082   // after a 'save' and I regs get their high bits chopped off on
2083   // interrupt.
2084   if( reg == R_G1H_num || reg == R_G1_num ) return true;
2085   if( reg == R_G4H_num || reg == R_G4_num ) return true;
2086 #endif
2087   // A few float args in registers
2088   if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2089 
2090   return false;
2091 }
2092 
2093 bool Matcher::is_spillable_arg( int reg ) {
2094   return can_be_java_arg(reg);
2095 }
2096 
2097 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2098   // Use hardware SDIVX instruction when it is
2099   // faster than a code which use multiply.
2100   return VM_Version::has_fast_idiv();
2101 }
2102 
2103 // Register for DIVI projection of divmodI
2104 RegMask Matcher::divI_proj_mask() {
2105   ShouldNotReachHere();
2106   return RegMask();
2107 }
2108 
2109 // Register for MODI projection of divmodI
2110 RegMask Matcher::modI_proj_mask() {
2111   ShouldNotReachHere();
2112   return RegMask();
2113 }
2114 
2115 // Register for DIVL projection of divmodL
2116 RegMask Matcher::divL_proj_mask() {
2117   ShouldNotReachHere();
2118   return RegMask();
2119 }
2120 
2121 // Register for MODL projection of divmodL
2122 RegMask Matcher::modL_proj_mask() {
2123   ShouldNotReachHere();
2124   return RegMask();
2125 }
2126 
2127 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2128   return L7_REGP_mask();
2129 }
2130 
2131 
2132 const bool Matcher::convi2l_type_required = true;
2133 
2134 // Should the Matcher clone shifts on addressing modes, expecting them
2135 // to be subsumed into complex addressing expressions or compute them
2136 // into registers?
2137 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2138   return clone_base_plus_offset_address(m, mstack, address_visited);
2139 }
2140 
2141 void Compile::reshape_address(AddPNode* addp) {
2142 }
2143 
2144 %}
2145 
2146 
2147 // The intptr_t operand types, defined by textual substitution.
2148 // (Cf. opto/type.hpp.  This lets us avoid many, many other ifdefs.)
2149 #ifdef _LP64
2150 #define immX      immL
2151 #define immX13    immL13
2152 #define immX13m7  immL13m7
2153 #define iRegX     iRegL
2154 #define g1RegX    g1RegL
2155 #else
2156 #define immX      immI
2157 #define immX13    immI13
2158 #define immX13m7  immI13m7
2159 #define iRegX     iRegI
2160 #define g1RegX    g1RegI
2161 #endif
2162 
2163 //----------ENCODING BLOCK-----------------------------------------------------
2164 // This block specifies the encoding classes used by the compiler to output
2165 // byte streams.  Encoding classes are parameterized macros used by
2166 // Machine Instruction Nodes in order to generate the bit encoding of the
2167 // instruction.  Operands specify their base encoding interface with the
2168 // interface keyword.  There are currently supported four interfaces,
2169 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
2170 // operand to generate a function which returns its register number when
2171 // queried.   CONST_INTER causes an operand to generate a function which
2172 // returns the value of the constant when queried.  MEMORY_INTER causes an
2173 // operand to generate four functions which return the Base Register, the
2174 // Index Register, the Scale Value, and the Offset Value of the operand when
2175 // queried.  COND_INTER causes an operand to generate six functions which
2176 // return the encoding code (ie - encoding bits for the instruction)
2177 // associated with each basic boolean condition for a conditional instruction.
2178 //
2179 // Instructions specify two basic values for encoding.  Again, a function
2180 // is available to check if the constant displacement is an oop. They use the
2181 // ins_encode keyword to specify their encoding classes (which must be
2182 // a sequence of enc_class names, and their parameters, specified in
2183 // the encoding block), and they use the
2184 // opcode keyword to specify, in order, their primary, secondary, and
2185 // tertiary opcode.  Only the opcode sections which a particular instruction
2186 // needs for encoding need to be specified.
2187 encode %{
2188   enc_class enc_untested %{
2189 #ifdef ASSERT
2190     MacroAssembler _masm(&cbuf);
2191     __ untested("encoding");
2192 #endif
2193   %}
2194 
2195   enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2196     emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2197                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2198   %}
2199 
2200   enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2201     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2202                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2203   %}
2204 
2205   enc_class form3_mem_prefetch_read( memory mem ) %{
2206     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2207                        $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2208   %}
2209 
2210   enc_class form3_mem_prefetch_write( memory mem ) %{
2211     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2212                        $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2213   %}
2214 
2215   enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2216     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
2217     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2218     guarantee($mem$$index == R_G0_enc, "double index?");
2219     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2220     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg );
2221     emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2222     emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2223   %}
2224 
2225   enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2226     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
2227     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2228     guarantee($mem$$index == R_G0_enc, "double index?");
2229     // Load long with 2 instructions
2230     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg+0 );
2231     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2232   %}
2233 
2234   //%%% form3_mem_plus_4_reg is a hack--get rid of it
2235   enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2236     guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2237     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2238   %}
2239 
2240   enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2241     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2242     if( $rs2$$reg != $rd$$reg )
2243       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2244   %}
2245 
2246   // Target lo half of long
2247   enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2248     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2249     if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2250       emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2251   %}
2252 
2253   // Source lo half of long
2254   enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2255     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2256     if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2257       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2258   %}
2259 
2260   // Target hi half of long
2261   enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2262     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2263   %}
2264 
2265   // Source lo half of long, and leave it sign extended.
2266   enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2267     // Sign extend low half
2268     emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2269   %}
2270 
2271   // Source hi half of long, and leave it sign extended.
2272   enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2273     // Shift high half to low half
2274     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2275   %}
2276 
2277   // Source hi half of long
2278   enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2279     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2280     if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2281       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2282   %}
2283 
2284   enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2285     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2286   %}
2287 
2288   enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2289     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, 0, 0, $src$$reg );
2290     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2291   %}
2292 
2293   enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2294     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2295     // clear if nothing else is happening
2296     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  0 );
2297     // blt,a,pn done
2298     emit2_19    ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2299     // mov dst,-1 in delay slot
2300     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2301   %}
2302 
2303   enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2304     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2305   %}
2306 
2307   enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2308     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2309   %}
2310 
2311   enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2312     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2313   %}
2314 
2315   enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2316     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2317   %}
2318 
2319   enc_class move_return_pc_to_o1() %{
2320     emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2321   %}
2322 
2323 #ifdef _LP64
2324   /* %%% merge with enc_to_bool */
2325   enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2326     MacroAssembler _masm(&cbuf);
2327 
2328     Register   src_reg = reg_to_register_object($src$$reg);
2329     Register   dst_reg = reg_to_register_object($dst$$reg);
2330     __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2331   %}
2332 #endif
2333 
2334   enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2335     // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2336     MacroAssembler _masm(&cbuf);
2337 
2338     Register   p_reg = reg_to_register_object($p$$reg);
2339     Register   q_reg = reg_to_register_object($q$$reg);
2340     Register   y_reg = reg_to_register_object($y$$reg);
2341     Register tmp_reg = reg_to_register_object($tmp$$reg);
2342 
2343     __ subcc( p_reg, q_reg,   p_reg );
2344     __ add  ( p_reg, y_reg, tmp_reg );
2345     __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2346   %}
2347 
2348   enc_class form_d2i_helper(regD src, regF dst) %{
2349     // fcmp %fcc0,$src,$src
2350     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2351     // branch %fcc0 not-nan, predict taken
2352     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2353     // fdtoi $src,$dst
2354     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtoi_opf, $src$$reg );
2355     // fitos $dst,$dst (if nan)
2356     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2357     // clear $dst (if nan)
2358     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2359     // carry on here...
2360   %}
2361 
2362   enc_class form_d2l_helper(regD src, regD dst) %{
2363     // fcmp %fcc0,$src,$src  check for NAN
2364     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2365     // branch %fcc0 not-nan, predict taken
2366     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2367     // fdtox $src,$dst   convert in delay slot
2368     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtox_opf, $src$$reg );
2369     // fxtod $dst,$dst  (if nan)
2370     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2371     // clear $dst (if nan)
2372     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2373     // carry on here...
2374   %}
2375 
2376   enc_class form_f2i_helper(regF src, regF dst) %{
2377     // fcmps %fcc0,$src,$src
2378     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2379     // branch %fcc0 not-nan, predict taken
2380     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2381     // fstoi $src,$dst
2382     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstoi_opf, $src$$reg );
2383     // fitos $dst,$dst (if nan)
2384     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2385     // clear $dst (if nan)
2386     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2387     // carry on here...
2388   %}
2389 
2390   enc_class form_f2l_helper(regF src, regD dst) %{
2391     // fcmps %fcc0,$src,$src
2392     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2393     // branch %fcc0 not-nan, predict taken
2394     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2395     // fstox $src,$dst
2396     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstox_opf, $src$$reg );
2397     // fxtod $dst,$dst (if nan)
2398     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2399     // clear $dst (if nan)
2400     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2401     // carry on here...
2402   %}
2403 
2404   enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2405   enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2406   enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2407   enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2408 
2409   enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2410 
2411   enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2412   enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2413 
2414   enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2415     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2416   %}
2417 
2418   enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2419     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2420   %}
2421 
2422   enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2423     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2424   %}
2425 
2426   enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2427     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2428   %}
2429 
2430   enc_class form3_convI2F(regF rs2, regF rd) %{
2431     emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2432   %}
2433 
2434   // Encloding class for traceable jumps
2435   enc_class form_jmpl(g3RegP dest) %{
2436     emit_jmpl(cbuf, $dest$$reg);
2437   %}
2438 
2439   enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2440     emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2441   %}
2442 
2443   enc_class form2_nop() %{
2444     emit_nop(cbuf);
2445   %}
2446 
2447   enc_class form2_illtrap() %{
2448     emit_illtrap(cbuf);
2449   %}
2450 
2451 
2452   // Compare longs and convert into -1, 0, 1.
2453   enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2454     // CMP $src1,$src2
2455     emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2456     // blt,a,pn done
2457     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less   , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2458     // mov dst,-1 in delay slot
2459     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2460     // bgt,a,pn done
2461     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2462     // mov dst,1 in delay slot
2463     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  1 );
2464     // CLR    $dst
2465     emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2466   %}
2467 
2468   enc_class enc_PartialSubtypeCheck() %{
2469     MacroAssembler _masm(&cbuf);
2470     __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2471     __ delayed()->nop();
2472   %}
2473 
2474   enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2475     MacroAssembler _masm(&cbuf);
2476     Label* L = $labl$$label;
2477     Assembler::Predict predict_taken =
2478       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2479 
2480     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2481     __ delayed()->nop();
2482   %}
2483 
2484   enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2485     MacroAssembler _masm(&cbuf);
2486     Label* L = $labl$$label;
2487     Assembler::Predict predict_taken =
2488       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2489 
2490     __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2491     __ delayed()->nop();
2492   %}
2493 
2494   enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2495     int op = (Assembler::arith_op << 30) |
2496              ($dst$$reg << 25) |
2497              (Assembler::movcc_op3 << 19) |
2498              (1 << 18) |                    // cc2 bit for 'icc'
2499              ($cmp$$cmpcode << 14) |
2500              (0 << 13) |                    // select register move
2501              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc' or 'xcc'
2502              ($src$$reg << 0);
2503     cbuf.insts()->emit_int32(op);
2504   %}
2505 
2506   enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2507     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2508     int op = (Assembler::arith_op << 30) |
2509              ($dst$$reg << 25) |
2510              (Assembler::movcc_op3 << 19) |
2511              (1 << 18) |                    // cc2 bit for 'icc'
2512              ($cmp$$cmpcode << 14) |
2513              (1 << 13) |                    // select immediate move
2514              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc'
2515              (simm11 << 0);
2516     cbuf.insts()->emit_int32(op);
2517   %}
2518 
2519   enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2520     int op = (Assembler::arith_op << 30) |
2521              ($dst$$reg << 25) |
2522              (Assembler::movcc_op3 << 19) |
2523              (0 << 18) |                    // cc2 bit for 'fccX'
2524              ($cmp$$cmpcode << 14) |
2525              (0 << 13) |                    // select register move
2526              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2527              ($src$$reg << 0);
2528     cbuf.insts()->emit_int32(op);
2529   %}
2530 
2531   enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2532     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2533     int op = (Assembler::arith_op << 30) |
2534              ($dst$$reg << 25) |
2535              (Assembler::movcc_op3 << 19) |
2536              (0 << 18) |                    // cc2 bit for 'fccX'
2537              ($cmp$$cmpcode << 14) |
2538              (1 << 13) |                    // select immediate move
2539              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2540              (simm11 << 0);
2541     cbuf.insts()->emit_int32(op);
2542   %}
2543 
2544   enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2545     int op = (Assembler::arith_op << 30) |
2546              ($dst$$reg << 25) |
2547              (Assembler::fpop2_op3 << 19) |
2548              (0 << 18) |
2549              ($cmp$$cmpcode << 14) |
2550              (1 << 13) |                    // select register move
2551              ($pcc$$constant << 11) |       // cc1-cc0 bits for 'icc' or 'xcc'
2552              ($primary << 5) |              // select single, double or quad
2553              ($src$$reg << 0);
2554     cbuf.insts()->emit_int32(op);
2555   %}
2556 
2557   enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2558     int op = (Assembler::arith_op << 30) |
2559              ($dst$$reg << 25) |
2560              (Assembler::fpop2_op3 << 19) |
2561              (0 << 18) |
2562              ($cmp$$cmpcode << 14) |
2563              ($fcc$$reg << 11) |            // cc2-cc0 bits for 'fccX'
2564              ($primary << 5) |              // select single, double or quad
2565              ($src$$reg << 0);
2566     cbuf.insts()->emit_int32(op);
2567   %}
2568 
2569   // Used by the MIN/MAX encodings.  Same as a CMOV, but
2570   // the condition comes from opcode-field instead of an argument.
2571   enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2572     int op = (Assembler::arith_op << 30) |
2573              ($dst$$reg << 25) |
2574              (Assembler::movcc_op3 << 19) |
2575              (1 << 18) |                    // cc2 bit for 'icc'
2576              ($primary << 14) |
2577              (0 << 13) |                    // select register move
2578              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2579              ($src$$reg << 0);
2580     cbuf.insts()->emit_int32(op);
2581   %}
2582 
2583   enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2584     int op = (Assembler::arith_op << 30) |
2585              ($dst$$reg << 25) |
2586              (Assembler::movcc_op3 << 19) |
2587              (6 << 16) |                    // cc2 bit for 'xcc'
2588              ($primary << 14) |
2589              (0 << 13) |                    // select register move
2590              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2591              ($src$$reg << 0);
2592     cbuf.insts()->emit_int32(op);
2593   %}
2594 
2595   enc_class Set13( immI13 src, iRegI rd ) %{
2596     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2597   %}
2598 
2599   enc_class SetHi22( immI src, iRegI rd ) %{
2600     emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2601   %}
2602 
2603   enc_class Set32( immI src, iRegI rd ) %{
2604     MacroAssembler _masm(&cbuf);
2605     __ set($src$$constant, reg_to_register_object($rd$$reg));
2606   %}
2607 
2608   enc_class call_epilog %{
2609     if( VerifyStackAtCalls ) {
2610       MacroAssembler _masm(&cbuf);
2611       int framesize = ra_->C->frame_size_in_bytes();
2612       Register temp_reg = G3;
2613       __ add(SP, framesize, temp_reg);
2614       __ cmp(temp_reg, FP);
2615       __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2616     }
2617   %}
2618 
2619   // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2620   // to G1 so the register allocator will not have to deal with the misaligned register
2621   // pair.
2622   enc_class adjust_long_from_native_call %{
2623 #ifndef _LP64
2624     if (returns_long()) {
2625       //    sllx  O0,32,O0
2626       emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2627       //    srl   O1,0,O1
2628       emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2629       //    or    O0,O1,G1
2630       emit3       ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2631     }
2632 #endif
2633   %}
2634 
2635   enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime
2636     // CALL directly to the runtime
2637     // The user of this is responsible for ensuring that R_L7 is empty (killed).
2638     emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2639   %}
2640 
2641   enc_class preserve_SP %{
2642     MacroAssembler _masm(&cbuf);
2643     __ mov(SP, L7_mh_SP_save);
2644   %}
2645 
2646   enc_class restore_SP %{
2647     MacroAssembler _masm(&cbuf);
2648     __ mov(L7_mh_SP_save, SP);
2649   %}
2650 
2651   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
2652     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
2653     // who we intended to call.
2654     if (!_method) {
2655       emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2656     } else {
2657       int method_index = resolved_method_index(cbuf);
2658       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2659                                                   : static_call_Relocation::spec(method_index);
2660       emit_call_reloc(cbuf, $meth$$method, rspec);
2661 
2662       // Emit stub for static call.
2663       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2664       // Stub does not fit into scratch buffer if TraceJumps is enabled
2665       if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2666         ciEnv::current()->record_failure("CodeCache is full");
2667         return;
2668       }
2669     }
2670   %}
2671 
2672   enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
2673     MacroAssembler _masm(&cbuf);
2674     __ set_inst_mark();
2675     int vtable_index = this->_vtable_index;
2676     // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2677     if (vtable_index < 0) {
2678       // must be invalid_vtable_index, not nonvirtual_vtable_index
2679       assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2680       Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2681       assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2682       assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2683       __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2684     } else {
2685       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2686       // Just go thru the vtable
2687       // get receiver klass (receiver already checked for non-null)
2688       // If we end up going thru a c2i adapter interpreter expects method in G5
2689       int off = __ offset();
2690       __ load_klass(O0, G3_scratch);
2691       int klass_load_size;
2692       if (UseCompressedClassPointers) {
2693         assert(Universe::heap() != NULL, "java heap should be initialized");
2694         klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2695       } else {
2696         klass_load_size = 1*BytesPerInstWord;
2697       }
2698       int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2699       int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2700       if (Assembler::is_simm13(v_off)) {
2701         __ ld_ptr(G3, v_off, G5_method);
2702       } else {
2703         // Generate 2 instructions
2704         __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2705         __ or3(G5_method, v_off & 0x3ff, G5_method);
2706         // ld_ptr, set_hi, set
2707         assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2708                "Unexpected instruction size(s)");
2709         __ ld_ptr(G3, G5_method, G5_method);
2710       }
2711       // NOTE: for vtable dispatches, the vtable entry will never be null.
2712       // However it may very well end up in handle_wrong_method if the
2713       // method is abstract for the particular class.
2714       __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2715       // jump to target (either compiled code or c2iadapter)
2716       __ jmpl(G3_scratch, G0, O7);
2717       __ delayed()->nop();
2718     }
2719   %}
2720 
2721   enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
2722     MacroAssembler _masm(&cbuf);
2723 
2724     Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2725     Register temp_reg = G3;   // caller must kill G3!  We cannot reuse G5_ic_reg here because
2726                               // we might be calling a C2I adapter which needs it.
2727 
2728     assert(temp_reg != G5_ic_reg, "conflicting registers");
2729     // Load nmethod
2730     __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2731 
2732     // CALL to compiled java, indirect the contents of G3
2733     __ set_inst_mark();
2734     __ callr(temp_reg, G0);
2735     __ delayed()->nop();
2736   %}
2737 
2738 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2739     MacroAssembler _masm(&cbuf);
2740     Register Rdividend = reg_to_register_object($src1$$reg);
2741     Register Rdivisor = reg_to_register_object($src2$$reg);
2742     Register Rresult = reg_to_register_object($dst$$reg);
2743 
2744     __ sra(Rdivisor, 0, Rdivisor);
2745     __ sra(Rdividend, 0, Rdividend);
2746     __ sdivx(Rdividend, Rdivisor, Rresult);
2747 %}
2748 
2749 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2750     MacroAssembler _masm(&cbuf);
2751 
2752     Register Rdividend = reg_to_register_object($src1$$reg);
2753     int divisor = $imm$$constant;
2754     Register Rresult = reg_to_register_object($dst$$reg);
2755 
2756     __ sra(Rdividend, 0, Rdividend);
2757     __ sdivx(Rdividend, divisor, Rresult);
2758 %}
2759 
2760 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2761     MacroAssembler _masm(&cbuf);
2762     Register Rsrc1 = reg_to_register_object($src1$$reg);
2763     Register Rsrc2 = reg_to_register_object($src2$$reg);
2764     Register Rdst  = reg_to_register_object($dst$$reg);
2765 
2766     __ sra( Rsrc1, 0, Rsrc1 );
2767     __ sra( Rsrc2, 0, Rsrc2 );
2768     __ mulx( Rsrc1, Rsrc2, Rdst );
2769     __ srlx( Rdst, 32, Rdst );
2770 %}
2771 
2772 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2773     MacroAssembler _masm(&cbuf);
2774     Register Rdividend = reg_to_register_object($src1$$reg);
2775     Register Rdivisor = reg_to_register_object($src2$$reg);
2776     Register Rresult = reg_to_register_object($dst$$reg);
2777     Register Rscratch = reg_to_register_object($scratch$$reg);
2778 
2779     assert(Rdividend != Rscratch, "");
2780     assert(Rdivisor  != Rscratch, "");
2781 
2782     __ sra(Rdividend, 0, Rdividend);
2783     __ sra(Rdivisor, 0, Rdivisor);
2784     __ sdivx(Rdividend, Rdivisor, Rscratch);
2785     __ mulx(Rscratch, Rdivisor, Rscratch);
2786     __ sub(Rdividend, Rscratch, Rresult);
2787 %}
2788 
2789 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2790     MacroAssembler _masm(&cbuf);
2791 
2792     Register Rdividend = reg_to_register_object($src1$$reg);
2793     int divisor = $imm$$constant;
2794     Register Rresult = reg_to_register_object($dst$$reg);
2795     Register Rscratch = reg_to_register_object($scratch$$reg);
2796 
2797     assert(Rdividend != Rscratch, "");
2798 
2799     __ sra(Rdividend, 0, Rdividend);
2800     __ sdivx(Rdividend, divisor, Rscratch);
2801     __ mulx(Rscratch, divisor, Rscratch);
2802     __ sub(Rdividend, Rscratch, Rresult);
2803 %}
2804 
2805 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2806     MacroAssembler _masm(&cbuf);
2807 
2808     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2809     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2810 
2811     __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2812 %}
2813 
2814 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2815     MacroAssembler _masm(&cbuf);
2816 
2817     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2818     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2819 
2820     __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2821 %}
2822 
2823 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2824     MacroAssembler _masm(&cbuf);
2825 
2826     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2827     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2828 
2829     __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2830 %}
2831 
2832 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2833     MacroAssembler _masm(&cbuf);
2834 
2835     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2836     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2837 
2838     __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2839 %}
2840 
2841 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2842     MacroAssembler _masm(&cbuf);
2843 
2844     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2845     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2846 
2847     __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2848 %}
2849 
2850 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2851     MacroAssembler _masm(&cbuf);
2852 
2853     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2854     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2855 
2856     __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2857 %}
2858 
2859 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2860     MacroAssembler _masm(&cbuf);
2861 
2862     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2863     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2864 
2865     __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2866 %}
2867 
2868 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2869     MacroAssembler _masm(&cbuf);
2870 
2871     Register Roop  = reg_to_register_object($oop$$reg);
2872     Register Rbox  = reg_to_register_object($box$$reg);
2873     Register Rscratch = reg_to_register_object($scratch$$reg);
2874     Register Rmark =    reg_to_register_object($scratch2$$reg);
2875 
2876     assert(Roop  != Rscratch, "");
2877     assert(Roop  != Rmark, "");
2878     assert(Rbox  != Rscratch, "");
2879     assert(Rbox  != Rmark, "");
2880 
2881     __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2882 %}
2883 
2884 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2885     MacroAssembler _masm(&cbuf);
2886 
2887     Register Roop  = reg_to_register_object($oop$$reg);
2888     Register Rbox  = reg_to_register_object($box$$reg);
2889     Register Rscratch = reg_to_register_object($scratch$$reg);
2890     Register Rmark =    reg_to_register_object($scratch2$$reg);
2891 
2892     assert(Roop  != Rscratch, "");
2893     assert(Roop  != Rmark, "");
2894     assert(Rbox  != Rscratch, "");
2895     assert(Rbox  != Rmark, "");
2896 
2897     __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2898   %}
2899 
2900   enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2901     MacroAssembler _masm(&cbuf);
2902     Register Rmem = reg_to_register_object($mem$$reg);
2903     Register Rold = reg_to_register_object($old$$reg);
2904     Register Rnew = reg_to_register_object($new$$reg);
2905 
2906     __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2907     __ cmp( Rold, Rnew );
2908   %}
2909 
2910   enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2911     Register Rmem = reg_to_register_object($mem$$reg);
2912     Register Rold = reg_to_register_object($old$$reg);
2913     Register Rnew = reg_to_register_object($new$$reg);
2914 
2915     MacroAssembler _masm(&cbuf);
2916     __ mov(Rnew, O7);
2917     __ casx(Rmem, Rold, O7);
2918     __ cmp( Rold, O7 );
2919   %}
2920 
2921   // raw int cas, used for compareAndSwap
2922   enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2923     Register Rmem = reg_to_register_object($mem$$reg);
2924     Register Rold = reg_to_register_object($old$$reg);
2925     Register Rnew = reg_to_register_object($new$$reg);
2926 
2927     MacroAssembler _masm(&cbuf);
2928     __ mov(Rnew, O7);
2929     __ cas(Rmem, Rold, O7);
2930     __ cmp( Rold, O7 );
2931   %}
2932 
2933   enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2934     Register Rres = reg_to_register_object($res$$reg);
2935 
2936     MacroAssembler _masm(&cbuf);
2937     __ mov(1, Rres);
2938     __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2939   %}
2940 
2941   enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2942     Register Rres = reg_to_register_object($res$$reg);
2943 
2944     MacroAssembler _masm(&cbuf);
2945     __ mov(1, Rres);
2946     __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2947   %}
2948 
2949   enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2950     MacroAssembler _masm(&cbuf);
2951     Register Rdst = reg_to_register_object($dst$$reg);
2952     FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2953                                      : reg_to_DoubleFloatRegister_object($src1$$reg);
2954     FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2955                                      : reg_to_DoubleFloatRegister_object($src2$$reg);
2956 
2957     // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2958     __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2959   %}
2960 
2961   enc_class enc_rethrow() %{
2962     cbuf.set_insts_mark();
2963     Register temp_reg = G3;
2964     AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2965     assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2966     MacroAssembler _masm(&cbuf);
2967 #ifdef ASSERT
2968     __ save_frame(0);
2969     AddressLiteral last_rethrow_addrlit(&last_rethrow);
2970     __ sethi(last_rethrow_addrlit, L1);
2971     Address addr(L1, last_rethrow_addrlit.low10());
2972     __ rdpc(L2);
2973     __ inc(L2, 3 * BytesPerInstWord);  // skip this & 2 more insns to point at jump_to
2974     __ st_ptr(L2, addr);
2975     __ restore();
2976 #endif
2977     __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2978     __ delayed()->nop();
2979   %}
2980 
2981   enc_class emit_mem_nop() %{
2982     // Generates the instruction LDUXA [o6,g0],#0x82,g0
2983     cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2984   %}
2985 
2986   enc_class emit_fadd_nop() %{
2987     // Generates the instruction FMOVS f31,f31
2988     cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2989   %}
2990 
2991   enc_class emit_br_nop() %{
2992     // Generates the instruction BPN,PN .
2993     cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2994   %}
2995 
2996   enc_class enc_membar_acquire %{
2997     MacroAssembler _masm(&cbuf);
2998     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2999   %}
3000 
3001   enc_class enc_membar_release %{
3002     MacroAssembler _masm(&cbuf);
3003     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3004   %}
3005 
3006   enc_class enc_membar_volatile %{
3007     MacroAssembler _masm(&cbuf);
3008     __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3009   %}
3010 
3011 %}
3012 
3013 //----------FRAME--------------------------------------------------------------
3014 // Definition of frame structure and management information.
3015 //
3016 //  S T A C K   L A Y O U T    Allocators stack-slot number
3017 //                             |   (to get allocators register number
3018 //  G  Owned by    |        |  v    add VMRegImpl::stack0)
3019 //  r   CALLER     |        |
3020 //  o     |        +--------+      pad to even-align allocators stack-slot
3021 //  w     V        |  pad0  |        numbers; owned by CALLER
3022 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
3023 //  h     ^        |   in   |  5
3024 //        |        |  args  |  4   Holes in incoming args owned by SELF
3025 //  |     |        |        |  3
3026 //  |     |        +--------+
3027 //  V     |        | old out|      Empty on Intel, window on Sparc
3028 //        |    old |preserve|      Must be even aligned.
3029 //        |     SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3030 //        |        |   in   |  3   area for Intel ret address
3031 //     Owned by    |preserve|      Empty on Sparc.
3032 //       SELF      +--------+
3033 //        |        |  pad2  |  2   pad to align old SP
3034 //        |        +--------+  1
3035 //        |        | locks  |  0
3036 //        |        +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3037 //        |        |  pad1  | 11   pad to align new SP
3038 //        |        +--------+
3039 //        |        |        | 10
3040 //        |        | spills |  9   spills
3041 //        V        |        |  8   (pad0 slot for callee)
3042 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
3043 //        ^        |  out   |  7
3044 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
3045 //     Owned by    +--------+
3046 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
3047 //        |    new |preserve|      Must be even-aligned.
3048 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
3049 //        |        |        |
3050 //
3051 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
3052 //         known from SELF's arguments and the Java calling convention.
3053 //         Region 6-7 is determined per call site.
3054 // Note 2: If the calling convention leaves holes in the incoming argument
3055 //         area, those holes are owned by SELF.  Holes in the outgoing area
3056 //         are owned by the CALLEE.  Holes should not be nessecary in the
3057 //         incoming area, as the Java calling convention is completely under
3058 //         the control of the AD file.  Doubles can be sorted and packed to
3059 //         avoid holes.  Holes in the outgoing arguments may be necessary for
3060 //         varargs C calling conventions.
3061 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
3062 //         even aligned with pad0 as needed.
3063 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
3064 //         region 6-11 is even aligned; it may be padded out more so that
3065 //         the region from SP to FP meets the minimum stack alignment.
3066 
3067 frame %{
3068   // What direction does stack grow in (assumed to be same for native & Java)
3069   stack_direction(TOWARDS_LOW);
3070 
3071   // These two registers define part of the calling convention
3072   // between compiled code and the interpreter.
3073   inline_cache_reg(R_G5);                // Inline Cache Register or Method* for I2C
3074   interpreter_method_oop_reg(R_G5);      // Method Oop Register when calling interpreter
3075 
3076   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3077   cisc_spilling_operand_name(indOffset);
3078 
3079   // Number of stack slots consumed by a Monitor enter
3080 #ifdef _LP64
3081   sync_stack_slots(2);
3082 #else
3083   sync_stack_slots(1);
3084 #endif
3085 
3086   // Compiled code's Frame Pointer
3087   frame_pointer(R_SP);
3088 
3089   // Stack alignment requirement
3090   stack_alignment(StackAlignmentInBytes);
3091   //  LP64: Alignment size in bytes (128-bit -> 16 bytes)
3092   // !LP64: Alignment size in bytes (64-bit  ->  8 bytes)
3093 
3094   // Number of stack slots between incoming argument block and the start of
3095   // a new frame.  The PROLOG must add this many slots to the stack.  The
3096   // EPILOG must remove this many slots.
3097   in_preserve_stack_slots(0);
3098 
3099   // Number of outgoing stack slots killed above the out_preserve_stack_slots
3100   // for calls to C.  Supports the var-args backing area for register parms.
3101   // ADLC doesn't support parsing expressions, so I folded the math by hand.
3102 #ifdef _LP64
3103   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3104   varargs_C_out_slots_killed(12);
3105 #else
3106   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3107   varargs_C_out_slots_killed( 7);
3108 #endif
3109 
3110   // The after-PROLOG location of the return address.  Location of
3111   // return address specifies a type (REG or STACK) and a number
3112   // representing the register number (i.e. - use a register name) or
3113   // stack slot.
3114   return_addr(REG R_I7);          // Ret Addr is in register I7
3115 
3116   // Body of function which returns an OptoRegs array locating
3117   // arguments either in registers or in stack slots for calling
3118   // java
3119   calling_convention %{
3120     (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3121 
3122   %}
3123 
3124   // Body of function which returns an OptoRegs array locating
3125   // arguments either in registers or in stack slots for calling
3126   // C.
3127   c_calling_convention %{
3128     // This is obviously always outgoing
3129     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3130   %}
3131 
3132   // Location of native (C/C++) and interpreter return values.  This is specified to
3133   // be the  same as Java.  In the 32-bit VM, long values are actually returned from
3134   // native calls in O0:O1 and returned to the interpreter in I0:I1.  The copying
3135   // to and from the register pairs is done by the appropriate call and epilog
3136   // opcodes.  This simplifies the register allocator.
3137   c_return_value %{
3138     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3139 #ifdef     _LP64
3140     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3141     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3142     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3143     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3144 #else  // !_LP64
3145     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3146     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3147     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3148     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3149 #endif
3150     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3151                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3152   %}
3153 
3154   // Location of compiled Java return values.  Same as C
3155   return_value %{
3156     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3157 #ifdef     _LP64
3158     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3159     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3160     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3161     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3162 #else  // !_LP64
3163     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3164     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3165     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3166     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3167 #endif
3168     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3169                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3170   %}
3171 
3172 %}
3173 
3174 
3175 //----------ATTRIBUTES---------------------------------------------------------
3176 //----------Operand Attributes-------------------------------------------------
3177 op_attrib op_cost(1);          // Required cost attribute
3178 
3179 //----------Instruction Attributes---------------------------------------------
3180 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3181 ins_attrib ins_size(32);           // Required size attribute (in bits)
3182 
3183 // avoid_back_to_back attribute is an expression that must return
3184 // one of the following values defined in MachNode:
3185 // AVOID_NONE   - instruction can be placed anywhere
3186 // AVOID_BEFORE - instruction cannot be placed after an
3187 //                instruction with MachNode::AVOID_AFTER
3188 // AVOID_AFTER  - the next instruction cannot be the one
3189 //                with MachNode::AVOID_BEFORE
3190 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3191 //                          the same time
3192 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3193 
3194 ins_attrib ins_short_branch(0);    // Required flag: is this instruction a
3195                                    // non-matching short branch variant of some
3196                                                             // long branch?
3197 
3198 //----------OPERANDS-----------------------------------------------------------
3199 // Operand definitions must precede instruction definitions for correct parsing
3200 // in the ADLC because operands constitute user defined types which are used in
3201 // instruction definitions.
3202 
3203 //----------Simple Operands----------------------------------------------------
3204 // Immediate Operands
3205 // Integer Immediate: 32-bit
3206 operand immI() %{
3207   match(ConI);
3208 
3209   op_cost(0);
3210   // formats are generated automatically for constants and base registers
3211   format %{ %}
3212   interface(CONST_INTER);
3213 %}
3214 
3215 // Integer Immediate: 0-bit
3216 operand immI0() %{
3217   predicate(n->get_int() == 0);
3218   match(ConI);
3219   op_cost(0);
3220 
3221   format %{ %}
3222   interface(CONST_INTER);
3223 %}
3224 
3225 // Integer Immediate: 5-bit
3226 operand immI5() %{
3227   predicate(Assembler::is_simm5(n->get_int()));
3228   match(ConI);
3229   op_cost(0);
3230   format %{ %}
3231   interface(CONST_INTER);
3232 %}
3233 
3234 // Integer Immediate: 8-bit
3235 operand immI8() %{
3236   predicate(Assembler::is_simm8(n->get_int()));
3237   match(ConI);
3238   op_cost(0);
3239   format %{ %}
3240   interface(CONST_INTER);
3241 %}
3242 
3243 // Integer Immediate: the value 10
3244 operand immI10() %{
3245   predicate(n->get_int() == 10);
3246   match(ConI);
3247   op_cost(0);
3248 
3249   format %{ %}
3250   interface(CONST_INTER);
3251 %}
3252 
3253 // Integer Immediate: 11-bit
3254 operand immI11() %{
3255   predicate(Assembler::is_simm11(n->get_int()));
3256   match(ConI);
3257   op_cost(0);
3258   format %{ %}
3259   interface(CONST_INTER);
3260 %}
3261 
3262 // Integer Immediate: 13-bit
3263 operand immI13() %{
3264   predicate(Assembler::is_simm13(n->get_int()));
3265   match(ConI);
3266   op_cost(0);
3267 
3268   format %{ %}
3269   interface(CONST_INTER);
3270 %}
3271 
3272 // Integer Immediate: 13-bit minus 7
3273 operand immI13m7() %{
3274   predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3275   match(ConI);
3276   op_cost(0);
3277 
3278   format %{ %}
3279   interface(CONST_INTER);
3280 %}
3281 
3282 // Integer Immediate: 16-bit
3283 operand immI16() %{
3284   predicate(Assembler::is_simm16(n->get_int()));
3285   match(ConI);
3286   op_cost(0);
3287   format %{ %}
3288   interface(CONST_INTER);
3289 %}
3290 
3291 // Integer Immediate: the values 1-31
3292 operand immI_1_31() %{
3293   predicate(n->get_int() >= 1 && n->get_int() <= 31);
3294   match(ConI);
3295   op_cost(0);
3296 
3297   format %{ %}
3298   interface(CONST_INTER);
3299 %}
3300 
3301 // Integer Immediate: the values 32-63
3302 operand immI_32_63() %{
3303   predicate(n->get_int() >= 32 && n->get_int() <= 63);
3304   match(ConI);
3305   op_cost(0);
3306 
3307   format %{ %}
3308   interface(CONST_INTER);
3309 %}
3310 
3311 // Immediates for special shifts (sign extend)
3312 
3313 // Integer Immediate: the value 16
3314 operand immI_16() %{
3315   predicate(n->get_int() == 16);
3316   match(ConI);
3317   op_cost(0);
3318 
3319   format %{ %}
3320   interface(CONST_INTER);
3321 %}
3322 
3323 // Integer Immediate: the value 24
3324 operand immI_24() %{
3325   predicate(n->get_int() == 24);
3326   match(ConI);
3327   op_cost(0);
3328 
3329   format %{ %}
3330   interface(CONST_INTER);
3331 %}
3332 // Integer Immediate: the value 255
3333 operand immI_255() %{
3334   predicate( n->get_int() == 255 );
3335   match(ConI);
3336   op_cost(0);
3337 
3338   format %{ %}
3339   interface(CONST_INTER);
3340 %}
3341 
3342 // Integer Immediate: the value 65535
3343 operand immI_65535() %{
3344   predicate(n->get_int() == 65535);
3345   match(ConI);
3346   op_cost(0);
3347 
3348   format %{ %}
3349   interface(CONST_INTER);
3350 %}
3351 
3352 // Integer Immediate: the values 0-31
3353 operand immU5() %{
3354   predicate(n->get_int() >= 0 && n->get_int() <= 31);
3355   match(ConI);
3356   op_cost(0);
3357 
3358   format %{ %}
3359   interface(CONST_INTER);
3360 %}
3361 
3362 // Integer Immediate: 6-bit
3363 operand immU6() %{
3364   predicate(n->get_int() >= 0 && n->get_int() <= 63);
3365   match(ConI);
3366   op_cost(0);
3367   format %{ %}
3368   interface(CONST_INTER);
3369 %}
3370 
3371 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3372 operand immU12() %{
3373   predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3374   match(ConI);
3375   op_cost(0);
3376 
3377   format %{ %}
3378   interface(CONST_INTER);
3379 %}
3380 
3381 // Integer Immediate non-negative
3382 operand immU31()
3383 %{
3384   predicate(n->get_int() >= 0);
3385   match(ConI);
3386 
3387   op_cost(0);
3388   format %{ %}
3389   interface(CONST_INTER);
3390 %}
3391 
3392 // Long Immediate: the value FF
3393 operand immL_FF() %{
3394   predicate( n->get_long() == 0xFFL );
3395   match(ConL);
3396   op_cost(0);
3397 
3398   format %{ %}
3399   interface(CONST_INTER);
3400 %}
3401 
3402 // Long Immediate: the value FFFF
3403 operand immL_FFFF() %{
3404   predicate( n->get_long() == 0xFFFFL );
3405   match(ConL);
3406   op_cost(0);
3407 
3408   format %{ %}
3409   interface(CONST_INTER);
3410 %}
3411 
3412 // Pointer Immediate: 32 or 64-bit
3413 operand immP() %{
3414   match(ConP);
3415 
3416   op_cost(5);
3417   // formats are generated automatically for constants and base registers
3418   format %{ %}
3419   interface(CONST_INTER);
3420 %}
3421 
3422 #ifdef _LP64
3423 // Pointer Immediate: 64-bit
3424 operand immP_set() %{
3425   predicate(!VM_Version::is_niagara_plus());
3426   match(ConP);
3427 
3428   op_cost(5);
3429   // formats are generated automatically for constants and base registers
3430   format %{ %}
3431   interface(CONST_INTER);
3432 %}
3433 
3434 // Pointer Immediate: 64-bit
3435 // From Niagara2 processors on a load should be better than materializing.
3436 operand immP_load() %{
3437   predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3438   match(ConP);
3439 
3440   op_cost(5);
3441   // formats are generated automatically for constants and base registers
3442   format %{ %}
3443   interface(CONST_INTER);
3444 %}
3445 
3446 // Pointer Immediate: 64-bit
3447 operand immP_no_oop_cheap() %{
3448   predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3449   match(ConP);
3450 
3451   op_cost(5);
3452   // formats are generated automatically for constants and base registers
3453   format %{ %}
3454   interface(CONST_INTER);
3455 %}
3456 #endif
3457 
3458 operand immP13() %{
3459   predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3460   match(ConP);
3461   op_cost(0);
3462 
3463   format %{ %}
3464   interface(CONST_INTER);
3465 %}
3466 
3467 operand immP0() %{
3468   predicate(n->get_ptr() == 0);
3469   match(ConP);
3470   op_cost(0);
3471 
3472   format %{ %}
3473   interface(CONST_INTER);
3474 %}
3475 
3476 operand immP_poll() %{
3477   predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3478   match(ConP);
3479 
3480   // formats are generated automatically for constants and base registers
3481   format %{ %}
3482   interface(CONST_INTER);
3483 %}
3484 
3485 // Pointer Immediate
3486 operand immN()
3487 %{
3488   match(ConN);
3489 
3490   op_cost(10);
3491   format %{ %}
3492   interface(CONST_INTER);
3493 %}
3494 
3495 operand immNKlass()
3496 %{
3497   match(ConNKlass);
3498 
3499   op_cost(10);
3500   format %{ %}
3501   interface(CONST_INTER);
3502 %}
3503 
3504 // NULL Pointer Immediate
3505 operand immN0()
3506 %{
3507   predicate(n->get_narrowcon() == 0);
3508   match(ConN);
3509 
3510   op_cost(0);
3511   format %{ %}
3512   interface(CONST_INTER);
3513 %}
3514 
3515 operand immL() %{
3516   match(ConL);
3517   op_cost(40);
3518   // formats are generated automatically for constants and base registers
3519   format %{ %}
3520   interface(CONST_INTER);
3521 %}
3522 
3523 operand immL0() %{
3524   predicate(n->get_long() == 0L);
3525   match(ConL);
3526   op_cost(0);
3527   // formats are generated automatically for constants and base registers
3528   format %{ %}
3529   interface(CONST_INTER);
3530 %}
3531 
3532 // Integer Immediate: 5-bit
3533 operand immL5() %{
3534   predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3535   match(ConL);
3536   op_cost(0);
3537   format %{ %}
3538   interface(CONST_INTER);
3539 %}
3540 
3541 // Long Immediate: 13-bit
3542 operand immL13() %{
3543   predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3544   match(ConL);
3545   op_cost(0);
3546 
3547   format %{ %}
3548   interface(CONST_INTER);
3549 %}
3550 
3551 // Long Immediate: 13-bit minus 7
3552 operand immL13m7() %{
3553   predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3554   match(ConL);
3555   op_cost(0);
3556 
3557   format %{ %}
3558   interface(CONST_INTER);
3559 %}
3560 
3561 // Long Immediate: low 32-bit mask
3562 operand immL_32bits() %{
3563   predicate(n->get_long() == 0xFFFFFFFFL);
3564   match(ConL);
3565   op_cost(0);
3566 
3567   format %{ %}
3568   interface(CONST_INTER);
3569 %}
3570 
3571 // Long Immediate: cheap (materialize in <= 3 instructions)
3572 operand immL_cheap() %{
3573   predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3574   match(ConL);
3575   op_cost(0);
3576 
3577   format %{ %}
3578   interface(CONST_INTER);
3579 %}
3580 
3581 // Long Immediate: expensive (materialize in > 3 instructions)
3582 operand immL_expensive() %{
3583   predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3584   match(ConL);
3585   op_cost(0);
3586 
3587   format %{ %}
3588   interface(CONST_INTER);
3589 %}
3590 
3591 // Double Immediate
3592 operand immD() %{
3593   match(ConD);
3594 
3595   op_cost(40);
3596   format %{ %}
3597   interface(CONST_INTER);
3598 %}
3599 
3600 // Double Immediate: +0.0d
3601 operand immD0() %{
3602   predicate(jlong_cast(n->getd()) == 0);
3603   match(ConD);
3604 
3605   op_cost(0);
3606   format %{ %}
3607   interface(CONST_INTER);
3608 %}
3609 
3610 // Float Immediate
3611 operand immF() %{
3612   match(ConF);
3613 
3614   op_cost(20);
3615   format %{ %}
3616   interface(CONST_INTER);
3617 %}
3618 
3619 // Float Immediate: +0.0f
3620 operand immF0() %{
3621   predicate(jint_cast(n->getf()) == 0);
3622   match(ConF);
3623 
3624   op_cost(0);
3625   format %{ %}
3626   interface(CONST_INTER);
3627 %}
3628 
3629 // Integer Register Operands
3630 // Integer Register
3631 operand iRegI() %{
3632   constraint(ALLOC_IN_RC(int_reg));
3633   match(RegI);
3634 
3635   match(notemp_iRegI);
3636   match(g1RegI);
3637   match(o0RegI);
3638   match(iRegIsafe);
3639 
3640   format %{ %}
3641   interface(REG_INTER);
3642 %}
3643 
3644 operand notemp_iRegI() %{
3645   constraint(ALLOC_IN_RC(notemp_int_reg));
3646   match(RegI);
3647 
3648   match(o0RegI);
3649 
3650   format %{ %}
3651   interface(REG_INTER);
3652 %}
3653 
3654 operand o0RegI() %{
3655   constraint(ALLOC_IN_RC(o0_regI));
3656   match(iRegI);
3657 
3658   format %{ %}
3659   interface(REG_INTER);
3660 %}
3661 
3662 // Pointer Register
3663 operand iRegP() %{
3664   constraint(ALLOC_IN_RC(ptr_reg));
3665   match(RegP);
3666 
3667   match(lock_ptr_RegP);
3668   match(g1RegP);
3669   match(g2RegP);
3670   match(g3RegP);
3671   match(g4RegP);
3672   match(i0RegP);
3673   match(o0RegP);
3674   match(o1RegP);
3675   match(l7RegP);
3676 
3677   format %{ %}
3678   interface(REG_INTER);
3679 %}
3680 
3681 operand sp_ptr_RegP() %{
3682   constraint(ALLOC_IN_RC(sp_ptr_reg));
3683   match(RegP);
3684   match(iRegP);
3685 
3686   format %{ %}
3687   interface(REG_INTER);
3688 %}
3689 
3690 operand lock_ptr_RegP() %{
3691   constraint(ALLOC_IN_RC(lock_ptr_reg));
3692   match(RegP);
3693   match(i0RegP);
3694   match(o0RegP);
3695   match(o1RegP);
3696   match(l7RegP);
3697 
3698   format %{ %}
3699   interface(REG_INTER);
3700 %}
3701 
3702 operand g1RegP() %{
3703   constraint(ALLOC_IN_RC(g1_regP));
3704   match(iRegP);
3705 
3706   format %{ %}
3707   interface(REG_INTER);
3708 %}
3709 
3710 operand g2RegP() %{
3711   constraint(ALLOC_IN_RC(g2_regP));
3712   match(iRegP);
3713 
3714   format %{ %}
3715   interface(REG_INTER);
3716 %}
3717 
3718 operand g3RegP() %{
3719   constraint(ALLOC_IN_RC(g3_regP));
3720   match(iRegP);
3721 
3722   format %{ %}
3723   interface(REG_INTER);
3724 %}
3725 
3726 operand g1RegI() %{
3727   constraint(ALLOC_IN_RC(g1_regI));
3728   match(iRegI);
3729 
3730   format %{ %}
3731   interface(REG_INTER);
3732 %}
3733 
3734 operand g3RegI() %{
3735   constraint(ALLOC_IN_RC(g3_regI));
3736   match(iRegI);
3737 
3738   format %{ %}
3739   interface(REG_INTER);
3740 %}
3741 
3742 operand g4RegI() %{
3743   constraint(ALLOC_IN_RC(g4_regI));
3744   match(iRegI);
3745 
3746   format %{ %}
3747   interface(REG_INTER);
3748 %}
3749 
3750 operand g4RegP() %{
3751   constraint(ALLOC_IN_RC(g4_regP));
3752   match(iRegP);
3753 
3754   format %{ %}
3755   interface(REG_INTER);
3756 %}
3757 
3758 operand i0RegP() %{
3759   constraint(ALLOC_IN_RC(i0_regP));
3760   match(iRegP);
3761 
3762   format %{ %}
3763   interface(REG_INTER);
3764 %}
3765 
3766 operand o0RegP() %{
3767   constraint(ALLOC_IN_RC(o0_regP));
3768   match(iRegP);
3769 
3770   format %{ %}
3771   interface(REG_INTER);
3772 %}
3773 
3774 operand o1RegP() %{
3775   constraint(ALLOC_IN_RC(o1_regP));
3776   match(iRegP);
3777 
3778   format %{ %}
3779   interface(REG_INTER);
3780 %}
3781 
3782 operand o2RegP() %{
3783   constraint(ALLOC_IN_RC(o2_regP));
3784   match(iRegP);
3785 
3786   format %{ %}
3787   interface(REG_INTER);
3788 %}
3789 
3790 operand o7RegP() %{
3791   constraint(ALLOC_IN_RC(o7_regP));
3792   match(iRegP);
3793 
3794   format %{ %}
3795   interface(REG_INTER);
3796 %}
3797 
3798 operand l7RegP() %{
3799   constraint(ALLOC_IN_RC(l7_regP));
3800   match(iRegP);
3801 
3802   format %{ %}
3803   interface(REG_INTER);
3804 %}
3805 
3806 operand o7RegI() %{
3807   constraint(ALLOC_IN_RC(o7_regI));
3808   match(iRegI);
3809 
3810   format %{ %}
3811   interface(REG_INTER);
3812 %}
3813 
3814 operand iRegN() %{
3815   constraint(ALLOC_IN_RC(int_reg));
3816   match(RegN);
3817 
3818   format %{ %}
3819   interface(REG_INTER);
3820 %}
3821 
3822 // Long Register
3823 operand iRegL() %{
3824   constraint(ALLOC_IN_RC(long_reg));
3825   match(RegL);
3826 
3827   format %{ %}
3828   interface(REG_INTER);
3829 %}
3830 
3831 operand o2RegL() %{
3832   constraint(ALLOC_IN_RC(o2_regL));
3833   match(iRegL);
3834 
3835   format %{ %}
3836   interface(REG_INTER);
3837 %}
3838 
3839 operand o7RegL() %{
3840   constraint(ALLOC_IN_RC(o7_regL));
3841   match(iRegL);
3842 
3843   format %{ %}
3844   interface(REG_INTER);
3845 %}
3846 
3847 operand g1RegL() %{
3848   constraint(ALLOC_IN_RC(g1_regL));
3849   match(iRegL);
3850 
3851   format %{ %}
3852   interface(REG_INTER);
3853 %}
3854 
3855 operand g3RegL() %{
3856   constraint(ALLOC_IN_RC(g3_regL));
3857   match(iRegL);
3858 
3859   format %{ %}
3860   interface(REG_INTER);
3861 %}
3862 
3863 // Int Register safe
3864 // This is 64bit safe
3865 operand iRegIsafe() %{
3866   constraint(ALLOC_IN_RC(long_reg));
3867 
3868   match(iRegI);
3869 
3870   format %{ %}
3871   interface(REG_INTER);
3872 %}
3873 
3874 // Condition Code Flag Register
3875 operand flagsReg() %{
3876   constraint(ALLOC_IN_RC(int_flags));
3877   match(RegFlags);
3878 
3879   format %{ "ccr" %} // both ICC and XCC
3880   interface(REG_INTER);
3881 %}
3882 
3883 // Condition Code Register, unsigned comparisons.
3884 operand flagsRegU() %{
3885   constraint(ALLOC_IN_RC(int_flags));
3886   match(RegFlags);
3887 
3888   format %{ "icc_U" %}
3889   interface(REG_INTER);
3890 %}
3891 
3892 // Condition Code Register, pointer comparisons.
3893 operand flagsRegP() %{
3894   constraint(ALLOC_IN_RC(int_flags));
3895   match(RegFlags);
3896 
3897 #ifdef _LP64
3898   format %{ "xcc_P" %}
3899 #else
3900   format %{ "icc_P" %}
3901 #endif
3902   interface(REG_INTER);
3903 %}
3904 
3905 // Condition Code Register, long comparisons.
3906 operand flagsRegL() %{
3907   constraint(ALLOC_IN_RC(int_flags));
3908   match(RegFlags);
3909 
3910   format %{ "xcc_L" %}
3911   interface(REG_INTER);
3912 %}
3913 
3914 // Condition Code Register, floating comparisons, unordered same as "less".
3915 operand flagsRegF() %{
3916   constraint(ALLOC_IN_RC(float_flags));
3917   match(RegFlags);
3918   match(flagsRegF0);
3919 
3920   format %{ %}
3921   interface(REG_INTER);
3922 %}
3923 
3924 operand flagsRegF0() %{
3925   constraint(ALLOC_IN_RC(float_flag0));
3926   match(RegFlags);
3927 
3928   format %{ %}
3929   interface(REG_INTER);
3930 %}
3931 
3932 
3933 // Condition Code Flag Register used by long compare
3934 operand flagsReg_long_LTGE() %{
3935   constraint(ALLOC_IN_RC(int_flags));
3936   match(RegFlags);
3937   format %{ "icc_LTGE" %}
3938   interface(REG_INTER);
3939 %}
3940 operand flagsReg_long_EQNE() %{
3941   constraint(ALLOC_IN_RC(int_flags));
3942   match(RegFlags);
3943   format %{ "icc_EQNE" %}
3944   interface(REG_INTER);
3945 %}
3946 operand flagsReg_long_LEGT() %{
3947   constraint(ALLOC_IN_RC(int_flags));
3948   match(RegFlags);
3949   format %{ "icc_LEGT" %}
3950   interface(REG_INTER);
3951 %}
3952 
3953 
3954 operand regD() %{
3955   constraint(ALLOC_IN_RC(dflt_reg));
3956   match(RegD);
3957 
3958   match(regD_low);
3959 
3960   format %{ %}
3961   interface(REG_INTER);
3962 %}
3963 
3964 operand regF() %{
3965   constraint(ALLOC_IN_RC(sflt_reg));
3966   match(RegF);
3967 
3968   format %{ %}
3969   interface(REG_INTER);
3970 %}
3971 
3972 operand regD_low() %{
3973   constraint(ALLOC_IN_RC(dflt_low_reg));
3974   match(regD);
3975 
3976   format %{ %}
3977   interface(REG_INTER);
3978 %}
3979 
3980 // Special Registers
3981 
3982 // Method Register
3983 operand inline_cache_regP(iRegP reg) %{
3984   constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3985   match(reg);
3986   format %{ %}
3987   interface(REG_INTER);
3988 %}
3989 
3990 operand interpreter_method_oop_regP(iRegP reg) %{
3991   constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3992   match(reg);
3993   format %{ %}
3994   interface(REG_INTER);
3995 %}
3996 
3997 
3998 //----------Complex Operands---------------------------------------------------
3999 // Indirect Memory Reference
4000 operand indirect(sp_ptr_RegP reg) %{
4001   constraint(ALLOC_IN_RC(sp_ptr_reg));
4002   match(reg);
4003 
4004   op_cost(100);
4005   format %{ "[$reg]" %}
4006   interface(MEMORY_INTER) %{
4007     base($reg);
4008     index(0x0);
4009     scale(0x0);
4010     disp(0x0);
4011   %}
4012 %}
4013 
4014 // Indirect with simm13 Offset
4015 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4016   constraint(ALLOC_IN_RC(sp_ptr_reg));
4017   match(AddP reg offset);
4018 
4019   op_cost(100);
4020   format %{ "[$reg + $offset]" %}
4021   interface(MEMORY_INTER) %{
4022     base($reg);
4023     index(0x0);
4024     scale(0x0);
4025     disp($offset);
4026   %}
4027 %}
4028 
4029 // Indirect with simm13 Offset minus 7
4030 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4031   constraint(ALLOC_IN_RC(sp_ptr_reg));
4032   match(AddP reg offset);
4033 
4034   op_cost(100);
4035   format %{ "[$reg + $offset]" %}
4036   interface(MEMORY_INTER) %{
4037     base($reg);
4038     index(0x0);
4039     scale(0x0);
4040     disp($offset);
4041   %}
4042 %}
4043 
4044 // Note:  Intel has a swapped version also, like this:
4045 //operand indOffsetX(iRegI reg, immP offset) %{
4046 //  constraint(ALLOC_IN_RC(int_reg));
4047 //  match(AddP offset reg);
4048 //
4049 //  op_cost(100);
4050 //  format %{ "[$reg + $offset]" %}
4051 //  interface(MEMORY_INTER) %{
4052 //    base($reg);
4053 //    index(0x0);
4054 //    scale(0x0);
4055 //    disp($offset);
4056 //  %}
4057 //%}
4058 //// However, it doesn't make sense for SPARC, since
4059 // we have no particularly good way to embed oops in
4060 // single instructions.
4061 
4062 // Indirect with Register Index
4063 operand indIndex(iRegP addr, iRegX index) %{
4064   constraint(ALLOC_IN_RC(ptr_reg));
4065   match(AddP addr index);
4066 
4067   op_cost(100);
4068   format %{ "[$addr + $index]" %}
4069   interface(MEMORY_INTER) %{
4070     base($addr);
4071     index($index);
4072     scale(0x0);
4073     disp(0x0);
4074   %}
4075 %}
4076 
4077 //----------Special Memory Operands--------------------------------------------
4078 // Stack Slot Operand - This operand is used for loading and storing temporary
4079 //                      values on the stack where a match requires a value to
4080 //                      flow through memory.
4081 operand stackSlotI(sRegI reg) %{
4082   constraint(ALLOC_IN_RC(stack_slots));
4083   op_cost(100);
4084   //match(RegI);
4085   format %{ "[$reg]" %}
4086   interface(MEMORY_INTER) %{
4087     base(0xE);   // R_SP
4088     index(0x0);
4089     scale(0x0);
4090     disp($reg);  // Stack Offset
4091   %}
4092 %}
4093 
4094 operand stackSlotP(sRegP reg) %{
4095   constraint(ALLOC_IN_RC(stack_slots));
4096   op_cost(100);
4097   //match(RegP);
4098   format %{ "[$reg]" %}
4099   interface(MEMORY_INTER) %{
4100     base(0xE);   // R_SP
4101     index(0x0);
4102     scale(0x0);
4103     disp($reg);  // Stack Offset
4104   %}
4105 %}
4106 
4107 operand stackSlotF(sRegF reg) %{
4108   constraint(ALLOC_IN_RC(stack_slots));
4109   op_cost(100);
4110   //match(RegF);
4111   format %{ "[$reg]" %}
4112   interface(MEMORY_INTER) %{
4113     base(0xE);   // R_SP
4114     index(0x0);
4115     scale(0x0);
4116     disp($reg);  // Stack Offset
4117   %}
4118 %}
4119 operand stackSlotD(sRegD reg) %{
4120   constraint(ALLOC_IN_RC(stack_slots));
4121   op_cost(100);
4122   //match(RegD);
4123   format %{ "[$reg]" %}
4124   interface(MEMORY_INTER) %{
4125     base(0xE);   // R_SP
4126     index(0x0);
4127     scale(0x0);
4128     disp($reg);  // Stack Offset
4129   %}
4130 %}
4131 operand stackSlotL(sRegL reg) %{
4132   constraint(ALLOC_IN_RC(stack_slots));
4133   op_cost(100);
4134   //match(RegL);
4135   format %{ "[$reg]" %}
4136   interface(MEMORY_INTER) %{
4137     base(0xE);   // R_SP
4138     index(0x0);
4139     scale(0x0);
4140     disp($reg);  // Stack Offset
4141   %}
4142 %}
4143 
4144 // Operands for expressing Control Flow
4145 // NOTE:  Label is a predefined operand which should not be redefined in
4146 //        the AD file.  It is generically handled within the ADLC.
4147 
4148 //----------Conditional Branch Operands----------------------------------------
4149 // Comparison Op  - This is the operation of the comparison, and is limited to
4150 //                  the following set of codes:
4151 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4152 //
4153 // Other attributes of the comparison, such as unsignedness, are specified
4154 // by the comparison instruction that sets a condition code flags register.
4155 // That result is represented by a flags operand whose subtype is appropriate
4156 // to the unsignedness (etc.) of the comparison.
4157 //
4158 // Later, the instruction which matches both the Comparison Op (a Bool) and
4159 // the flags (produced by the Cmp) specifies the coding of the comparison op
4160 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4161 
4162 operand cmpOp() %{
4163   match(Bool);
4164 
4165   format %{ "" %}
4166   interface(COND_INTER) %{
4167     equal(0x1);
4168     not_equal(0x9);
4169     less(0x3);
4170     greater_equal(0xB);
4171     less_equal(0x2);
4172     greater(0xA);
4173     overflow(0x7);
4174     no_overflow(0xF);
4175   %}
4176 %}
4177 
4178 // Comparison Op, unsigned
4179 operand cmpOpU() %{
4180   match(Bool);
4181   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4182             n->as_Bool()->_test._test != BoolTest::no_overflow);
4183 
4184   format %{ "u" %}
4185   interface(COND_INTER) %{
4186     equal(0x1);
4187     not_equal(0x9);
4188     less(0x5);
4189     greater_equal(0xD);
4190     less_equal(0x4);
4191     greater(0xC);
4192     overflow(0x7);
4193     no_overflow(0xF);
4194   %}
4195 %}
4196 
4197 // Comparison Op, pointer (same as unsigned)
4198 operand cmpOpP() %{
4199   match(Bool);
4200   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4201             n->as_Bool()->_test._test != BoolTest::no_overflow);
4202 
4203   format %{ "p" %}
4204   interface(COND_INTER) %{
4205     equal(0x1);
4206     not_equal(0x9);
4207     less(0x5);
4208     greater_equal(0xD);
4209     less_equal(0x4);
4210     greater(0xC);
4211     overflow(0x7);
4212     no_overflow(0xF);
4213   %}
4214 %}
4215 
4216 // Comparison Op, branch-register encoding
4217 operand cmpOp_reg() %{
4218   match(Bool);
4219   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4220             n->as_Bool()->_test._test != BoolTest::no_overflow);
4221 
4222   format %{ "" %}
4223   interface(COND_INTER) %{
4224     equal        (0x1);
4225     not_equal    (0x5);
4226     less         (0x3);
4227     greater_equal(0x7);
4228     less_equal   (0x2);
4229     greater      (0x6);
4230     overflow(0x7); // not supported
4231     no_overflow(0xF); // not supported
4232   %}
4233 %}
4234 
4235 // Comparison Code, floating, unordered same as less
4236 operand cmpOpF() %{
4237   match(Bool);
4238   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4239             n->as_Bool()->_test._test != BoolTest::no_overflow);
4240 
4241   format %{ "fl" %}
4242   interface(COND_INTER) %{
4243     equal(0x9);
4244     not_equal(0x1);
4245     less(0x3);
4246     greater_equal(0xB);
4247     less_equal(0xE);
4248     greater(0x6);
4249 
4250     overflow(0x7); // not supported
4251     no_overflow(0xF); // not supported
4252   %}
4253 %}
4254 
4255 // Used by long compare
4256 operand cmpOp_commute() %{
4257   match(Bool);
4258   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4259             n->as_Bool()->_test._test != BoolTest::no_overflow);
4260 
4261   format %{ "" %}
4262   interface(COND_INTER) %{
4263     equal(0x1);
4264     not_equal(0x9);
4265     less(0xA);
4266     greater_equal(0x2);
4267     less_equal(0xB);
4268     greater(0x3);
4269     overflow(0x7);
4270     no_overflow(0xF);
4271   %}
4272 %}
4273 
4274 //----------OPERAND CLASSES----------------------------------------------------
4275 // Operand Classes are groups of operands that are used to simplify
4276 // instruction definitions by not requiring the AD writer to specify separate
4277 // instructions for every form of operand when the instruction accepts
4278 // multiple operand types with the same basic encoding and format.  The classic
4279 // case of this is memory operands.
4280 opclass memory( indirect, indOffset13, indIndex );
4281 opclass indIndexMemory( indIndex );
4282 
4283 //----------PIPELINE-----------------------------------------------------------
4284 pipeline %{
4285 
4286 //----------ATTRIBUTES---------------------------------------------------------
4287 attributes %{
4288   fixed_size_instructions;           // Fixed size instructions
4289   branch_has_delay_slot;             // Branch has delay slot following
4290   max_instructions_per_bundle = 4;   // Up to 4 instructions per bundle
4291   instruction_unit_size = 4;         // An instruction is 4 bytes long
4292   instruction_fetch_unit_size = 16;  // The processor fetches one line
4293   instruction_fetch_units = 1;       // of 16 bytes
4294 
4295   // List of nop instructions
4296   nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4297 %}
4298 
4299 //----------RESOURCES----------------------------------------------------------
4300 // Resources are the functional units available to the machine
4301 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4302 
4303 //----------PIPELINE DESCRIPTION-----------------------------------------------
4304 // Pipeline Description specifies the stages in the machine's pipeline
4305 
4306 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4307 
4308 //----------PIPELINE CLASSES---------------------------------------------------
4309 // Pipeline Classes describe the stages in which input and output are
4310 // referenced by the hardware pipeline.
4311 
4312 // Integer ALU reg-reg operation
4313 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4314     single_instruction;
4315     dst   : E(write);
4316     src1  : R(read);
4317     src2  : R(read);
4318     IALU  : R;
4319 %}
4320 
4321 // Integer ALU reg-reg long operation
4322 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4323     instruction_count(2);
4324     dst   : E(write);
4325     src1  : R(read);
4326     src2  : R(read);
4327     IALU  : R;
4328     IALU  : R;
4329 %}
4330 
4331 // Integer ALU reg-reg long dependent operation
4332 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4333     instruction_count(1); multiple_bundles;
4334     dst   : E(write);
4335     src1  : R(read);
4336     src2  : R(read);
4337     cr    : E(write);
4338     IALU  : R(2);
4339 %}
4340 
4341 // Integer ALU reg-imm operaion
4342 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4343     single_instruction;
4344     dst   : E(write);
4345     src1  : R(read);
4346     IALU  : R;
4347 %}
4348 
4349 // Integer ALU reg-reg operation with condition code
4350 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4351     single_instruction;
4352     dst   : E(write);
4353     cr    : E(write);
4354     src1  : R(read);
4355     src2  : R(read);
4356     IALU  : R;
4357 %}
4358 
4359 // Integer ALU reg-imm operation with condition code
4360 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4361     single_instruction;
4362     dst   : E(write);
4363     cr    : E(write);
4364     src1  : R(read);
4365     IALU  : R;
4366 %}
4367 
4368 // Integer ALU zero-reg operation
4369 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4370     single_instruction;
4371     dst   : E(write);
4372     src2  : R(read);
4373     IALU  : R;
4374 %}
4375 
4376 // Integer ALU zero-reg operation with condition code only
4377 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4378     single_instruction;
4379     cr    : E(write);
4380     src   : R(read);
4381     IALU  : R;
4382 %}
4383 
4384 // Integer ALU reg-reg operation with condition code only
4385 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4386     single_instruction;
4387     cr    : E(write);
4388     src1  : R(read);
4389     src2  : R(read);
4390     IALU  : R;
4391 %}
4392 
4393 // Integer ALU reg-imm operation with condition code only
4394 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4395     single_instruction;
4396     cr    : E(write);
4397     src1  : R(read);
4398     IALU  : R;
4399 %}
4400 
4401 // Integer ALU reg-reg-zero operation with condition code only
4402 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4403     single_instruction;
4404     cr    : E(write);
4405     src1  : R(read);
4406     src2  : R(read);
4407     IALU  : R;
4408 %}
4409 
4410 // Integer ALU reg-imm-zero operation with condition code only
4411 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4412     single_instruction;
4413     cr    : E(write);
4414     src1  : R(read);
4415     IALU  : R;
4416 %}
4417 
4418 // Integer ALU reg-reg operation with condition code, src1 modified
4419 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4420     single_instruction;
4421     cr    : E(write);
4422     src1  : E(write);
4423     src1  : R(read);
4424     src2  : R(read);
4425     IALU  : R;
4426 %}
4427 
4428 // Integer ALU reg-imm operation with condition code, src1 modified
4429 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4430     single_instruction;
4431     cr    : E(write);
4432     src1  : E(write);
4433     src1  : R(read);
4434     IALU  : R;
4435 %}
4436 
4437 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4438     multiple_bundles;
4439     dst   : E(write)+4;
4440     cr    : E(write);
4441     src1  : R(read);
4442     src2  : R(read);
4443     IALU  : R(3);
4444     BR    : R(2);
4445 %}
4446 
4447 // Integer ALU operation
4448 pipe_class ialu_none(iRegI dst) %{
4449     single_instruction;
4450     dst   : E(write);
4451     IALU  : R;
4452 %}
4453 
4454 // Integer ALU reg operation
4455 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4456     single_instruction; may_have_no_code;
4457     dst   : E(write);
4458     src   : R(read);
4459     IALU  : R;
4460 %}
4461 
4462 // Integer ALU reg conditional operation
4463 // This instruction has a 1 cycle stall, and cannot execute
4464 // in the same cycle as the instruction setting the condition
4465 // code. We kludge this by pretending to read the condition code
4466 // 1 cycle earlier, and by marking the functional units as busy
4467 // for 2 cycles with the result available 1 cycle later than
4468 // is really the case.
4469 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4470     single_instruction;
4471     op2_out : C(write);
4472     op1     : R(read);
4473     cr      : R(read);       // This is really E, with a 1 cycle stall
4474     BR      : R(2);
4475     MS      : R(2);
4476 %}
4477 
4478 #ifdef _LP64
4479 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4480     instruction_count(1); multiple_bundles;
4481     dst     : C(write)+1;
4482     src     : R(read)+1;
4483     IALU    : R(1);
4484     BR      : E(2);
4485     MS      : E(2);
4486 %}
4487 #endif
4488 
4489 // Integer ALU reg operation
4490 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4491     single_instruction; may_have_no_code;
4492     dst   : E(write);
4493     src   : R(read);
4494     IALU  : R;
4495 %}
4496 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4497     single_instruction; may_have_no_code;
4498     dst   : E(write);
4499     src   : R(read);
4500     IALU  : R;
4501 %}
4502 
4503 // Two integer ALU reg operations
4504 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4505     instruction_count(2);
4506     dst   : E(write);
4507     src   : R(read);
4508     A0    : R;
4509     A1    : R;
4510 %}
4511 
4512 // Two integer ALU reg operations
4513 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4514     instruction_count(2); may_have_no_code;
4515     dst   : E(write);
4516     src   : R(read);
4517     A0    : R;
4518     A1    : R;
4519 %}
4520 
4521 // Integer ALU imm operation
4522 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4523     single_instruction;
4524     dst   : E(write);
4525     IALU  : R;
4526 %}
4527 
4528 // Integer ALU reg-reg with carry operation
4529 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4530     single_instruction;
4531     dst   : E(write);
4532     src1  : R(read);
4533     src2  : R(read);
4534     IALU  : R;
4535 %}
4536 
4537 // Integer ALU cc operation
4538 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4539     single_instruction;
4540     dst   : E(write);
4541     cc    : R(read);
4542     IALU  : R;
4543 %}
4544 
4545 // Integer ALU cc / second IALU operation
4546 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4547     instruction_count(1); multiple_bundles;
4548     dst   : E(write)+1;
4549     src   : R(read);
4550     IALU  : R;
4551 %}
4552 
4553 // Integer ALU cc / second IALU operation
4554 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4555     instruction_count(1); multiple_bundles;
4556     dst   : E(write)+1;
4557     p     : R(read);
4558     q     : R(read);
4559     IALU  : R;
4560 %}
4561 
4562 // Integer ALU hi-lo-reg operation
4563 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4564     instruction_count(1); multiple_bundles;
4565     dst   : E(write)+1;
4566     IALU  : R(2);
4567 %}
4568 
4569 // Float ALU hi-lo-reg operation (with temp)
4570 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4571     instruction_count(1); multiple_bundles;
4572     dst   : E(write)+1;
4573     IALU  : R(2);
4574 %}
4575 
4576 // Long Constant
4577 pipe_class loadConL( iRegL dst, immL src ) %{
4578     instruction_count(2); multiple_bundles;
4579     dst   : E(write)+1;
4580     IALU  : R(2);
4581     IALU  : R(2);
4582 %}
4583 
4584 // Pointer Constant
4585 pipe_class loadConP( iRegP dst, immP src ) %{
4586     instruction_count(0); multiple_bundles;
4587     fixed_latency(6);
4588 %}
4589 
4590 // Polling Address
4591 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4592 #ifdef _LP64
4593     instruction_count(0); multiple_bundles;
4594     fixed_latency(6);
4595 #else
4596     dst   : E(write);
4597     IALU  : R;
4598 #endif
4599 %}
4600 
4601 // Long Constant small
4602 pipe_class loadConLlo( iRegL dst, immL src ) %{
4603     instruction_count(2);
4604     dst   : E(write);
4605     IALU  : R;
4606     IALU  : R;
4607 %}
4608 
4609 // [PHH] This is wrong for 64-bit.  See LdImmF/D.
4610 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4611     instruction_count(1); multiple_bundles;
4612     src   : R(read);
4613     dst   : M(write)+1;
4614     IALU  : R;
4615     MS    : E;
4616 %}
4617 
4618 // Integer ALU nop operation
4619 pipe_class ialu_nop() %{
4620     single_instruction;
4621     IALU  : R;
4622 %}
4623 
4624 // Integer ALU nop operation
4625 pipe_class ialu_nop_A0() %{
4626     single_instruction;
4627     A0    : R;
4628 %}
4629 
4630 // Integer ALU nop operation
4631 pipe_class ialu_nop_A1() %{
4632     single_instruction;
4633     A1    : R;
4634 %}
4635 
4636 // Integer Multiply reg-reg operation
4637 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4638     single_instruction;
4639     dst   : E(write);
4640     src1  : R(read);
4641     src2  : R(read);
4642     MS    : R(5);
4643 %}
4644 
4645 // Integer Multiply reg-imm operation
4646 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4647     single_instruction;
4648     dst   : E(write);
4649     src1  : R(read);
4650     MS    : R(5);
4651 %}
4652 
4653 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4654     single_instruction;
4655     dst   : E(write)+4;
4656     src1  : R(read);
4657     src2  : R(read);
4658     MS    : R(6);
4659 %}
4660 
4661 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4662     single_instruction;
4663     dst   : E(write)+4;
4664     src1  : R(read);
4665     MS    : R(6);
4666 %}
4667 
4668 // Integer Divide reg-reg
4669 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4670     instruction_count(1); multiple_bundles;
4671     dst   : E(write);
4672     temp  : E(write);
4673     src1  : R(read);
4674     src2  : R(read);
4675     temp  : R(read);
4676     MS    : R(38);
4677 %}
4678 
4679 // Integer Divide reg-imm
4680 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4681     instruction_count(1); multiple_bundles;
4682     dst   : E(write);
4683     temp  : E(write);
4684     src1  : R(read);
4685     temp  : R(read);
4686     MS    : R(38);
4687 %}
4688 
4689 // Long Divide
4690 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4691     dst  : E(write)+71;
4692     src1 : R(read);
4693     src2 : R(read)+1;
4694     MS   : R(70);
4695 %}
4696 
4697 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4698     dst  : E(write)+71;
4699     src1 : R(read);
4700     MS   : R(70);
4701 %}
4702 
4703 // Floating Point Add Float
4704 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4705     single_instruction;
4706     dst   : X(write);
4707     src1  : E(read);
4708     src2  : E(read);
4709     FA    : R;
4710 %}
4711 
4712 // Floating Point Add Double
4713 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4714     single_instruction;
4715     dst   : X(write);
4716     src1  : E(read);
4717     src2  : E(read);
4718     FA    : R;
4719 %}
4720 
4721 // Floating Point Conditional Move based on integer flags
4722 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4723     single_instruction;
4724     dst   : X(write);
4725     src   : E(read);
4726     cr    : R(read);
4727     FA    : R(2);
4728     BR    : R(2);
4729 %}
4730 
4731 // Floating Point Conditional Move based on integer flags
4732 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4733     single_instruction;
4734     dst   : X(write);
4735     src   : E(read);
4736     cr    : R(read);
4737     FA    : R(2);
4738     BR    : R(2);
4739 %}
4740 
4741 // Floating Point Multiply Float
4742 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4743     single_instruction;
4744     dst   : X(write);
4745     src1  : E(read);
4746     src2  : E(read);
4747     FM    : R;
4748 %}
4749 
4750 // Floating Point Multiply Double
4751 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4752     single_instruction;
4753     dst   : X(write);
4754     src1  : E(read);
4755     src2  : E(read);
4756     FM    : R;
4757 %}
4758 
4759 // Floating Point Divide Float
4760 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4761     single_instruction;
4762     dst   : X(write);
4763     src1  : E(read);
4764     src2  : E(read);
4765     FM    : R;
4766     FDIV  : C(14);
4767 %}
4768 
4769 // Floating Point Divide Double
4770 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4771     single_instruction;
4772     dst   : X(write);
4773     src1  : E(read);
4774     src2  : E(read);
4775     FM    : R;
4776     FDIV  : C(17);
4777 %}
4778 
4779 // Floating Point Move/Negate/Abs Float
4780 pipe_class faddF_reg(regF dst, regF src) %{
4781     single_instruction;
4782     dst   : W(write);
4783     src   : E(read);
4784     FA    : R(1);
4785 %}
4786 
4787 // Floating Point Move/Negate/Abs Double
4788 pipe_class faddD_reg(regD dst, regD src) %{
4789     single_instruction;
4790     dst   : W(write);
4791     src   : E(read);
4792     FA    : R;
4793 %}
4794 
4795 // Floating Point Convert F->D
4796 pipe_class fcvtF2D(regD dst, regF src) %{
4797     single_instruction;
4798     dst   : X(write);
4799     src   : E(read);
4800     FA    : R;
4801 %}
4802 
4803 // Floating Point Convert I->D
4804 pipe_class fcvtI2D(regD dst, regF src) %{
4805     single_instruction;
4806     dst   : X(write);
4807     src   : E(read);
4808     FA    : R;
4809 %}
4810 
4811 // Floating Point Convert LHi->D
4812 pipe_class fcvtLHi2D(regD dst, regD src) %{
4813     single_instruction;
4814     dst   : X(write);
4815     src   : E(read);
4816     FA    : R;
4817 %}
4818 
4819 // Floating Point Convert L->D
4820 pipe_class fcvtL2D(regD dst, regF src) %{
4821     single_instruction;
4822     dst   : X(write);
4823     src   : E(read);
4824     FA    : R;
4825 %}
4826 
4827 // Floating Point Convert L->F
4828 pipe_class fcvtL2F(regD dst, regF src) %{
4829     single_instruction;
4830     dst   : X(write);
4831     src   : E(read);
4832     FA    : R;
4833 %}
4834 
4835 // Floating Point Convert D->F
4836 pipe_class fcvtD2F(regD dst, regF src) %{
4837     single_instruction;
4838     dst   : X(write);
4839     src   : E(read);
4840     FA    : R;
4841 %}
4842 
4843 // Floating Point Convert I->L
4844 pipe_class fcvtI2L(regD dst, regF src) %{
4845     single_instruction;
4846     dst   : X(write);
4847     src   : E(read);
4848     FA    : R;
4849 %}
4850 
4851 // Floating Point Convert D->F
4852 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4853     instruction_count(1); multiple_bundles;
4854     dst   : X(write)+6;
4855     src   : E(read);
4856     FA    : R;
4857 %}
4858 
4859 // Floating Point Convert D->L
4860 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4861     instruction_count(1); multiple_bundles;
4862     dst   : X(write)+6;
4863     src   : E(read);
4864     FA    : R;
4865 %}
4866 
4867 // Floating Point Convert F->I
4868 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4869     instruction_count(1); multiple_bundles;
4870     dst   : X(write)+6;
4871     src   : E(read);
4872     FA    : R;
4873 %}
4874 
4875 // Floating Point Convert F->L
4876 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4877     instruction_count(1); multiple_bundles;
4878     dst   : X(write)+6;
4879     src   : E(read);
4880     FA    : R;
4881 %}
4882 
4883 // Floating Point Convert I->F
4884 pipe_class fcvtI2F(regF dst, regF src) %{
4885     single_instruction;
4886     dst   : X(write);
4887     src   : E(read);
4888     FA    : R;
4889 %}
4890 
4891 // Floating Point Compare
4892 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4893     single_instruction;
4894     cr    : X(write);
4895     src1  : E(read);
4896     src2  : E(read);
4897     FA    : R;
4898 %}
4899 
4900 // Floating Point Compare
4901 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4902     single_instruction;
4903     cr    : X(write);
4904     src1  : E(read);
4905     src2  : E(read);
4906     FA    : R;
4907 %}
4908 
4909 // Floating Add Nop
4910 pipe_class fadd_nop() %{
4911     single_instruction;
4912     FA  : R;
4913 %}
4914 
4915 // Integer Store to Memory
4916 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4917     single_instruction;
4918     mem   : R(read);
4919     src   : C(read);
4920     MS    : R;
4921 %}
4922 
4923 // Integer Store to Memory
4924 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4925     single_instruction;
4926     mem   : R(read);
4927     src   : C(read);
4928     MS    : R;
4929 %}
4930 
4931 // Integer Store Zero to Memory
4932 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4933     single_instruction;
4934     mem   : R(read);
4935     MS    : R;
4936 %}
4937 
4938 // Special Stack Slot Store
4939 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4940     single_instruction;
4941     stkSlot : R(read);
4942     src     : C(read);
4943     MS      : R;
4944 %}
4945 
4946 // Special Stack Slot Store
4947 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4948     instruction_count(2); multiple_bundles;
4949     stkSlot : R(read);
4950     src     : C(read);
4951     MS      : R(2);
4952 %}
4953 
4954 // Float Store
4955 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4956     single_instruction;
4957     mem : R(read);
4958     src : C(read);
4959     MS  : R;
4960 %}
4961 
4962 // Float Store
4963 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4964     single_instruction;
4965     mem : R(read);
4966     MS  : R;
4967 %}
4968 
4969 // Double Store
4970 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4971     instruction_count(1);
4972     mem : R(read);
4973     src : C(read);
4974     MS  : R;
4975 %}
4976 
4977 // Double Store
4978 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4979     single_instruction;
4980     mem : R(read);
4981     MS  : R;
4982 %}
4983 
4984 // Special Stack Slot Float Store
4985 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4986     single_instruction;
4987     stkSlot : R(read);
4988     src     : C(read);
4989     MS      : R;
4990 %}
4991 
4992 // Special Stack Slot Double Store
4993 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4994     single_instruction;
4995     stkSlot : R(read);
4996     src     : C(read);
4997     MS      : R;
4998 %}
4999 
5000 // Integer Load (when sign bit propagation not needed)
5001 pipe_class iload_mem(iRegI dst, memory mem) %{
5002     single_instruction;
5003     mem : R(read);
5004     dst : C(write);
5005     MS  : R;
5006 %}
5007 
5008 // Integer Load from stack operand
5009 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5010     single_instruction;
5011     mem : R(read);
5012     dst : C(write);
5013     MS  : R;
5014 %}
5015 
5016 // Integer Load (when sign bit propagation or masking is needed)
5017 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5018     single_instruction;
5019     mem : R(read);
5020     dst : M(write);
5021     MS  : R;
5022 %}
5023 
5024 // Float Load
5025 pipe_class floadF_mem(regF dst, memory mem) %{
5026     single_instruction;
5027     mem : R(read);
5028     dst : M(write);
5029     MS  : R;
5030 %}
5031 
5032 // Float Load
5033 pipe_class floadD_mem(regD dst, memory mem) %{
5034     instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5035     mem : R(read);
5036     dst : M(write);
5037     MS  : R;
5038 %}
5039 
5040 // Float Load
5041 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5042     single_instruction;
5043     stkSlot : R(read);
5044     dst : M(write);
5045     MS  : R;
5046 %}
5047 
5048 // Float Load
5049 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5050     single_instruction;
5051     stkSlot : R(read);
5052     dst : M(write);
5053     MS  : R;
5054 %}
5055 
5056 // Memory Nop
5057 pipe_class mem_nop() %{
5058     single_instruction;
5059     MS  : R;
5060 %}
5061 
5062 pipe_class sethi(iRegP dst, immI src) %{
5063     single_instruction;
5064     dst  : E(write);
5065     IALU : R;
5066 %}
5067 
5068 pipe_class loadPollP(iRegP poll) %{
5069     single_instruction;
5070     poll : R(read);
5071     MS   : R;
5072 %}
5073 
5074 pipe_class br(Universe br, label labl) %{
5075     single_instruction_with_delay_slot;
5076     BR  : R;
5077 %}
5078 
5079 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5080     single_instruction_with_delay_slot;
5081     cr    : E(read);
5082     BR    : R;
5083 %}
5084 
5085 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5086     single_instruction_with_delay_slot;
5087     op1 : E(read);
5088     BR  : R;
5089     MS  : R;
5090 %}
5091 
5092 // Compare and branch
5093 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5094     instruction_count(2); has_delay_slot;
5095     cr    : E(write);
5096     src1  : R(read);
5097     src2  : R(read);
5098     IALU  : R;
5099     BR    : R;
5100 %}
5101 
5102 // Compare and branch
5103 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5104     instruction_count(2); has_delay_slot;
5105     cr    : E(write);
5106     src1  : R(read);
5107     IALU  : R;
5108     BR    : R;
5109 %}
5110 
5111 // Compare and branch using cbcond
5112 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5113     single_instruction;
5114     src1  : E(read);
5115     src2  : E(read);
5116     IALU  : R;
5117     BR    : R;
5118 %}
5119 
5120 // Compare and branch using cbcond
5121 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5122     single_instruction;
5123     src1  : E(read);
5124     IALU  : R;
5125     BR    : R;
5126 %}
5127 
5128 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5129     single_instruction_with_delay_slot;
5130     cr    : E(read);
5131     BR    : R;
5132 %}
5133 
5134 pipe_class br_nop() %{
5135     single_instruction;
5136     BR  : R;
5137 %}
5138 
5139 pipe_class simple_call(method meth) %{
5140     instruction_count(2); multiple_bundles; force_serialization;
5141     fixed_latency(100);
5142     BR  : R(1);
5143     MS  : R(1);
5144     A0  : R(1);
5145 %}
5146 
5147 pipe_class compiled_call(method meth) %{
5148     instruction_count(1); multiple_bundles; force_serialization;
5149     fixed_latency(100);
5150     MS  : R(1);
5151 %}
5152 
5153 pipe_class call(method meth) %{
5154     instruction_count(0); multiple_bundles; force_serialization;
5155     fixed_latency(100);
5156 %}
5157 
5158 pipe_class tail_call(Universe ignore, label labl) %{
5159     single_instruction; has_delay_slot;
5160     fixed_latency(100);
5161     BR  : R(1);
5162     MS  : R(1);
5163 %}
5164 
5165 pipe_class ret(Universe ignore) %{
5166     single_instruction; has_delay_slot;
5167     BR  : R(1);
5168     MS  : R(1);
5169 %}
5170 
5171 pipe_class ret_poll(g3RegP poll) %{
5172     instruction_count(3); has_delay_slot;
5173     poll : E(read);
5174     MS   : R;
5175 %}
5176 
5177 // The real do-nothing guy
5178 pipe_class empty( ) %{
5179     instruction_count(0);
5180 %}
5181 
5182 pipe_class long_memory_op() %{
5183     instruction_count(0); multiple_bundles; force_serialization;
5184     fixed_latency(25);
5185     MS  : R(1);
5186 %}
5187 
5188 // Check-cast
5189 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5190     array : R(read);
5191     match  : R(read);
5192     IALU   : R(2);
5193     BR     : R(2);
5194     MS     : R;
5195 %}
5196 
5197 // Convert FPU flags into +1,0,-1
5198 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5199     src1  : E(read);
5200     src2  : E(read);
5201     dst   : E(write);
5202     FA    : R;
5203     MS    : R(2);
5204     BR    : R(2);
5205 %}
5206 
5207 // Compare for p < q, and conditionally add y
5208 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5209     p     : E(read);
5210     q     : E(read);
5211     y     : E(read);
5212     IALU  : R(3)
5213 %}
5214 
5215 // Perform a compare, then move conditionally in a branch delay slot.
5216 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5217     src2   : E(read);
5218     srcdst : E(read);
5219     IALU   : R;
5220     BR     : R;
5221 %}
5222 
5223 // Define the class for the Nop node
5224 define %{
5225    MachNop = ialu_nop;
5226 %}
5227 
5228 %}
5229 
5230 //----------INSTRUCTIONS-------------------------------------------------------
5231 
5232 //------------Special Stack Slot instructions - no match rules-----------------
5233 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5234   // No match rule to avoid chain rule match.
5235   effect(DEF dst, USE src);
5236   ins_cost(MEMORY_REF_COST);
5237   format %{ "LDF    $src,$dst\t! stkI to regF" %}
5238   opcode(Assembler::ldf_op3);
5239   ins_encode(simple_form3_mem_reg(src, dst));
5240   ins_pipe(floadF_stk);
5241 %}
5242 
5243 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5244   // No match rule to avoid chain rule match.
5245   effect(DEF dst, USE src);
5246   ins_cost(MEMORY_REF_COST);
5247   format %{ "LDDF   $src,$dst\t! stkL to regD" %}
5248   opcode(Assembler::lddf_op3);
5249   ins_encode(simple_form3_mem_reg(src, dst));
5250   ins_pipe(floadD_stk);
5251 %}
5252 
5253 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5254   // No match rule to avoid chain rule match.
5255   effect(DEF dst, USE src);
5256   ins_cost(MEMORY_REF_COST);
5257   format %{ "STF    $src,$dst\t! regF to stkI" %}
5258   opcode(Assembler::stf_op3);
5259   ins_encode(simple_form3_mem_reg(dst, src));
5260   ins_pipe(fstoreF_stk_reg);
5261 %}
5262 
5263 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5264   // No match rule to avoid chain rule match.
5265   effect(DEF dst, USE src);
5266   ins_cost(MEMORY_REF_COST);
5267   format %{ "STDF   $src,$dst\t! regD to stkL" %}
5268   opcode(Assembler::stdf_op3);
5269   ins_encode(simple_form3_mem_reg(dst, src));
5270   ins_pipe(fstoreD_stk_reg);
5271 %}
5272 
5273 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5274   effect(DEF dst, USE src);
5275   ins_cost(MEMORY_REF_COST*2);
5276   format %{ "STW    $src,$dst.hi\t! long\n\t"
5277             "STW    R_G0,$dst.lo" %}
5278   opcode(Assembler::stw_op3);
5279   ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5280   ins_pipe(lstoreI_stk_reg);
5281 %}
5282 
5283 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5284   // No match rule to avoid chain rule match.
5285   effect(DEF dst, USE src);
5286   ins_cost(MEMORY_REF_COST);
5287   format %{ "STX    $src,$dst\t! regL to stkD" %}
5288   opcode(Assembler::stx_op3);
5289   ins_encode(simple_form3_mem_reg( dst, src ) );
5290   ins_pipe(istore_stk_reg);
5291 %}
5292 
5293 //---------- Chain stack slots between similar types --------
5294 
5295 // Load integer from stack slot
5296 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5297   match(Set dst src);
5298   ins_cost(MEMORY_REF_COST);
5299 
5300   format %{ "LDUW   $src,$dst\t!stk" %}
5301   opcode(Assembler::lduw_op3);
5302   ins_encode(simple_form3_mem_reg( src, dst ) );
5303   ins_pipe(iload_mem);
5304 %}
5305 
5306 // Store integer to stack slot
5307 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5308   match(Set dst src);
5309   ins_cost(MEMORY_REF_COST);
5310 
5311   format %{ "STW    $src,$dst\t!stk" %}
5312   opcode(Assembler::stw_op3);
5313   ins_encode(simple_form3_mem_reg( dst, src ) );
5314   ins_pipe(istore_mem_reg);
5315 %}
5316 
5317 // Load long from stack slot
5318 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5319   match(Set dst src);
5320 
5321   ins_cost(MEMORY_REF_COST);
5322   format %{ "LDX    $src,$dst\t! long" %}
5323   opcode(Assembler::ldx_op3);
5324   ins_encode(simple_form3_mem_reg( src, dst ) );
5325   ins_pipe(iload_mem);
5326 %}
5327 
5328 // Store long to stack slot
5329 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5330   match(Set dst src);
5331 
5332   ins_cost(MEMORY_REF_COST);
5333   format %{ "STX    $src,$dst\t! long" %}
5334   opcode(Assembler::stx_op3);
5335   ins_encode(simple_form3_mem_reg( dst, src ) );
5336   ins_pipe(istore_mem_reg);
5337 %}
5338 
5339 #ifdef _LP64
5340 // Load pointer from stack slot, 64-bit encoding
5341 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5342   match(Set dst src);
5343   ins_cost(MEMORY_REF_COST);
5344   format %{ "LDX    $src,$dst\t!ptr" %}
5345   opcode(Assembler::ldx_op3);
5346   ins_encode(simple_form3_mem_reg( src, dst ) );
5347   ins_pipe(iload_mem);
5348 %}
5349 
5350 // Store pointer to stack slot
5351 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5352   match(Set dst src);
5353   ins_cost(MEMORY_REF_COST);
5354   format %{ "STX    $src,$dst\t!ptr" %}
5355   opcode(Assembler::stx_op3);
5356   ins_encode(simple_form3_mem_reg( dst, src ) );
5357   ins_pipe(istore_mem_reg);
5358 %}
5359 #else // _LP64
5360 // Load pointer from stack slot, 32-bit encoding
5361 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5362   match(Set dst src);
5363   ins_cost(MEMORY_REF_COST);
5364   format %{ "LDUW   $src,$dst\t!ptr" %}
5365   opcode(Assembler::lduw_op3, Assembler::ldst_op);
5366   ins_encode(simple_form3_mem_reg( src, dst ) );
5367   ins_pipe(iload_mem);
5368 %}
5369 
5370 // Store pointer to stack slot
5371 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5372   match(Set dst src);
5373   ins_cost(MEMORY_REF_COST);
5374   format %{ "STW    $src,$dst\t!ptr" %}
5375   opcode(Assembler::stw_op3, Assembler::ldst_op);
5376   ins_encode(simple_form3_mem_reg( dst, src ) );
5377   ins_pipe(istore_mem_reg);
5378 %}
5379 #endif // _LP64
5380 
5381 //------------Special Nop instructions for bundling - no match rules-----------
5382 // Nop using the A0 functional unit
5383 instruct Nop_A0() %{
5384   ins_cost(0);
5385 
5386   format %{ "NOP    ! Alu Pipeline" %}
5387   opcode(Assembler::or_op3, Assembler::arith_op);
5388   ins_encode( form2_nop() );
5389   ins_pipe(ialu_nop_A0);
5390 %}
5391 
5392 // Nop using the A1 functional unit
5393 instruct Nop_A1( ) %{
5394   ins_cost(0);
5395 
5396   format %{ "NOP    ! Alu Pipeline" %}
5397   opcode(Assembler::or_op3, Assembler::arith_op);
5398   ins_encode( form2_nop() );
5399   ins_pipe(ialu_nop_A1);
5400 %}
5401 
5402 // Nop using the memory functional unit
5403 instruct Nop_MS( ) %{
5404   ins_cost(0);
5405 
5406   format %{ "NOP    ! Memory Pipeline" %}
5407   ins_encode( emit_mem_nop );
5408   ins_pipe(mem_nop);
5409 %}
5410 
5411 // Nop using the floating add functional unit
5412 instruct Nop_FA( ) %{
5413   ins_cost(0);
5414 
5415   format %{ "NOP    ! Floating Add Pipeline" %}
5416   ins_encode( emit_fadd_nop );
5417   ins_pipe(fadd_nop);
5418 %}
5419 
5420 // Nop using the branch functional unit
5421 instruct Nop_BR( ) %{
5422   ins_cost(0);
5423 
5424   format %{ "NOP    ! Branch Pipeline" %}
5425   ins_encode( emit_br_nop );
5426   ins_pipe(br_nop);
5427 %}
5428 
5429 //----------Load/Store/Move Instructions---------------------------------------
5430 //----------Load Instructions--------------------------------------------------
5431 // Load Byte (8bit signed)
5432 instruct loadB(iRegI dst, memory mem) %{
5433   match(Set dst (LoadB mem));
5434   ins_cost(MEMORY_REF_COST);
5435 
5436   size(4);
5437   format %{ "LDSB   $mem,$dst\t! byte" %}
5438   ins_encode %{
5439     __ ldsb($mem$$Address, $dst$$Register);
5440   %}
5441   ins_pipe(iload_mask_mem);
5442 %}
5443 
5444 // Load Byte (8bit signed) into a Long Register
5445 instruct loadB2L(iRegL dst, memory mem) %{
5446   match(Set dst (ConvI2L (LoadB mem)));
5447   ins_cost(MEMORY_REF_COST);
5448 
5449   size(4);
5450   format %{ "LDSB   $mem,$dst\t! byte -> long" %}
5451   ins_encode %{
5452     __ ldsb($mem$$Address, $dst$$Register);
5453   %}
5454   ins_pipe(iload_mask_mem);
5455 %}
5456 
5457 // Load Unsigned Byte (8bit UNsigned) into an int reg
5458 instruct loadUB(iRegI dst, memory mem) %{
5459   match(Set dst (LoadUB mem));
5460   ins_cost(MEMORY_REF_COST);
5461 
5462   size(4);
5463   format %{ "LDUB   $mem,$dst\t! ubyte" %}
5464   ins_encode %{
5465     __ ldub($mem$$Address, $dst$$Register);
5466   %}
5467   ins_pipe(iload_mem);
5468 %}
5469 
5470 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5471 instruct loadUB2L(iRegL dst, memory mem) %{
5472   match(Set dst (ConvI2L (LoadUB mem)));
5473   ins_cost(MEMORY_REF_COST);
5474 
5475   size(4);
5476   format %{ "LDUB   $mem,$dst\t! ubyte -> long" %}
5477   ins_encode %{
5478     __ ldub($mem$$Address, $dst$$Register);
5479   %}
5480   ins_pipe(iload_mem);
5481 %}
5482 
5483 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5484 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5485   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5486   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5487 
5488   size(2*4);
5489   format %{ "LDUB   $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5490             "AND    $dst,right_n_bits($mask, 8),$dst" %}
5491   ins_encode %{
5492     __ ldub($mem$$Address, $dst$$Register);
5493     __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5494   %}
5495   ins_pipe(iload_mem);
5496 %}
5497 
5498 // Load Short (16bit signed)
5499 instruct loadS(iRegI dst, memory mem) %{
5500   match(Set dst (LoadS mem));
5501   ins_cost(MEMORY_REF_COST);
5502 
5503   size(4);
5504   format %{ "LDSH   $mem,$dst\t! short" %}
5505   ins_encode %{
5506     __ ldsh($mem$$Address, $dst$$Register);
5507   %}
5508   ins_pipe(iload_mask_mem);
5509 %}
5510 
5511 // Load Short (16 bit signed) to Byte (8 bit signed)
5512 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5513   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5514   ins_cost(MEMORY_REF_COST);
5515 
5516   size(4);
5517 
5518   format %{ "LDSB   $mem+1,$dst\t! short -> byte" %}
5519   ins_encode %{
5520     __ ldsb($mem$$Address, $dst$$Register, 1);
5521   %}
5522   ins_pipe(iload_mask_mem);
5523 %}
5524 
5525 // Load Short (16bit signed) into a Long Register
5526 instruct loadS2L(iRegL dst, memory mem) %{
5527   match(Set dst (ConvI2L (LoadS mem)));
5528   ins_cost(MEMORY_REF_COST);
5529 
5530   size(4);
5531   format %{ "LDSH   $mem,$dst\t! short -> long" %}
5532   ins_encode %{
5533     __ ldsh($mem$$Address, $dst$$Register);
5534   %}
5535   ins_pipe(iload_mask_mem);
5536 %}
5537 
5538 // Load Unsigned Short/Char (16bit UNsigned)
5539 instruct loadUS(iRegI dst, memory mem) %{
5540   match(Set dst (LoadUS mem));
5541   ins_cost(MEMORY_REF_COST);
5542 
5543   size(4);
5544   format %{ "LDUH   $mem,$dst\t! ushort/char" %}
5545   ins_encode %{
5546     __ lduh($mem$$Address, $dst$$Register);
5547   %}
5548   ins_pipe(iload_mem);
5549 %}
5550 
5551 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5552 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5553   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5554   ins_cost(MEMORY_REF_COST);
5555 
5556   size(4);
5557   format %{ "LDSB   $mem+1,$dst\t! ushort -> byte" %}
5558   ins_encode %{
5559     __ ldsb($mem$$Address, $dst$$Register, 1);
5560   %}
5561   ins_pipe(iload_mask_mem);
5562 %}
5563 
5564 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5565 instruct loadUS2L(iRegL dst, memory mem) %{
5566   match(Set dst (ConvI2L (LoadUS mem)));
5567   ins_cost(MEMORY_REF_COST);
5568 
5569   size(4);
5570   format %{ "LDUH   $mem,$dst\t! ushort/char -> long" %}
5571   ins_encode %{
5572     __ lduh($mem$$Address, $dst$$Register);
5573   %}
5574   ins_pipe(iload_mem);
5575 %}
5576 
5577 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5578 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5579   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5580   ins_cost(MEMORY_REF_COST);
5581 
5582   size(4);
5583   format %{ "LDUB   $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5584   ins_encode %{
5585     __ ldub($mem$$Address, $dst$$Register, 1);  // LSB is index+1 on BE
5586   %}
5587   ins_pipe(iload_mem);
5588 %}
5589 
5590 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5591 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5592   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5593   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5594 
5595   size(2*4);
5596   format %{ "LDUH   $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5597             "AND    $dst,$mask,$dst" %}
5598   ins_encode %{
5599     Register Rdst = $dst$$Register;
5600     __ lduh($mem$$Address, Rdst);
5601     __ and3(Rdst, $mask$$constant, Rdst);
5602   %}
5603   ins_pipe(iload_mem);
5604 %}
5605 
5606 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5607 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5608   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5609   effect(TEMP dst, TEMP tmp);
5610   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5611 
5612   format %{ "LDUH   $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5613             "SET    right_n_bits($mask, 16),$tmp\n\t"
5614             "AND    $dst,$tmp,$dst" %}
5615   ins_encode %{
5616     Register Rdst = $dst$$Register;
5617     Register Rtmp = $tmp$$Register;
5618     __ lduh($mem$$Address, Rdst);
5619     __ set($mask$$constant & right_n_bits(16), Rtmp);
5620     __ and3(Rdst, Rtmp, Rdst);
5621   %}
5622   ins_pipe(iload_mem);
5623 %}
5624 
5625 // Load Integer
5626 instruct loadI(iRegI dst, memory mem) %{
5627   match(Set dst (LoadI mem));
5628   ins_cost(MEMORY_REF_COST);
5629 
5630   size(4);
5631   format %{ "LDUW   $mem,$dst\t! int" %}
5632   ins_encode %{
5633     __ lduw($mem$$Address, $dst$$Register);
5634   %}
5635   ins_pipe(iload_mem);
5636 %}
5637 
5638 // Load Integer to Byte (8 bit signed)
5639 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5640   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5641   ins_cost(MEMORY_REF_COST);
5642 
5643   size(4);
5644 
5645   format %{ "LDSB   $mem+3,$dst\t! int -> byte" %}
5646   ins_encode %{
5647     __ ldsb($mem$$Address, $dst$$Register, 3);
5648   %}
5649   ins_pipe(iload_mask_mem);
5650 %}
5651 
5652 // Load Integer to Unsigned Byte (8 bit UNsigned)
5653 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5654   match(Set dst (AndI (LoadI mem) mask));
5655   ins_cost(MEMORY_REF_COST);
5656 
5657   size(4);
5658 
5659   format %{ "LDUB   $mem+3,$dst\t! int -> ubyte" %}
5660   ins_encode %{
5661     __ ldub($mem$$Address, $dst$$Register, 3);
5662   %}
5663   ins_pipe(iload_mask_mem);
5664 %}
5665 
5666 // Load Integer to Short (16 bit signed)
5667 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5668   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5669   ins_cost(MEMORY_REF_COST);
5670 
5671   size(4);
5672 
5673   format %{ "LDSH   $mem+2,$dst\t! int -> short" %}
5674   ins_encode %{
5675     __ ldsh($mem$$Address, $dst$$Register, 2);
5676   %}
5677   ins_pipe(iload_mask_mem);
5678 %}
5679 
5680 // Load Integer to Unsigned Short (16 bit UNsigned)
5681 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5682   match(Set dst (AndI (LoadI mem) mask));
5683   ins_cost(MEMORY_REF_COST);
5684 
5685   size(4);
5686 
5687   format %{ "LDUH   $mem+2,$dst\t! int -> ushort/char" %}
5688   ins_encode %{
5689     __ lduh($mem$$Address, $dst$$Register, 2);
5690   %}
5691   ins_pipe(iload_mask_mem);
5692 %}
5693 
5694 // Load Integer into a Long Register
5695 instruct loadI2L(iRegL dst, memory mem) %{
5696   match(Set dst (ConvI2L (LoadI mem)));
5697   ins_cost(MEMORY_REF_COST);
5698 
5699   size(4);
5700   format %{ "LDSW   $mem,$dst\t! int -> long" %}
5701   ins_encode %{
5702     __ ldsw($mem$$Address, $dst$$Register);
5703   %}
5704   ins_pipe(iload_mask_mem);
5705 %}
5706 
5707 // Load Integer with mask 0xFF into a Long Register
5708 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5709   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5710   ins_cost(MEMORY_REF_COST);
5711 
5712   size(4);
5713   format %{ "LDUB   $mem+3,$dst\t! int & 0xFF -> long" %}
5714   ins_encode %{
5715     __ ldub($mem$$Address, $dst$$Register, 3);  // LSB is index+3 on BE
5716   %}
5717   ins_pipe(iload_mem);
5718 %}
5719 
5720 // Load Integer with mask 0xFFFF into a Long Register
5721 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5722   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5723   ins_cost(MEMORY_REF_COST);
5724 
5725   size(4);
5726   format %{ "LDUH   $mem+2,$dst\t! int & 0xFFFF -> long" %}
5727   ins_encode %{
5728     __ lduh($mem$$Address, $dst$$Register, 2);  // LSW is index+2 on BE
5729   %}
5730   ins_pipe(iload_mem);
5731 %}
5732 
5733 // Load Integer with a 12-bit mask into a Long Register
5734 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5735   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5736   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5737 
5738   size(2*4);
5739   format %{ "LDUW   $mem,$dst\t! int & 12-bit mask -> long\n\t"
5740             "AND    $dst,$mask,$dst" %}
5741   ins_encode %{
5742     Register Rdst = $dst$$Register;
5743     __ lduw($mem$$Address, Rdst);
5744     __ and3(Rdst, $mask$$constant, Rdst);
5745   %}
5746   ins_pipe(iload_mem);
5747 %}
5748 
5749 // Load Integer with a 31-bit mask into a Long Register
5750 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5751   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5752   effect(TEMP dst, TEMP tmp);
5753   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5754 
5755   format %{ "LDUW   $mem,$dst\t! int & 31-bit mask -> long\n\t"
5756             "SET    $mask,$tmp\n\t"
5757             "AND    $dst,$tmp,$dst" %}
5758   ins_encode %{
5759     Register Rdst = $dst$$Register;
5760     Register Rtmp = $tmp$$Register;
5761     __ lduw($mem$$Address, Rdst);
5762     __ set($mask$$constant, Rtmp);
5763     __ and3(Rdst, Rtmp, Rdst);
5764   %}
5765   ins_pipe(iload_mem);
5766 %}
5767 
5768 // Load Unsigned Integer into a Long Register
5769 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5770   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5771   ins_cost(MEMORY_REF_COST);
5772 
5773   size(4);
5774   format %{ "LDUW   $mem,$dst\t! uint -> long" %}
5775   ins_encode %{
5776     __ lduw($mem$$Address, $dst$$Register);
5777   %}
5778   ins_pipe(iload_mem);
5779 %}
5780 
5781 // Load Long - aligned
5782 instruct loadL(iRegL dst, memory mem ) %{
5783   match(Set dst (LoadL mem));
5784   ins_cost(MEMORY_REF_COST);
5785 
5786   size(4);
5787   format %{ "LDX    $mem,$dst\t! long" %}
5788   ins_encode %{
5789     __ ldx($mem$$Address, $dst$$Register);
5790   %}
5791   ins_pipe(iload_mem);
5792 %}
5793 
5794 // Load Long - UNaligned
5795 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5796   match(Set dst (LoadL_unaligned mem));
5797   effect(KILL tmp);
5798   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5799   format %{ "LDUW   $mem+4,R_O7\t! misaligned long\n"
5800           "\tLDUW   $mem  ,$dst\n"
5801           "\tSLLX   #32, $dst, $dst\n"
5802           "\tOR     $dst, R_O7, $dst" %}
5803   opcode(Assembler::lduw_op3);
5804   ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5805   ins_pipe(iload_mem);
5806 %}
5807 
5808 // Load Range
5809 instruct loadRange(iRegI dst, memory mem) %{
5810   match(Set dst (LoadRange mem));
5811   ins_cost(MEMORY_REF_COST);
5812 
5813   format %{ "LDUW   $mem,$dst\t! range" %}
5814   opcode(Assembler::lduw_op3);
5815   ins_encode(simple_form3_mem_reg( mem, dst ) );
5816   ins_pipe(iload_mem);
5817 %}
5818 
5819 // Load Integer into %f register (for fitos/fitod)
5820 instruct loadI_freg(regF dst, memory mem) %{
5821   match(Set dst (LoadI mem));
5822   ins_cost(MEMORY_REF_COST);
5823 
5824   format %{ "LDF    $mem,$dst\t! for fitos/fitod" %}
5825   opcode(Assembler::ldf_op3);
5826   ins_encode(simple_form3_mem_reg( mem, dst ) );
5827   ins_pipe(floadF_mem);
5828 %}
5829 
5830 // Load Pointer
5831 instruct loadP(iRegP dst, memory mem) %{
5832   match(Set dst (LoadP mem));
5833   ins_cost(MEMORY_REF_COST);
5834   size(4);
5835 
5836 #ifndef _LP64
5837   format %{ "LDUW   $mem,$dst\t! ptr" %}
5838   ins_encode %{
5839     __ lduw($mem$$Address, $dst$$Register);
5840   %}
5841 #else
5842   format %{ "LDX    $mem,$dst\t! ptr" %}
5843   ins_encode %{
5844     __ ldx($mem$$Address, $dst$$Register);
5845   %}
5846 #endif
5847   ins_pipe(iload_mem);
5848 %}
5849 
5850 // Load Compressed Pointer
5851 instruct loadN(iRegN dst, memory mem) %{
5852   match(Set dst (LoadN mem));
5853   ins_cost(MEMORY_REF_COST);
5854   size(4);
5855 
5856   format %{ "LDUW   $mem,$dst\t! compressed ptr" %}
5857   ins_encode %{
5858     __ lduw($mem$$Address, $dst$$Register);
5859   %}
5860   ins_pipe(iload_mem);
5861 %}
5862 
5863 // Load Klass Pointer
5864 instruct loadKlass(iRegP dst, memory mem) %{
5865   match(Set dst (LoadKlass mem));
5866   ins_cost(MEMORY_REF_COST);
5867   size(4);
5868 
5869 #ifndef _LP64
5870   format %{ "LDUW   $mem,$dst\t! klass ptr" %}
5871   ins_encode %{
5872     __ lduw($mem$$Address, $dst$$Register);
5873   %}
5874 #else
5875   format %{ "LDX    $mem,$dst\t! klass ptr" %}
5876   ins_encode %{
5877     __ ldx($mem$$Address, $dst$$Register);
5878   %}
5879 #endif
5880   ins_pipe(iload_mem);
5881 %}
5882 
5883 // Load narrow Klass Pointer
5884 instruct loadNKlass(iRegN dst, memory mem) %{
5885   match(Set dst (LoadNKlass mem));
5886   ins_cost(MEMORY_REF_COST);
5887   size(4);
5888 
5889   format %{ "LDUW   $mem,$dst\t! compressed klass ptr" %}
5890   ins_encode %{
5891     __ lduw($mem$$Address, $dst$$Register);
5892   %}
5893   ins_pipe(iload_mem);
5894 %}
5895 
5896 // Load Double
5897 instruct loadD(regD dst, memory mem) %{
5898   match(Set dst (LoadD mem));
5899   ins_cost(MEMORY_REF_COST);
5900 
5901   format %{ "LDDF   $mem,$dst" %}
5902   opcode(Assembler::lddf_op3);
5903   ins_encode(simple_form3_mem_reg( mem, dst ) );
5904   ins_pipe(floadD_mem);
5905 %}
5906 
5907 // Load Double - UNaligned
5908 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5909   match(Set dst (LoadD_unaligned mem));
5910   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5911   format %{ "LDF    $mem  ,$dst.hi\t! misaligned double\n"
5912           "\tLDF    $mem+4,$dst.lo\t!" %}
5913   opcode(Assembler::ldf_op3);
5914   ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5915   ins_pipe(iload_mem);
5916 %}
5917 
5918 // Load Float
5919 instruct loadF(regF dst, memory mem) %{
5920   match(Set dst (LoadF mem));
5921   ins_cost(MEMORY_REF_COST);
5922 
5923   format %{ "LDF    $mem,$dst" %}
5924   opcode(Assembler::ldf_op3);
5925   ins_encode(simple_form3_mem_reg( mem, dst ) );
5926   ins_pipe(floadF_mem);
5927 %}
5928 
5929 // Load Constant
5930 instruct loadConI( iRegI dst, immI src ) %{
5931   match(Set dst src);
5932   ins_cost(DEFAULT_COST * 3/2);
5933   format %{ "SET    $src,$dst" %}
5934   ins_encode( Set32(src, dst) );
5935   ins_pipe(ialu_hi_lo_reg);
5936 %}
5937 
5938 instruct loadConI13( iRegI dst, immI13 src ) %{
5939   match(Set dst src);
5940 
5941   size(4);
5942   format %{ "MOV    $src,$dst" %}
5943   ins_encode( Set13( src, dst ) );
5944   ins_pipe(ialu_imm);
5945 %}
5946 
5947 #ifndef _LP64
5948 instruct loadConP(iRegP dst, immP con) %{
5949   match(Set dst con);
5950   ins_cost(DEFAULT_COST * 3/2);
5951   format %{ "SET    $con,$dst\t!ptr" %}
5952   ins_encode %{
5953     relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5954       intptr_t val = $con$$constant;
5955     if (constant_reloc == relocInfo::oop_type) {
5956       __ set_oop_constant((jobject) val, $dst$$Register);
5957     } else if (constant_reloc == relocInfo::metadata_type) {
5958       __ set_metadata_constant((Metadata*)val, $dst$$Register);
5959     } else {          // non-oop pointers, e.g. card mark base, heap top
5960       assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5961       __ set(val, $dst$$Register);
5962     }
5963   %}
5964   ins_pipe(loadConP);
5965 %}
5966 #else
5967 instruct loadConP_set(iRegP dst, immP_set con) %{
5968   match(Set dst con);
5969   ins_cost(DEFAULT_COST * 3/2);
5970   format %{ "SET    $con,$dst\t! ptr" %}
5971   ins_encode %{
5972     relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5973       intptr_t val = $con$$constant;
5974     if (constant_reloc == relocInfo::oop_type) {
5975       __ set_oop_constant((jobject) val, $dst$$Register);
5976     } else if (constant_reloc == relocInfo::metadata_type) {
5977       __ set_metadata_constant((Metadata*)val, $dst$$Register);
5978     } else {          // non-oop pointers, e.g. card mark base, heap top
5979       assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5980       __ set(val, $dst$$Register);
5981     }
5982   %}
5983   ins_pipe(loadConP);
5984 %}
5985 
5986 instruct loadConP_load(iRegP dst, immP_load con) %{
5987   match(Set dst con);
5988   ins_cost(MEMORY_REF_COST);
5989   format %{ "LD     [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5990   ins_encode %{
5991     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5992     __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5993   %}
5994   ins_pipe(loadConP);
5995 %}
5996 
5997 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5998   match(Set dst con);
5999   ins_cost(DEFAULT_COST * 3/2);
6000   format %{ "SET    $con,$dst\t! non-oop ptr" %}
6001   ins_encode %{
6002     if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
6003       __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
6004     } else {
6005       __ set($con$$constant, $dst$$Register);
6006     }
6007   %}
6008   ins_pipe(loadConP);
6009 %}
6010 #endif // _LP64
6011 
6012 instruct loadConP0(iRegP dst, immP0 src) %{
6013   match(Set dst src);
6014 
6015   size(4);
6016   format %{ "CLR    $dst\t!ptr" %}
6017   ins_encode %{
6018     __ clr($dst$$Register);
6019   %}
6020   ins_pipe(ialu_imm);
6021 %}
6022 
6023 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6024   match(Set dst src);
6025   ins_cost(DEFAULT_COST);
6026   format %{ "SET    $src,$dst\t!ptr" %}
6027   ins_encode %{
6028     AddressLiteral polling_page(os::get_polling_page());
6029     __ sethi(polling_page, reg_to_register_object($dst$$reg));
6030   %}
6031   ins_pipe(loadConP_poll);
6032 %}
6033 
6034 instruct loadConN0(iRegN dst, immN0 src) %{
6035   match(Set dst src);
6036 
6037   size(4);
6038   format %{ "CLR    $dst\t! compressed NULL ptr" %}
6039   ins_encode %{
6040     __ clr($dst$$Register);
6041   %}
6042   ins_pipe(ialu_imm);
6043 %}
6044 
6045 instruct loadConN(iRegN dst, immN src) %{
6046   match(Set dst src);
6047   ins_cost(DEFAULT_COST * 3/2);
6048   format %{ "SET    $src,$dst\t! compressed ptr" %}
6049   ins_encode %{
6050     Register dst = $dst$$Register;
6051     __ set_narrow_oop((jobject)$src$$constant, dst);
6052   %}
6053   ins_pipe(ialu_hi_lo_reg);
6054 %}
6055 
6056 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6057   match(Set dst src);
6058   ins_cost(DEFAULT_COST * 3/2);
6059   format %{ "SET    $src,$dst\t! compressed klass ptr" %}
6060   ins_encode %{
6061     Register dst = $dst$$Register;
6062     __ set_narrow_klass((Klass*)$src$$constant, dst);
6063   %}
6064   ins_pipe(ialu_hi_lo_reg);
6065 %}
6066 
6067 // Materialize long value (predicated by immL_cheap).
6068 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6069   match(Set dst con);
6070   effect(KILL tmp);
6071   ins_cost(DEFAULT_COST * 3);
6072   format %{ "SET64   $con,$dst KILL $tmp\t! cheap long" %}
6073   ins_encode %{
6074     __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6075   %}
6076   ins_pipe(loadConL);
6077 %}
6078 
6079 // Load long value from constant table (predicated by immL_expensive).
6080 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6081   match(Set dst con);
6082   ins_cost(MEMORY_REF_COST);
6083   format %{ "LDX     [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6084   ins_encode %{
6085       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6086     __ ldx($constanttablebase, con_offset, $dst$$Register);
6087   %}
6088   ins_pipe(loadConL);
6089 %}
6090 
6091 instruct loadConL0( iRegL dst, immL0 src ) %{
6092   match(Set dst src);
6093   ins_cost(DEFAULT_COST);
6094   size(4);
6095   format %{ "CLR    $dst\t! long" %}
6096   ins_encode( Set13( src, dst ) );
6097   ins_pipe(ialu_imm);
6098 %}
6099 
6100 instruct loadConL13( iRegL dst, immL13 src ) %{
6101   match(Set dst src);
6102   ins_cost(DEFAULT_COST * 2);
6103 
6104   size(4);
6105   format %{ "MOV    $src,$dst\t! long" %}
6106   ins_encode( Set13( src, dst ) );
6107   ins_pipe(ialu_imm);
6108 %}
6109 
6110 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6111   match(Set dst con);
6112   effect(KILL tmp);
6113   format %{ "LDF    [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6114   ins_encode %{
6115       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6116     __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6117   %}
6118   ins_pipe(loadConFD);
6119 %}
6120 
6121 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6122   match(Set dst con);
6123   effect(KILL tmp);
6124   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6125   ins_encode %{
6126     // XXX This is a quick fix for 6833573.
6127     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6128     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6129     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6130   %}
6131   ins_pipe(loadConFD);
6132 %}
6133 
6134 // Prefetch instructions for allocation.
6135 // Must be safe to execute with invalid address (cannot fault).
6136 
6137 instruct prefetchAlloc( memory mem ) %{
6138   predicate(AllocatePrefetchInstr == 0);
6139   match( PrefetchAllocation mem );
6140   ins_cost(MEMORY_REF_COST);
6141 
6142   format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6143   opcode(Assembler::prefetch_op3);
6144   ins_encode( form3_mem_prefetch_write( mem ) );
6145   ins_pipe(iload_mem);
6146 %}
6147 
6148 // Use BIS instruction to prefetch for allocation.
6149 // Could fault, need space at the end of TLAB.
6150 instruct prefetchAlloc_bis( iRegP dst ) %{
6151   predicate(AllocatePrefetchInstr == 1);
6152   match( PrefetchAllocation dst );
6153   ins_cost(MEMORY_REF_COST);
6154   size(4);
6155 
6156   format %{ "STXA   [$dst]\t! // Prefetch allocation using BIS" %}
6157   ins_encode %{
6158     __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6159   %}
6160   ins_pipe(istore_mem_reg);
6161 %}
6162 
6163 // Next code is used for finding next cache line address to prefetch.
6164 #ifndef _LP64
6165 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6166   match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6167   ins_cost(DEFAULT_COST);
6168   size(4);
6169 
6170   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
6171   ins_encode %{
6172     __ and3($src$$Register, $mask$$constant, $dst$$Register);
6173   %}
6174   ins_pipe(ialu_reg_imm);
6175 %}
6176 #else
6177 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6178   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6179   ins_cost(DEFAULT_COST);
6180   size(4);
6181 
6182   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
6183   ins_encode %{
6184     __ and3($src$$Register, $mask$$constant, $dst$$Register);
6185   %}
6186   ins_pipe(ialu_reg_imm);
6187 %}
6188 #endif
6189 
6190 //----------Store Instructions-------------------------------------------------
6191 // Store Byte
6192 instruct storeB(memory mem, iRegI src) %{
6193   match(Set mem (StoreB mem src));
6194   ins_cost(MEMORY_REF_COST);
6195 
6196   format %{ "STB    $src,$mem\t! byte" %}
6197   opcode(Assembler::stb_op3);
6198   ins_encode(simple_form3_mem_reg( mem, src ) );
6199   ins_pipe(istore_mem_reg);
6200 %}
6201 
6202 instruct storeB0(memory mem, immI0 src) %{
6203   match(Set mem (StoreB mem src));
6204   ins_cost(MEMORY_REF_COST);
6205 
6206   format %{ "STB    $src,$mem\t! byte" %}
6207   opcode(Assembler::stb_op3);
6208   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6209   ins_pipe(istore_mem_zero);
6210 %}
6211 
6212 instruct storeCM0(memory mem, immI0 src) %{
6213   match(Set mem (StoreCM mem src));
6214   ins_cost(MEMORY_REF_COST);
6215 
6216   format %{ "STB    $src,$mem\t! CMS card-mark byte 0" %}
6217   opcode(Assembler::stb_op3);
6218   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6219   ins_pipe(istore_mem_zero);
6220 %}
6221 
6222 // Store Char/Short
6223 instruct storeC(memory mem, iRegI src) %{
6224   match(Set mem (StoreC mem src));
6225   ins_cost(MEMORY_REF_COST);
6226 
6227   format %{ "STH    $src,$mem\t! short" %}
6228   opcode(Assembler::sth_op3);
6229   ins_encode(simple_form3_mem_reg( mem, src ) );
6230   ins_pipe(istore_mem_reg);
6231 %}
6232 
6233 instruct storeC0(memory mem, immI0 src) %{
6234   match(Set mem (StoreC mem src));
6235   ins_cost(MEMORY_REF_COST);
6236 
6237   format %{ "STH    $src,$mem\t! short" %}
6238   opcode(Assembler::sth_op3);
6239   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6240   ins_pipe(istore_mem_zero);
6241 %}
6242 
6243 // Store Integer
6244 instruct storeI(memory mem, iRegI src) %{
6245   match(Set mem (StoreI mem src));
6246   ins_cost(MEMORY_REF_COST);
6247 
6248   format %{ "STW    $src,$mem" %}
6249   opcode(Assembler::stw_op3);
6250   ins_encode(simple_form3_mem_reg( mem, src ) );
6251   ins_pipe(istore_mem_reg);
6252 %}
6253 
6254 // Store Long
6255 instruct storeL(memory mem, iRegL src) %{
6256   match(Set mem (StoreL mem src));
6257   ins_cost(MEMORY_REF_COST);
6258   format %{ "STX    $src,$mem\t! long" %}
6259   opcode(Assembler::stx_op3);
6260   ins_encode(simple_form3_mem_reg( mem, src ) );
6261   ins_pipe(istore_mem_reg);
6262 %}
6263 
6264 instruct storeI0(memory mem, immI0 src) %{
6265   match(Set mem (StoreI mem src));
6266   ins_cost(MEMORY_REF_COST);
6267 
6268   format %{ "STW    $src,$mem" %}
6269   opcode(Assembler::stw_op3);
6270   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6271   ins_pipe(istore_mem_zero);
6272 %}
6273 
6274 instruct storeL0(memory mem, immL0 src) %{
6275   match(Set mem (StoreL mem src));
6276   ins_cost(MEMORY_REF_COST);
6277 
6278   format %{ "STX    $src,$mem" %}
6279   opcode(Assembler::stx_op3);
6280   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6281   ins_pipe(istore_mem_zero);
6282 %}
6283 
6284 // Store Integer from float register (used after fstoi)
6285 instruct storeI_Freg(memory mem, regF src) %{
6286   match(Set mem (StoreI mem src));
6287   ins_cost(MEMORY_REF_COST);
6288 
6289   format %{ "STF    $src,$mem\t! after fstoi/fdtoi" %}
6290   opcode(Assembler::stf_op3);
6291   ins_encode(simple_form3_mem_reg( mem, src ) );
6292   ins_pipe(fstoreF_mem_reg);
6293 %}
6294 
6295 // Store Pointer
6296 instruct storeP(memory dst, sp_ptr_RegP src) %{
6297   match(Set dst (StoreP dst src));
6298   ins_cost(MEMORY_REF_COST);
6299 
6300 #ifndef _LP64
6301   format %{ "STW    $src,$dst\t! ptr" %}
6302   opcode(Assembler::stw_op3, 0, REGP_OP);
6303 #else
6304   format %{ "STX    $src,$dst\t! ptr" %}
6305   opcode(Assembler::stx_op3, 0, REGP_OP);
6306 #endif
6307   ins_encode( form3_mem_reg( dst, src ) );
6308   ins_pipe(istore_mem_spORreg);
6309 %}
6310 
6311 instruct storeP0(memory dst, immP0 src) %{
6312   match(Set dst (StoreP dst src));
6313   ins_cost(MEMORY_REF_COST);
6314 
6315 #ifndef _LP64
6316   format %{ "STW    $src,$dst\t! ptr" %}
6317   opcode(Assembler::stw_op3, 0, REGP_OP);
6318 #else
6319   format %{ "STX    $src,$dst\t! ptr" %}
6320   opcode(Assembler::stx_op3, 0, REGP_OP);
6321 #endif
6322   ins_encode( form3_mem_reg( dst, R_G0 ) );
6323   ins_pipe(istore_mem_zero);
6324 %}
6325 
6326 // Store Compressed Pointer
6327 instruct storeN(memory dst, iRegN src) %{
6328    match(Set dst (StoreN dst src));
6329    ins_cost(MEMORY_REF_COST);
6330    size(4);
6331 
6332    format %{ "STW    $src,$dst\t! compressed ptr" %}
6333    ins_encode %{
6334      Register base = as_Register($dst$$base);
6335      Register index = as_Register($dst$$index);
6336      Register src = $src$$Register;
6337      if (index != G0) {
6338        __ stw(src, base, index);
6339      } else {
6340        __ stw(src, base, $dst$$disp);
6341      }
6342    %}
6343    ins_pipe(istore_mem_spORreg);
6344 %}
6345 
6346 instruct storeNKlass(memory dst, iRegN src) %{
6347    match(Set dst (StoreNKlass dst src));
6348    ins_cost(MEMORY_REF_COST);
6349    size(4);
6350 
6351    format %{ "STW    $src,$dst\t! compressed klass ptr" %}
6352    ins_encode %{
6353      Register base = as_Register($dst$$base);
6354      Register index = as_Register($dst$$index);
6355      Register src = $src$$Register;
6356      if (index != G0) {
6357        __ stw(src, base, index);
6358      } else {
6359        __ stw(src, base, $dst$$disp);
6360      }
6361    %}
6362    ins_pipe(istore_mem_spORreg);
6363 %}
6364 
6365 instruct storeN0(memory dst, immN0 src) %{
6366    match(Set dst (StoreN dst src));
6367    ins_cost(MEMORY_REF_COST);
6368    size(4);
6369 
6370    format %{ "STW    $src,$dst\t! compressed ptr" %}
6371    ins_encode %{
6372      Register base = as_Register($dst$$base);
6373      Register index = as_Register($dst$$index);
6374      if (index != G0) {
6375        __ stw(0, base, index);
6376      } else {
6377        __ stw(0, base, $dst$$disp);
6378      }
6379    %}
6380    ins_pipe(istore_mem_zero);
6381 %}
6382 
6383 // Store Double
6384 instruct storeD( memory mem, regD src) %{
6385   match(Set mem (StoreD mem src));
6386   ins_cost(MEMORY_REF_COST);
6387 
6388   format %{ "STDF   $src,$mem" %}
6389   opcode(Assembler::stdf_op3);
6390   ins_encode(simple_form3_mem_reg( mem, src ) );
6391   ins_pipe(fstoreD_mem_reg);
6392 %}
6393 
6394 instruct storeD0( memory mem, immD0 src) %{
6395   match(Set mem (StoreD mem src));
6396   ins_cost(MEMORY_REF_COST);
6397 
6398   format %{ "STX    $src,$mem" %}
6399   opcode(Assembler::stx_op3);
6400   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6401   ins_pipe(fstoreD_mem_zero);
6402 %}
6403 
6404 // Store Float
6405 instruct storeF( memory mem, regF src) %{
6406   match(Set mem (StoreF mem src));
6407   ins_cost(MEMORY_REF_COST);
6408 
6409   format %{ "STF    $src,$mem" %}
6410   opcode(Assembler::stf_op3);
6411   ins_encode(simple_form3_mem_reg( mem, src ) );
6412   ins_pipe(fstoreF_mem_reg);
6413 %}
6414 
6415 instruct storeF0( memory mem, immF0 src) %{
6416   match(Set mem (StoreF mem src));
6417   ins_cost(MEMORY_REF_COST);
6418 
6419   format %{ "STW    $src,$mem\t! storeF0" %}
6420   opcode(Assembler::stw_op3);
6421   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6422   ins_pipe(fstoreF_mem_zero);
6423 %}
6424 
6425 // Convert oop pointer into compressed form
6426 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6427   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6428   match(Set dst (EncodeP src));
6429   format %{ "encode_heap_oop $src, $dst" %}
6430   ins_encode %{
6431     __ encode_heap_oop($src$$Register, $dst$$Register);
6432   %}
6433   ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6434   ins_pipe(ialu_reg);
6435 %}
6436 
6437 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6438   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6439   match(Set dst (EncodeP src));
6440   format %{ "encode_heap_oop_not_null $src, $dst" %}
6441   ins_encode %{
6442     __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6443   %}
6444   ins_pipe(ialu_reg);
6445 %}
6446 
6447 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6448   predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6449             n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6450   match(Set dst (DecodeN src));
6451   format %{ "decode_heap_oop $src, $dst" %}
6452   ins_encode %{
6453     __ decode_heap_oop($src$$Register, $dst$$Register);
6454   %}
6455   ins_pipe(ialu_reg);
6456 %}
6457 
6458 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6459   predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6460             n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6461   match(Set dst (DecodeN src));
6462   format %{ "decode_heap_oop_not_null $src, $dst" %}
6463   ins_encode %{
6464     __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6465   %}
6466   ins_pipe(ialu_reg);
6467 %}
6468 
6469 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6470   match(Set dst (EncodePKlass src));
6471   format %{ "encode_klass_not_null $src, $dst" %}
6472   ins_encode %{
6473     __ encode_klass_not_null($src$$Register, $dst$$Register);
6474   %}
6475   ins_pipe(ialu_reg);
6476 %}
6477 
6478 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6479   match(Set dst (DecodeNKlass src));
6480   format %{ "decode_klass_not_null $src, $dst" %}
6481   ins_encode %{
6482     __ decode_klass_not_null($src$$Register, $dst$$Register);
6483   %}
6484   ins_pipe(ialu_reg);
6485 %}
6486 
6487 //----------MemBar Instructions-----------------------------------------------
6488 // Memory barrier flavors
6489 
6490 instruct membar_acquire() %{
6491   match(MemBarAcquire);
6492   match(LoadFence);
6493   ins_cost(4*MEMORY_REF_COST);
6494 
6495   size(0);
6496   format %{ "MEMBAR-acquire" %}
6497   ins_encode( enc_membar_acquire );
6498   ins_pipe(long_memory_op);
6499 %}
6500 
6501 instruct membar_acquire_lock() %{
6502   match(MemBarAcquireLock);
6503   ins_cost(0);
6504 
6505   size(0);
6506   format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6507   ins_encode( );
6508   ins_pipe(empty);
6509 %}
6510 
6511 instruct membar_release() %{
6512   match(MemBarRelease);
6513   match(StoreFence);
6514   ins_cost(4*MEMORY_REF_COST);
6515 
6516   size(0);
6517   format %{ "MEMBAR-release" %}
6518   ins_encode( enc_membar_release );
6519   ins_pipe(long_memory_op);
6520 %}
6521 
6522 instruct membar_release_lock() %{
6523   match(MemBarReleaseLock);
6524   ins_cost(0);
6525 
6526   size(0);
6527   format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6528   ins_encode( );
6529   ins_pipe(empty);
6530 %}
6531 
6532 instruct membar_volatile() %{
6533   match(MemBarVolatile);
6534   ins_cost(4*MEMORY_REF_COST);
6535 
6536   size(4);
6537   format %{ "MEMBAR-volatile" %}
6538   ins_encode( enc_membar_volatile );
6539   ins_pipe(long_memory_op);
6540 %}
6541 
6542 instruct unnecessary_membar_volatile() %{
6543   match(MemBarVolatile);
6544   predicate(Matcher::post_store_load_barrier(n));
6545   ins_cost(0);
6546 
6547   size(0);
6548   format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6549   ins_encode( );
6550   ins_pipe(empty);
6551 %}
6552 
6553 instruct membar_storestore() %{
6554   match(MemBarStoreStore);
6555   ins_cost(0);
6556 
6557   size(0);
6558   format %{ "!MEMBAR-storestore (empty encoding)" %}
6559   ins_encode( );
6560   ins_pipe(empty);
6561 %}
6562 
6563 //----------Register Move Instructions-----------------------------------------
6564 instruct roundDouble_nop(regD dst) %{
6565   match(Set dst (RoundDouble dst));
6566   ins_cost(0);
6567   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6568   ins_encode( );
6569   ins_pipe(empty);
6570 %}
6571 
6572 
6573 instruct roundFloat_nop(regF dst) %{
6574   match(Set dst (RoundFloat dst));
6575   ins_cost(0);
6576   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6577   ins_encode( );
6578   ins_pipe(empty);
6579 %}
6580 
6581 
6582 // Cast Index to Pointer for unsafe natives
6583 instruct castX2P(iRegX src, iRegP dst) %{
6584   match(Set dst (CastX2P src));
6585 
6586   format %{ "MOV    $src,$dst\t! IntX->Ptr" %}
6587   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6588   ins_pipe(ialu_reg);
6589 %}
6590 
6591 // Cast Pointer to Index for unsafe natives
6592 instruct castP2X(iRegP src, iRegX dst) %{
6593   match(Set dst (CastP2X src));
6594 
6595   format %{ "MOV    $src,$dst\t! Ptr->IntX" %}
6596   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6597   ins_pipe(ialu_reg);
6598 %}
6599 
6600 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6601   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6602   match(Set stkSlot src);   // chain rule
6603   ins_cost(MEMORY_REF_COST);
6604   format %{ "STDF   $src,$stkSlot\t!stk" %}
6605   opcode(Assembler::stdf_op3);
6606   ins_encode(simple_form3_mem_reg(stkSlot, src));
6607   ins_pipe(fstoreD_stk_reg);
6608 %}
6609 
6610 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6611   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6612   match(Set dst stkSlot);   // chain rule
6613   ins_cost(MEMORY_REF_COST);
6614   format %{ "LDDF   $stkSlot,$dst\t!stk" %}
6615   opcode(Assembler::lddf_op3);
6616   ins_encode(simple_form3_mem_reg(stkSlot, dst));
6617   ins_pipe(floadD_stk);
6618 %}
6619 
6620 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6621   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6622   match(Set stkSlot src);   // chain rule
6623   ins_cost(MEMORY_REF_COST);
6624   format %{ "STF   $src,$stkSlot\t!stk" %}
6625   opcode(Assembler::stf_op3);
6626   ins_encode(simple_form3_mem_reg(stkSlot, src));
6627   ins_pipe(fstoreF_stk_reg);
6628 %}
6629 
6630 //----------Conditional Move---------------------------------------------------
6631 // Conditional move
6632 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6633   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6634   ins_cost(150);
6635   format %{ "MOV$cmp $pcc,$src,$dst" %}
6636   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6637   ins_pipe(ialu_reg);
6638 %}
6639 
6640 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6641   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6642   ins_cost(140);
6643   format %{ "MOV$cmp $pcc,$src,$dst" %}
6644   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6645   ins_pipe(ialu_imm);
6646 %}
6647 
6648 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6649   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6650   ins_cost(150);
6651   size(4);
6652   format %{ "MOV$cmp  $icc,$src,$dst" %}
6653   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6654   ins_pipe(ialu_reg);
6655 %}
6656 
6657 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6658   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6659   ins_cost(140);
6660   size(4);
6661   format %{ "MOV$cmp  $icc,$src,$dst" %}
6662   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6663   ins_pipe(ialu_imm);
6664 %}
6665 
6666 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6667   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6668   ins_cost(150);
6669   size(4);
6670   format %{ "MOV$cmp  $icc,$src,$dst" %}
6671   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6672   ins_pipe(ialu_reg);
6673 %}
6674 
6675 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6676   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6677   ins_cost(140);
6678   size(4);
6679   format %{ "MOV$cmp  $icc,$src,$dst" %}
6680   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6681   ins_pipe(ialu_imm);
6682 %}
6683 
6684 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6685   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6686   ins_cost(150);
6687   size(4);
6688   format %{ "MOV$cmp $fcc,$src,$dst" %}
6689   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6690   ins_pipe(ialu_reg);
6691 %}
6692 
6693 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6694   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6695   ins_cost(140);
6696   size(4);
6697   format %{ "MOV$cmp $fcc,$src,$dst" %}
6698   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6699   ins_pipe(ialu_imm);
6700 %}
6701 
6702 // Conditional move for RegN. Only cmov(reg,reg).
6703 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6704   match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6705   ins_cost(150);
6706   format %{ "MOV$cmp $pcc,$src,$dst" %}
6707   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6708   ins_pipe(ialu_reg);
6709 %}
6710 
6711 // This instruction also works with CmpN so we don't need cmovNN_reg.
6712 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6713   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6714   ins_cost(150);
6715   size(4);
6716   format %{ "MOV$cmp  $icc,$src,$dst" %}
6717   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6718   ins_pipe(ialu_reg);
6719 %}
6720 
6721 // This instruction also works with CmpN so we don't need cmovNN_reg.
6722 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6723   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6724   ins_cost(150);
6725   size(4);
6726   format %{ "MOV$cmp  $icc,$src,$dst" %}
6727   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6728   ins_pipe(ialu_reg);
6729 %}
6730 
6731 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6732   match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6733   ins_cost(150);
6734   size(4);
6735   format %{ "MOV$cmp $fcc,$src,$dst" %}
6736   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6737   ins_pipe(ialu_reg);
6738 %}
6739 
6740 // Conditional move
6741 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6742   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6743   ins_cost(150);
6744   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6745   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6746   ins_pipe(ialu_reg);
6747 %}
6748 
6749 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6750   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6751   ins_cost(140);
6752   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6753   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6754   ins_pipe(ialu_imm);
6755 %}
6756 
6757 // This instruction also works with CmpN so we don't need cmovPN_reg.
6758 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6759   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6760   ins_cost(150);
6761 
6762   size(4);
6763   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6764   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6765   ins_pipe(ialu_reg);
6766 %}
6767 
6768 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6769   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6770   ins_cost(150);
6771 
6772   size(4);
6773   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6774   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6775   ins_pipe(ialu_reg);
6776 %}
6777 
6778 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6779   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6780   ins_cost(140);
6781 
6782   size(4);
6783   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6784   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6785   ins_pipe(ialu_imm);
6786 %}
6787 
6788 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6789   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6790   ins_cost(140);
6791 
6792   size(4);
6793   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6794   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6795   ins_pipe(ialu_imm);
6796 %}
6797 
6798 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6799   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6800   ins_cost(150);
6801   size(4);
6802   format %{ "MOV$cmp $fcc,$src,$dst" %}
6803   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6804   ins_pipe(ialu_imm);
6805 %}
6806 
6807 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6808   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6809   ins_cost(140);
6810   size(4);
6811   format %{ "MOV$cmp $fcc,$src,$dst" %}
6812   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6813   ins_pipe(ialu_imm);
6814 %}
6815 
6816 // Conditional move
6817 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6818   match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6819   ins_cost(150);
6820   opcode(0x101);
6821   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6822   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6823   ins_pipe(int_conditional_float_move);
6824 %}
6825 
6826 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6827   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6828   ins_cost(150);
6829 
6830   size(4);
6831   format %{ "FMOVS$cmp $icc,$src,$dst" %}
6832   opcode(0x101);
6833   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6834   ins_pipe(int_conditional_float_move);
6835 %}
6836 
6837 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6838   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6839   ins_cost(150);
6840 
6841   size(4);
6842   format %{ "FMOVS$cmp $icc,$src,$dst" %}
6843   opcode(0x101);
6844   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6845   ins_pipe(int_conditional_float_move);
6846 %}
6847 
6848 // Conditional move,
6849 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6850   match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6851   ins_cost(150);
6852   size(4);
6853   format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6854   opcode(0x1);
6855   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6856   ins_pipe(int_conditional_double_move);
6857 %}
6858 
6859 // Conditional move
6860 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6861   match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6862   ins_cost(150);
6863   size(4);
6864   opcode(0x102);
6865   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6866   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6867   ins_pipe(int_conditional_double_move);
6868 %}
6869 
6870 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6871   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6872   ins_cost(150);
6873 
6874   size(4);
6875   format %{ "FMOVD$cmp $icc,$src,$dst" %}
6876   opcode(0x102);
6877   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6878   ins_pipe(int_conditional_double_move);
6879 %}
6880 
6881 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6882   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6883   ins_cost(150);
6884 
6885   size(4);
6886   format %{ "FMOVD$cmp $icc,$src,$dst" %}
6887   opcode(0x102);
6888   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6889   ins_pipe(int_conditional_double_move);
6890 %}
6891 
6892 // Conditional move,
6893 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6894   match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6895   ins_cost(150);
6896   size(4);
6897   format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6898   opcode(0x2);
6899   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6900   ins_pipe(int_conditional_double_move);
6901 %}
6902 
6903 // Conditional move
6904 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6905   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6906   ins_cost(150);
6907   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6908   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6909   ins_pipe(ialu_reg);
6910 %}
6911 
6912 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6913   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6914   ins_cost(140);
6915   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6916   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6917   ins_pipe(ialu_imm);
6918 %}
6919 
6920 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6921   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6922   ins_cost(150);
6923 
6924   size(4);
6925   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
6926   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6927   ins_pipe(ialu_reg);
6928 %}
6929 
6930 
6931 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6932   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6933   ins_cost(150);
6934 
6935   size(4);
6936   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
6937   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6938   ins_pipe(ialu_reg);
6939 %}
6940 
6941 
6942 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6943   match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6944   ins_cost(150);
6945 
6946   size(4);
6947   format %{ "MOV$cmp  $fcc,$src,$dst\t! long" %}
6948   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6949   ins_pipe(ialu_reg);
6950 %}
6951 
6952 
6953 
6954 //----------OS and Locking Instructions----------------------------------------
6955 
6956 // This name is KNOWN by the ADLC and cannot be changed.
6957 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6958 // for this guy.
6959 instruct tlsLoadP(g2RegP dst) %{
6960   match(Set dst (ThreadLocal));
6961 
6962   size(0);
6963   ins_cost(0);
6964   format %{ "# TLS is in G2" %}
6965   ins_encode( /*empty encoding*/ );
6966   ins_pipe(ialu_none);
6967 %}
6968 
6969 instruct checkCastPP( iRegP dst ) %{
6970   match(Set dst (CheckCastPP dst));
6971 
6972   size(0);
6973   format %{ "# checkcastPP of $dst" %}
6974   ins_encode( /*empty encoding*/ );
6975   ins_pipe(empty);
6976 %}
6977 
6978 
6979 instruct castPP( iRegP dst ) %{
6980   match(Set dst (CastPP dst));
6981   format %{ "# castPP of $dst" %}
6982   ins_encode( /*empty encoding*/ );
6983   ins_pipe(empty);
6984 %}
6985 
6986 instruct castII( iRegI dst ) %{
6987   match(Set dst (CastII dst));
6988   format %{ "# castII of $dst" %}
6989   ins_encode( /*empty encoding*/ );
6990   ins_cost(0);
6991   ins_pipe(empty);
6992 %}
6993 
6994 //----------Arithmetic Instructions--------------------------------------------
6995 // Addition Instructions
6996 // Register Addition
6997 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6998   match(Set dst (AddI src1 src2));
6999 
7000   size(4);
7001   format %{ "ADD    $src1,$src2,$dst" %}
7002   ins_encode %{
7003     __ add($src1$$Register, $src2$$Register, $dst$$Register);
7004   %}
7005   ins_pipe(ialu_reg_reg);
7006 %}
7007 
7008 // Immediate Addition
7009 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7010   match(Set dst (AddI src1 src2));
7011 
7012   size(4);
7013   format %{ "ADD    $src1,$src2,$dst" %}
7014   opcode(Assembler::add_op3, Assembler::arith_op);
7015   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7016   ins_pipe(ialu_reg_imm);
7017 %}
7018 
7019 // Pointer Register Addition
7020 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7021   match(Set dst (AddP src1 src2));
7022 
7023   size(4);
7024   format %{ "ADD    $src1,$src2,$dst" %}
7025   opcode(Assembler::add_op3, Assembler::arith_op);
7026   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7027   ins_pipe(ialu_reg_reg);
7028 %}
7029 
7030 // Pointer Immediate Addition
7031 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7032   match(Set dst (AddP src1 src2));
7033 
7034   size(4);
7035   format %{ "ADD    $src1,$src2,$dst" %}
7036   opcode(Assembler::add_op3, Assembler::arith_op);
7037   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7038   ins_pipe(ialu_reg_imm);
7039 %}
7040 
7041 // Long Addition
7042 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7043   match(Set dst (AddL src1 src2));
7044 
7045   size(4);
7046   format %{ "ADD    $src1,$src2,$dst\t! long" %}
7047   opcode(Assembler::add_op3, Assembler::arith_op);
7048   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7049   ins_pipe(ialu_reg_reg);
7050 %}
7051 
7052 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7053   match(Set dst (AddL src1 con));
7054 
7055   size(4);
7056   format %{ "ADD    $src1,$con,$dst" %}
7057   opcode(Assembler::add_op3, Assembler::arith_op);
7058   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7059   ins_pipe(ialu_reg_imm);
7060 %}
7061 
7062 //----------Conditional_store--------------------------------------------------
7063 // Conditional-store of the updated heap-top.
7064 // Used during allocation of the shared heap.
7065 // Sets flags (EQ) on success.  Implemented with a CASA on Sparc.
7066 
7067 // LoadP-locked.  Same as a regular pointer load when used with a compare-swap
7068 instruct loadPLocked(iRegP dst, memory mem) %{
7069   match(Set dst (LoadPLocked mem));
7070   ins_cost(MEMORY_REF_COST);
7071 
7072 #ifndef _LP64
7073   format %{ "LDUW   $mem,$dst\t! ptr" %}
7074   opcode(Assembler::lduw_op3, 0, REGP_OP);
7075 #else
7076   format %{ "LDX    $mem,$dst\t! ptr" %}
7077   opcode(Assembler::ldx_op3, 0, REGP_OP);
7078 #endif
7079   ins_encode( form3_mem_reg( mem, dst ) );
7080   ins_pipe(iload_mem);
7081 %}
7082 
7083 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7084   match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7085   effect( KILL newval );
7086   format %{ "CASA   [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7087             "CMP    R_G3,$oldval\t\t! See if we made progress"  %}
7088   ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7089   ins_pipe( long_memory_op );
7090 %}
7091 
7092 // Conditional-store of an int value.
7093 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7094   match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7095   effect( KILL newval );
7096   format %{ "CASA   [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7097             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7098   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7099   ins_pipe( long_memory_op );
7100 %}
7101 
7102 // Conditional-store of a long value.
7103 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7104   match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7105   effect( KILL newval );
7106   format %{ "CASXA  [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7107             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7108   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7109   ins_pipe( long_memory_op );
7110 %}
7111 
7112 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7113 
7114 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7115   predicate(VM_Version::supports_cx8());
7116   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7117   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7118   format %{
7119             "MOV    $newval,O7\n\t"
7120             "CASXA  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7121             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7122             "MOV    1,$res\n\t"
7123             "MOVne  xcc,R_G0,$res"
7124   %}
7125   ins_encode( enc_casx(mem_ptr, oldval, newval),
7126               enc_lflags_ne_to_boolean(res) );
7127   ins_pipe( long_memory_op );
7128 %}
7129 
7130 
7131 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7132   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7133   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7134   format %{
7135             "MOV    $newval,O7\n\t"
7136             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7137             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7138             "MOV    1,$res\n\t"
7139             "MOVne  icc,R_G0,$res"
7140   %}
7141   ins_encode( enc_casi(mem_ptr, oldval, newval),
7142               enc_iflags_ne_to_boolean(res) );
7143   ins_pipe( long_memory_op );
7144 %}
7145 
7146 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7147 #ifdef _LP64
7148   predicate(VM_Version::supports_cx8());
7149 #endif
7150   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7151   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7152   format %{
7153             "MOV    $newval,O7\n\t"
7154             "CASA_PTR  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7155             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7156             "MOV    1,$res\n\t"
7157             "MOVne  xcc,R_G0,$res"
7158   %}
7159 #ifdef _LP64
7160   ins_encode( enc_casx(mem_ptr, oldval, newval),
7161               enc_lflags_ne_to_boolean(res) );
7162 #else
7163   ins_encode( enc_casi(mem_ptr, oldval, newval),
7164               enc_iflags_ne_to_boolean(res) );
7165 #endif
7166   ins_pipe( long_memory_op );
7167 %}
7168 
7169 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7170   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7171   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7172   format %{
7173             "MOV    $newval,O7\n\t"
7174             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7175             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7176             "MOV    1,$res\n\t"
7177             "MOVne  icc,R_G0,$res"
7178   %}
7179   ins_encode( enc_casi(mem_ptr, oldval, newval),
7180               enc_iflags_ne_to_boolean(res) );
7181   ins_pipe( long_memory_op );
7182 %}
7183 
7184 instruct xchgI( memory mem, iRegI newval) %{
7185   match(Set newval (GetAndSetI mem newval));
7186   format %{ "SWAP  [$mem],$newval" %}
7187   size(4);
7188   ins_encode %{
7189     __ swap($mem$$Address, $newval$$Register);
7190   %}
7191   ins_pipe( long_memory_op );
7192 %}
7193 
7194 #ifndef _LP64
7195 instruct xchgP( memory mem, iRegP newval) %{
7196   match(Set newval (GetAndSetP mem newval));
7197   format %{ "SWAP  [$mem],$newval" %}
7198   size(4);
7199   ins_encode %{
7200     __ swap($mem$$Address, $newval$$Register);
7201   %}
7202   ins_pipe( long_memory_op );
7203 %}
7204 #endif
7205 
7206 instruct xchgN( memory mem, iRegN newval) %{
7207   match(Set newval (GetAndSetN mem newval));
7208   format %{ "SWAP  [$mem],$newval" %}
7209   size(4);
7210   ins_encode %{
7211     __ swap($mem$$Address, $newval$$Register);
7212   %}
7213   ins_pipe( long_memory_op );
7214 %}
7215 
7216 //---------------------
7217 // Subtraction Instructions
7218 // Register Subtraction
7219 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7220   match(Set dst (SubI src1 src2));
7221 
7222   size(4);
7223   format %{ "SUB    $src1,$src2,$dst" %}
7224   opcode(Assembler::sub_op3, Assembler::arith_op);
7225   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7226   ins_pipe(ialu_reg_reg);
7227 %}
7228 
7229 // Immediate Subtraction
7230 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7231   match(Set dst (SubI src1 src2));
7232 
7233   size(4);
7234   format %{ "SUB    $src1,$src2,$dst" %}
7235   opcode(Assembler::sub_op3, Assembler::arith_op);
7236   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7237   ins_pipe(ialu_reg_imm);
7238 %}
7239 
7240 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7241   match(Set dst (SubI zero src2));
7242 
7243   size(4);
7244   format %{ "NEG    $src2,$dst" %}
7245   opcode(Assembler::sub_op3, Assembler::arith_op);
7246   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7247   ins_pipe(ialu_zero_reg);
7248 %}
7249 
7250 // Long subtraction
7251 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7252   match(Set dst (SubL src1 src2));
7253 
7254   size(4);
7255   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7256   opcode(Assembler::sub_op3, Assembler::arith_op);
7257   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7258   ins_pipe(ialu_reg_reg);
7259 %}
7260 
7261 // Immediate Subtraction
7262 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7263   match(Set dst (SubL src1 con));
7264 
7265   size(4);
7266   format %{ "SUB    $src1,$con,$dst\t! long" %}
7267   opcode(Assembler::sub_op3, Assembler::arith_op);
7268   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7269   ins_pipe(ialu_reg_imm);
7270 %}
7271 
7272 // Long negation
7273 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7274   match(Set dst (SubL zero src2));
7275 
7276   size(4);
7277   format %{ "NEG    $src2,$dst\t! long" %}
7278   opcode(Assembler::sub_op3, Assembler::arith_op);
7279   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7280   ins_pipe(ialu_zero_reg);
7281 %}
7282 
7283 // Multiplication Instructions
7284 // Integer Multiplication
7285 // Register Multiplication
7286 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7287   match(Set dst (MulI src1 src2));
7288 
7289   size(4);
7290   format %{ "MULX   $src1,$src2,$dst" %}
7291   opcode(Assembler::mulx_op3, Assembler::arith_op);
7292   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7293   ins_pipe(imul_reg_reg);
7294 %}
7295 
7296 // Immediate Multiplication
7297 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7298   match(Set dst (MulI src1 src2));
7299 
7300   size(4);
7301   format %{ "MULX   $src1,$src2,$dst" %}
7302   opcode(Assembler::mulx_op3, Assembler::arith_op);
7303   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7304   ins_pipe(imul_reg_imm);
7305 %}
7306 
7307 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7308   match(Set dst (MulL src1 src2));
7309   ins_cost(DEFAULT_COST * 5);
7310   size(4);
7311   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7312   opcode(Assembler::mulx_op3, Assembler::arith_op);
7313   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7314   ins_pipe(mulL_reg_reg);
7315 %}
7316 
7317 // Immediate Multiplication
7318 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7319   match(Set dst (MulL src1 src2));
7320   ins_cost(DEFAULT_COST * 5);
7321   size(4);
7322   format %{ "MULX   $src1,$src2,$dst" %}
7323   opcode(Assembler::mulx_op3, Assembler::arith_op);
7324   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7325   ins_pipe(mulL_reg_imm);
7326 %}
7327 
7328 // Integer Division
7329 // Register Division
7330 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7331   match(Set dst (DivI src1 src2));
7332   ins_cost((2+71)*DEFAULT_COST);
7333 
7334   format %{ "SRA     $src2,0,$src2\n\t"
7335             "SRA     $src1,0,$src1\n\t"
7336             "SDIVX   $src1,$src2,$dst" %}
7337   ins_encode( idiv_reg( src1, src2, dst ) );
7338   ins_pipe(sdiv_reg_reg);
7339 %}
7340 
7341 // Immediate Division
7342 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7343   match(Set dst (DivI src1 src2));
7344   ins_cost((2+71)*DEFAULT_COST);
7345 
7346   format %{ "SRA     $src1,0,$src1\n\t"
7347             "SDIVX   $src1,$src2,$dst" %}
7348   ins_encode( idiv_imm( src1, src2, dst ) );
7349   ins_pipe(sdiv_reg_imm);
7350 %}
7351 
7352 //----------Div-By-10-Expansion------------------------------------------------
7353 // Extract hi bits of a 32x32->64 bit multiply.
7354 // Expand rule only, not matched
7355 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7356   effect( DEF dst, USE src1, USE src2 );
7357   format %{ "MULX   $src1,$src2,$dst\t! Used in div-by-10\n\t"
7358             "SRLX   $dst,#32,$dst\t\t! Extract only hi word of result" %}
7359   ins_encode( enc_mul_hi(dst,src1,src2));
7360   ins_pipe(sdiv_reg_reg);
7361 %}
7362 
7363 // Magic constant, reciprocal of 10
7364 instruct loadConI_x66666667(iRegIsafe dst) %{
7365   effect( DEF dst );
7366 
7367   size(8);
7368   format %{ "SET    0x66666667,$dst\t! Used in div-by-10" %}
7369   ins_encode( Set32(0x66666667, dst) );
7370   ins_pipe(ialu_hi_lo_reg);
7371 %}
7372 
7373 // Register Shift Right Arithmetic Long by 32-63
7374 instruct sra_31( iRegI dst, iRegI src ) %{
7375   effect( DEF dst, USE src );
7376   format %{ "SRA    $src,31,$dst\t! Used in div-by-10" %}
7377   ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7378   ins_pipe(ialu_reg_reg);
7379 %}
7380 
7381 // Arithmetic Shift Right by 8-bit immediate
7382 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7383   effect( DEF dst, USE src );
7384   format %{ "SRA    $src,2,$dst\t! Used in div-by-10" %}
7385   opcode(Assembler::sra_op3, Assembler::arith_op);
7386   ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7387   ins_pipe(ialu_reg_imm);
7388 %}
7389 
7390 // Integer DIV with 10
7391 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7392   match(Set dst (DivI src div));
7393   ins_cost((6+6)*DEFAULT_COST);
7394   expand %{
7395     iRegIsafe tmp1;               // Killed temps;
7396     iRegIsafe tmp2;               // Killed temps;
7397     iRegI tmp3;                   // Killed temps;
7398     iRegI tmp4;                   // Killed temps;
7399     loadConI_x66666667( tmp1 );   // SET  0x66666667 -> tmp1
7400     mul_hi( tmp2, src, tmp1 );    // MUL  hibits(src * tmp1) -> tmp2
7401     sra_31( tmp3, src );          // SRA  src,31 -> tmp3
7402     sra_reg_2( tmp4, tmp2 );      // SRA  tmp2,2 -> tmp4
7403     subI_reg_reg( dst,tmp4,tmp3); // SUB  tmp4 - tmp3 -> dst
7404   %}
7405 %}
7406 
7407 // Register Long Division
7408 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7409   match(Set dst (DivL src1 src2));
7410   ins_cost(DEFAULT_COST*71);
7411   size(4);
7412   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7413   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7414   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7415   ins_pipe(divL_reg_reg);
7416 %}
7417 
7418 // Register Long Division
7419 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7420   match(Set dst (DivL src1 src2));
7421   ins_cost(DEFAULT_COST*71);
7422   size(4);
7423   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7424   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7425   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7426   ins_pipe(divL_reg_imm);
7427 %}
7428 
7429 // Integer Remainder
7430 // Register Remainder
7431 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7432   match(Set dst (ModI src1 src2));
7433   effect( KILL ccr, KILL temp);
7434 
7435   format %{ "SREM   $src1,$src2,$dst" %}
7436   ins_encode( irem_reg(src1, src2, dst, temp) );
7437   ins_pipe(sdiv_reg_reg);
7438 %}
7439 
7440 // Immediate Remainder
7441 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7442   match(Set dst (ModI src1 src2));
7443   effect( KILL ccr, KILL temp);
7444 
7445   format %{ "SREM   $src1,$src2,$dst" %}
7446   ins_encode( irem_imm(src1, src2, dst, temp) );
7447   ins_pipe(sdiv_reg_imm);
7448 %}
7449 
7450 // Register Long Remainder
7451 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7452   effect(DEF dst, USE src1, USE src2);
7453   size(4);
7454   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7455   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7456   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7457   ins_pipe(divL_reg_reg);
7458 %}
7459 
7460 // Register Long Division
7461 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7462   effect(DEF dst, USE src1, USE src2);
7463   size(4);
7464   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7465   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7466   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7467   ins_pipe(divL_reg_imm);
7468 %}
7469 
7470 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7471   effect(DEF dst, USE src1, USE src2);
7472   size(4);
7473   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7474   opcode(Assembler::mulx_op3, Assembler::arith_op);
7475   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7476   ins_pipe(mulL_reg_reg);
7477 %}
7478 
7479 // Immediate Multiplication
7480 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7481   effect(DEF dst, USE src1, USE src2);
7482   size(4);
7483   format %{ "MULX   $src1,$src2,$dst" %}
7484   opcode(Assembler::mulx_op3, Assembler::arith_op);
7485   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7486   ins_pipe(mulL_reg_imm);
7487 %}
7488 
7489 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7490   effect(DEF dst, USE src1, USE src2);
7491   size(4);
7492   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7493   opcode(Assembler::sub_op3, Assembler::arith_op);
7494   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7495   ins_pipe(ialu_reg_reg);
7496 %}
7497 
7498 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7499   effect(DEF dst, USE src1, USE src2);
7500   size(4);
7501   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7502   opcode(Assembler::sub_op3, Assembler::arith_op);
7503   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7504   ins_pipe(ialu_reg_reg);
7505 %}
7506 
7507 // Register Long Remainder
7508 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7509   match(Set dst (ModL src1 src2));
7510   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7511   expand %{
7512     iRegL tmp1;
7513     iRegL tmp2;
7514     divL_reg_reg_1(tmp1, src1, src2);
7515     mulL_reg_reg_1(tmp2, tmp1, src2);
7516     subL_reg_reg_1(dst,  src1, tmp2);
7517   %}
7518 %}
7519 
7520 // Register Long Remainder
7521 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7522   match(Set dst (ModL src1 src2));
7523   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7524   expand %{
7525     iRegL tmp1;
7526     iRegL tmp2;
7527     divL_reg_imm13_1(tmp1, src1, src2);
7528     mulL_reg_imm13_1(tmp2, tmp1, src2);
7529     subL_reg_reg_2  (dst,  src1, tmp2);
7530   %}
7531 %}
7532 
7533 // Integer Shift Instructions
7534 // Register Shift Left
7535 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7536   match(Set dst (LShiftI src1 src2));
7537 
7538   size(4);
7539   format %{ "SLL    $src1,$src2,$dst" %}
7540   opcode(Assembler::sll_op3, Assembler::arith_op);
7541   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7542   ins_pipe(ialu_reg_reg);
7543 %}
7544 
7545 // Register Shift Left Immediate
7546 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7547   match(Set dst (LShiftI src1 src2));
7548 
7549   size(4);
7550   format %{ "SLL    $src1,$src2,$dst" %}
7551   opcode(Assembler::sll_op3, Assembler::arith_op);
7552   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7553   ins_pipe(ialu_reg_imm);
7554 %}
7555 
7556 // Register Shift Left
7557 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7558   match(Set dst (LShiftL src1 src2));
7559 
7560   size(4);
7561   format %{ "SLLX   $src1,$src2,$dst" %}
7562   opcode(Assembler::sllx_op3, Assembler::arith_op);
7563   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7564   ins_pipe(ialu_reg_reg);
7565 %}
7566 
7567 // Register Shift Left Immediate
7568 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7569   match(Set dst (LShiftL src1 src2));
7570 
7571   size(4);
7572   format %{ "SLLX   $src1,$src2,$dst" %}
7573   opcode(Assembler::sllx_op3, Assembler::arith_op);
7574   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7575   ins_pipe(ialu_reg_imm);
7576 %}
7577 
7578 // Register Arithmetic Shift Right
7579 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7580   match(Set dst (RShiftI src1 src2));
7581   size(4);
7582   format %{ "SRA    $src1,$src2,$dst" %}
7583   opcode(Assembler::sra_op3, Assembler::arith_op);
7584   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7585   ins_pipe(ialu_reg_reg);
7586 %}
7587 
7588 // Register Arithmetic Shift Right Immediate
7589 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7590   match(Set dst (RShiftI src1 src2));
7591 
7592   size(4);
7593   format %{ "SRA    $src1,$src2,$dst" %}
7594   opcode(Assembler::sra_op3, Assembler::arith_op);
7595   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7596   ins_pipe(ialu_reg_imm);
7597 %}
7598 
7599 // Register Shift Right Arithmatic Long
7600 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7601   match(Set dst (RShiftL src1 src2));
7602 
7603   size(4);
7604   format %{ "SRAX   $src1,$src2,$dst" %}
7605   opcode(Assembler::srax_op3, Assembler::arith_op);
7606   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7607   ins_pipe(ialu_reg_reg);
7608 %}
7609 
7610 // Register Shift Left Immediate
7611 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7612   match(Set dst (RShiftL src1 src2));
7613 
7614   size(4);
7615   format %{ "SRAX   $src1,$src2,$dst" %}
7616   opcode(Assembler::srax_op3, Assembler::arith_op);
7617   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7618   ins_pipe(ialu_reg_imm);
7619 %}
7620 
7621 // Register Shift Right
7622 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7623   match(Set dst (URShiftI src1 src2));
7624 
7625   size(4);
7626   format %{ "SRL    $src1,$src2,$dst" %}
7627   opcode(Assembler::srl_op3, Assembler::arith_op);
7628   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7629   ins_pipe(ialu_reg_reg);
7630 %}
7631 
7632 // Register Shift Right Immediate
7633 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7634   match(Set dst (URShiftI src1 src2));
7635 
7636   size(4);
7637   format %{ "SRL    $src1,$src2,$dst" %}
7638   opcode(Assembler::srl_op3, Assembler::arith_op);
7639   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7640   ins_pipe(ialu_reg_imm);
7641 %}
7642 
7643 // Register Shift Right
7644 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7645   match(Set dst (URShiftL src1 src2));
7646 
7647   size(4);
7648   format %{ "SRLX   $src1,$src2,$dst" %}
7649   opcode(Assembler::srlx_op3, Assembler::arith_op);
7650   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7651   ins_pipe(ialu_reg_reg);
7652 %}
7653 
7654 // Register Shift Right Immediate
7655 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7656   match(Set dst (URShiftL src1 src2));
7657 
7658   size(4);
7659   format %{ "SRLX   $src1,$src2,$dst" %}
7660   opcode(Assembler::srlx_op3, Assembler::arith_op);
7661   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7662   ins_pipe(ialu_reg_imm);
7663 %}
7664 
7665 // Register Shift Right Immediate with a CastP2X
7666 #ifdef _LP64
7667 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7668   match(Set dst (URShiftL (CastP2X src1) src2));
7669   size(4);
7670   format %{ "SRLX   $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7671   opcode(Assembler::srlx_op3, Assembler::arith_op);
7672   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7673   ins_pipe(ialu_reg_imm);
7674 %}
7675 #else
7676 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7677   match(Set dst (URShiftI (CastP2X src1) src2));
7678   size(4);
7679   format %{ "SRL    $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7680   opcode(Assembler::srl_op3, Assembler::arith_op);
7681   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7682   ins_pipe(ialu_reg_imm);
7683 %}
7684 #endif
7685 
7686 
7687 //----------Floating Point Arithmetic Instructions-----------------------------
7688 
7689 //  Add float single precision
7690 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7691   match(Set dst (AddF src1 src2));
7692 
7693   size(4);
7694   format %{ "FADDS  $src1,$src2,$dst" %}
7695   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7696   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7697   ins_pipe(faddF_reg_reg);
7698 %}
7699 
7700 //  Add float double precision
7701 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7702   match(Set dst (AddD src1 src2));
7703 
7704   size(4);
7705   format %{ "FADDD  $src1,$src2,$dst" %}
7706   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7707   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7708   ins_pipe(faddD_reg_reg);
7709 %}
7710 
7711 //  Sub float single precision
7712 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7713   match(Set dst (SubF src1 src2));
7714 
7715   size(4);
7716   format %{ "FSUBS  $src1,$src2,$dst" %}
7717   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7718   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7719   ins_pipe(faddF_reg_reg);
7720 %}
7721 
7722 //  Sub float double precision
7723 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7724   match(Set dst (SubD src1 src2));
7725 
7726   size(4);
7727   format %{ "FSUBD  $src1,$src2,$dst" %}
7728   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7729   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7730   ins_pipe(faddD_reg_reg);
7731 %}
7732 
7733 //  Mul float single precision
7734 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7735   match(Set dst (MulF src1 src2));
7736 
7737   size(4);
7738   format %{ "FMULS  $src1,$src2,$dst" %}
7739   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7740   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7741   ins_pipe(fmulF_reg_reg);
7742 %}
7743 
7744 //  Mul float double precision
7745 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7746   match(Set dst (MulD src1 src2));
7747 
7748   size(4);
7749   format %{ "FMULD  $src1,$src2,$dst" %}
7750   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7751   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7752   ins_pipe(fmulD_reg_reg);
7753 %}
7754 
7755 //  Div float single precision
7756 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7757   match(Set dst (DivF src1 src2));
7758 
7759   size(4);
7760   format %{ "FDIVS  $src1,$src2,$dst" %}
7761   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7762   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7763   ins_pipe(fdivF_reg_reg);
7764 %}
7765 
7766 //  Div float double precision
7767 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7768   match(Set dst (DivD src1 src2));
7769 
7770   size(4);
7771   format %{ "FDIVD  $src1,$src2,$dst" %}
7772   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7773   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7774   ins_pipe(fdivD_reg_reg);
7775 %}
7776 
7777 //  Absolute float double precision
7778 instruct absD_reg(regD dst, regD src) %{
7779   match(Set dst (AbsD src));
7780 
7781   format %{ "FABSd  $src,$dst" %}
7782   ins_encode(fabsd(dst, src));
7783   ins_pipe(faddD_reg);
7784 %}
7785 
7786 //  Absolute float single precision
7787 instruct absF_reg(regF dst, regF src) %{
7788   match(Set dst (AbsF src));
7789 
7790   format %{ "FABSs  $src,$dst" %}
7791   ins_encode(fabss(dst, src));
7792   ins_pipe(faddF_reg);
7793 %}
7794 
7795 instruct negF_reg(regF dst, regF src) %{
7796   match(Set dst (NegF src));
7797 
7798   size(4);
7799   format %{ "FNEGs  $src,$dst" %}
7800   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7801   ins_encode(form3_opf_rs2F_rdF(src, dst));
7802   ins_pipe(faddF_reg);
7803 %}
7804 
7805 instruct negD_reg(regD dst, regD src) %{
7806   match(Set dst (NegD src));
7807 
7808   format %{ "FNEGd  $src,$dst" %}
7809   ins_encode(fnegd(dst, src));
7810   ins_pipe(faddD_reg);
7811 %}
7812 
7813 //  Sqrt float double precision
7814 instruct sqrtF_reg_reg(regF dst, regF src) %{
7815   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7816 
7817   size(4);
7818   format %{ "FSQRTS $src,$dst" %}
7819   ins_encode(fsqrts(dst, src));
7820   ins_pipe(fdivF_reg_reg);
7821 %}
7822 
7823 //  Sqrt float double precision
7824 instruct sqrtD_reg_reg(regD dst, regD src) %{
7825   match(Set dst (SqrtD src));
7826 
7827   size(4);
7828   format %{ "FSQRTD $src,$dst" %}
7829   ins_encode(fsqrtd(dst, src));
7830   ins_pipe(fdivD_reg_reg);
7831 %}
7832 
7833 //----------Logical Instructions-----------------------------------------------
7834 // And Instructions
7835 // Register And
7836 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7837   match(Set dst (AndI src1 src2));
7838 
7839   size(4);
7840   format %{ "AND    $src1,$src2,$dst" %}
7841   opcode(Assembler::and_op3, Assembler::arith_op);
7842   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7843   ins_pipe(ialu_reg_reg);
7844 %}
7845 
7846 // Immediate And
7847 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7848   match(Set dst (AndI src1 src2));
7849 
7850   size(4);
7851   format %{ "AND    $src1,$src2,$dst" %}
7852   opcode(Assembler::and_op3, Assembler::arith_op);
7853   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7854   ins_pipe(ialu_reg_imm);
7855 %}
7856 
7857 // Register And Long
7858 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7859   match(Set dst (AndL src1 src2));
7860 
7861   ins_cost(DEFAULT_COST);
7862   size(4);
7863   format %{ "AND    $src1,$src2,$dst\t! long" %}
7864   opcode(Assembler::and_op3, Assembler::arith_op);
7865   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7866   ins_pipe(ialu_reg_reg);
7867 %}
7868 
7869 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7870   match(Set dst (AndL src1 con));
7871 
7872   ins_cost(DEFAULT_COST);
7873   size(4);
7874   format %{ "AND    $src1,$con,$dst\t! long" %}
7875   opcode(Assembler::and_op3, Assembler::arith_op);
7876   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7877   ins_pipe(ialu_reg_imm);
7878 %}
7879 
7880 // Or Instructions
7881 // Register Or
7882 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7883   match(Set dst (OrI src1 src2));
7884 
7885   size(4);
7886   format %{ "OR     $src1,$src2,$dst" %}
7887   opcode(Assembler::or_op3, Assembler::arith_op);
7888   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7889   ins_pipe(ialu_reg_reg);
7890 %}
7891 
7892 // Immediate Or
7893 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7894   match(Set dst (OrI src1 src2));
7895 
7896   size(4);
7897   format %{ "OR     $src1,$src2,$dst" %}
7898   opcode(Assembler::or_op3, Assembler::arith_op);
7899   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7900   ins_pipe(ialu_reg_imm);
7901 %}
7902 
7903 // Register Or Long
7904 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7905   match(Set dst (OrL src1 src2));
7906 
7907   ins_cost(DEFAULT_COST);
7908   size(4);
7909   format %{ "OR     $src1,$src2,$dst\t! long" %}
7910   opcode(Assembler::or_op3, Assembler::arith_op);
7911   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7912   ins_pipe(ialu_reg_reg);
7913 %}
7914 
7915 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7916   match(Set dst (OrL src1 con));
7917   ins_cost(DEFAULT_COST*2);
7918 
7919   ins_cost(DEFAULT_COST);
7920   size(4);
7921   format %{ "OR     $src1,$con,$dst\t! long" %}
7922   opcode(Assembler::or_op3, Assembler::arith_op);
7923   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7924   ins_pipe(ialu_reg_imm);
7925 %}
7926 
7927 #ifndef _LP64
7928 
7929 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7930 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7931   match(Set dst (OrI src1 (CastP2X src2)));
7932 
7933   size(4);
7934   format %{ "OR     $src1,$src2,$dst" %}
7935   opcode(Assembler::or_op3, Assembler::arith_op);
7936   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7937   ins_pipe(ialu_reg_reg);
7938 %}
7939 
7940 #else
7941 
7942 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7943   match(Set dst (OrL src1 (CastP2X src2)));
7944 
7945   ins_cost(DEFAULT_COST);
7946   size(4);
7947   format %{ "OR     $src1,$src2,$dst\t! long" %}
7948   opcode(Assembler::or_op3, Assembler::arith_op);
7949   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7950   ins_pipe(ialu_reg_reg);
7951 %}
7952 
7953 #endif
7954 
7955 // Xor Instructions
7956 // Register Xor
7957 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7958   match(Set dst (XorI src1 src2));
7959 
7960   size(4);
7961   format %{ "XOR    $src1,$src2,$dst" %}
7962   opcode(Assembler::xor_op3, Assembler::arith_op);
7963   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7964   ins_pipe(ialu_reg_reg);
7965 %}
7966 
7967 // Immediate Xor
7968 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7969   match(Set dst (XorI src1 src2));
7970 
7971   size(4);
7972   format %{ "XOR    $src1,$src2,$dst" %}
7973   opcode(Assembler::xor_op3, Assembler::arith_op);
7974   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7975   ins_pipe(ialu_reg_imm);
7976 %}
7977 
7978 // Register Xor Long
7979 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7980   match(Set dst (XorL src1 src2));
7981 
7982   ins_cost(DEFAULT_COST);
7983   size(4);
7984   format %{ "XOR    $src1,$src2,$dst\t! long" %}
7985   opcode(Assembler::xor_op3, Assembler::arith_op);
7986   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7987   ins_pipe(ialu_reg_reg);
7988 %}
7989 
7990 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7991   match(Set dst (XorL src1 con));
7992 
7993   ins_cost(DEFAULT_COST);
7994   size(4);
7995   format %{ "XOR    $src1,$con,$dst\t! long" %}
7996   opcode(Assembler::xor_op3, Assembler::arith_op);
7997   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7998   ins_pipe(ialu_reg_imm);
7999 %}
8000 
8001 //----------Convert to Boolean-------------------------------------------------
8002 // Nice hack for 32-bit tests but doesn't work for
8003 // 64-bit pointers.
8004 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8005   match(Set dst (Conv2B src));
8006   effect( KILL ccr );
8007   ins_cost(DEFAULT_COST*2);
8008   format %{ "CMP    R_G0,$src\n\t"
8009             "ADDX   R_G0,0,$dst" %}
8010   ins_encode( enc_to_bool( src, dst ) );
8011   ins_pipe(ialu_reg_ialu);
8012 %}
8013 
8014 #ifndef _LP64
8015 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8016   match(Set dst (Conv2B src));
8017   effect( KILL ccr );
8018   ins_cost(DEFAULT_COST*2);
8019   format %{ "CMP    R_G0,$src\n\t"
8020             "ADDX   R_G0,0,$dst" %}
8021   ins_encode( enc_to_bool( src, dst ) );
8022   ins_pipe(ialu_reg_ialu);
8023 %}
8024 #else
8025 instruct convP2B( iRegI dst, iRegP src ) %{
8026   match(Set dst (Conv2B src));
8027   ins_cost(DEFAULT_COST*2);
8028   format %{ "MOV    $src,$dst\n\t"
8029             "MOVRNZ $src,1,$dst" %}
8030   ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8031   ins_pipe(ialu_clr_and_mover);
8032 %}
8033 #endif
8034 
8035 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8036   match(Set dst (CmpLTMask src zero));
8037   effect(KILL ccr);
8038   size(4);
8039   format %{ "SRA    $src,#31,$dst\t# cmpLTMask0" %}
8040   ins_encode %{
8041     __ sra($src$$Register, 31, $dst$$Register);
8042   %}
8043   ins_pipe(ialu_reg_imm);
8044 %}
8045 
8046 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8047   match(Set dst (CmpLTMask p q));
8048   effect( KILL ccr );
8049   ins_cost(DEFAULT_COST*4);
8050   format %{ "CMP    $p,$q\n\t"
8051             "MOV    #0,$dst\n\t"
8052             "BLT,a  .+8\n\t"
8053             "MOV    #-1,$dst" %}
8054   ins_encode( enc_ltmask(p,q,dst) );
8055   ins_pipe(ialu_reg_reg_ialu);
8056 %}
8057 
8058 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8059   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8060   effect(KILL ccr, TEMP tmp);
8061   ins_cost(DEFAULT_COST*3);
8062 
8063   format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
8064             "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
8065             "MOVlt  $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8066   ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8067   ins_pipe(cadd_cmpltmask);
8068 %}
8069 
8070 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8071   match(Set p (AndI (CmpLTMask p q) y));
8072   effect(KILL ccr);
8073   ins_cost(DEFAULT_COST*3);
8074 
8075   format %{ "CMP  $p,$q\n\t"
8076             "MOV  $y,$p\n\t"
8077             "MOVge G0,$p" %}
8078   ins_encode %{
8079     __ cmp($p$$Register, $q$$Register);
8080     __ mov($y$$Register, $p$$Register);
8081     __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8082   %}
8083   ins_pipe(ialu_reg_reg_ialu);
8084 %}
8085 
8086 //-----------------------------------------------------------------
8087 // Direct raw moves between float and general registers using VIS3.
8088 
8089 //  ins_pipe(faddF_reg);
8090 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8091   predicate(UseVIS >= 3);
8092   match(Set dst (MoveF2I src));
8093 
8094   format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8095   ins_encode %{
8096     __ movstouw($src$$FloatRegister, $dst$$Register);
8097   %}
8098   ins_pipe(ialu_reg_reg);
8099 %}
8100 
8101 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8102   predicate(UseVIS >= 3);
8103   match(Set dst (MoveI2F src));
8104 
8105   format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8106   ins_encode %{
8107     __ movwtos($src$$Register, $dst$$FloatRegister);
8108   %}
8109   ins_pipe(ialu_reg_reg);
8110 %}
8111 
8112 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8113   predicate(UseVIS >= 3);
8114   match(Set dst (MoveD2L src));
8115 
8116   format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8117   ins_encode %{
8118     __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8119   %}
8120   ins_pipe(ialu_reg_reg);
8121 %}
8122 
8123 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8124   predicate(UseVIS >= 3);
8125   match(Set dst (MoveL2D src));
8126 
8127   format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8128   ins_encode %{
8129     __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8130   %}
8131   ins_pipe(ialu_reg_reg);
8132 %}
8133 
8134 
8135 // Raw moves between float and general registers using stack.
8136 
8137 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8138   match(Set dst (MoveF2I src));
8139   effect(DEF dst, USE src);
8140   ins_cost(MEMORY_REF_COST);
8141 
8142   format %{ "LDUW   $src,$dst\t! MoveF2I" %}
8143   opcode(Assembler::lduw_op3);
8144   ins_encode(simple_form3_mem_reg( src, dst ) );
8145   ins_pipe(iload_mem);
8146 %}
8147 
8148 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8149   match(Set dst (MoveI2F src));
8150   effect(DEF dst, USE src);
8151   ins_cost(MEMORY_REF_COST);
8152 
8153   format %{ "LDF    $src,$dst\t! MoveI2F" %}
8154   opcode(Assembler::ldf_op3);
8155   ins_encode(simple_form3_mem_reg(src, dst));
8156   ins_pipe(floadF_stk);
8157 %}
8158 
8159 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8160   match(Set dst (MoveD2L src));
8161   effect(DEF dst, USE src);
8162   ins_cost(MEMORY_REF_COST);
8163 
8164   format %{ "LDX    $src,$dst\t! MoveD2L" %}
8165   opcode(Assembler::ldx_op3);
8166   ins_encode(simple_form3_mem_reg( src, dst ) );
8167   ins_pipe(iload_mem);
8168 %}
8169 
8170 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8171   match(Set dst (MoveL2D src));
8172   effect(DEF dst, USE src);
8173   ins_cost(MEMORY_REF_COST);
8174 
8175   format %{ "LDDF   $src,$dst\t! MoveL2D" %}
8176   opcode(Assembler::lddf_op3);
8177   ins_encode(simple_form3_mem_reg(src, dst));
8178   ins_pipe(floadD_stk);
8179 %}
8180 
8181 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8182   match(Set dst (MoveF2I src));
8183   effect(DEF dst, USE src);
8184   ins_cost(MEMORY_REF_COST);
8185 
8186   format %{ "STF   $src,$dst\t! MoveF2I" %}
8187   opcode(Assembler::stf_op3);
8188   ins_encode(simple_form3_mem_reg(dst, src));
8189   ins_pipe(fstoreF_stk_reg);
8190 %}
8191 
8192 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8193   match(Set dst (MoveI2F src));
8194   effect(DEF dst, USE src);
8195   ins_cost(MEMORY_REF_COST);
8196 
8197   format %{ "STW    $src,$dst\t! MoveI2F" %}
8198   opcode(Assembler::stw_op3);
8199   ins_encode(simple_form3_mem_reg( dst, src ) );
8200   ins_pipe(istore_mem_reg);
8201 %}
8202 
8203 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8204   match(Set dst (MoveD2L src));
8205   effect(DEF dst, USE src);
8206   ins_cost(MEMORY_REF_COST);
8207 
8208   format %{ "STDF   $src,$dst\t! MoveD2L" %}
8209   opcode(Assembler::stdf_op3);
8210   ins_encode(simple_form3_mem_reg(dst, src));
8211   ins_pipe(fstoreD_stk_reg);
8212 %}
8213 
8214 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8215   match(Set dst (MoveL2D src));
8216   effect(DEF dst, USE src);
8217   ins_cost(MEMORY_REF_COST);
8218 
8219   format %{ "STX    $src,$dst\t! MoveL2D" %}
8220   opcode(Assembler::stx_op3);
8221   ins_encode(simple_form3_mem_reg( dst, src ) );
8222   ins_pipe(istore_mem_reg);
8223 %}
8224 
8225 
8226 //----------Arithmetic Conversion Instructions---------------------------------
8227 // The conversions operations are all Alpha sorted.  Please keep it that way!
8228 
8229 instruct convD2F_reg(regF dst, regD src) %{
8230   match(Set dst (ConvD2F src));
8231   size(4);
8232   format %{ "FDTOS  $src,$dst" %}
8233   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8234   ins_encode(form3_opf_rs2D_rdF(src, dst));
8235   ins_pipe(fcvtD2F);
8236 %}
8237 
8238 
8239 // Convert a double to an int in a float register.
8240 // If the double is a NAN, stuff a zero in instead.
8241 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8242   effect(DEF dst, USE src, KILL fcc0);
8243   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8244             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8245             "FDTOI  $src,$dst\t! convert in delay slot\n\t"
8246             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8247             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8248       "skip:" %}
8249   ins_encode(form_d2i_helper(src,dst));
8250   ins_pipe(fcvtD2I);
8251 %}
8252 
8253 instruct convD2I_stk(stackSlotI dst, regD src) %{
8254   match(Set dst (ConvD2I src));
8255   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8256   expand %{
8257     regF tmp;
8258     convD2I_helper(tmp, src);
8259     regF_to_stkI(dst, tmp);
8260   %}
8261 %}
8262 
8263 instruct convD2I_reg(iRegI dst, regD src) %{
8264   predicate(UseVIS >= 3);
8265   match(Set dst (ConvD2I src));
8266   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8267   expand %{
8268     regF tmp;
8269     convD2I_helper(tmp, src);
8270     MoveF2I_reg_reg(dst, tmp);
8271   %}
8272 %}
8273 
8274 
8275 // Convert a double to a long in a double register.
8276 // If the double is a NAN, stuff a zero in instead.
8277 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8278   effect(DEF dst, USE src, KILL fcc0);
8279   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8280             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8281             "FDTOX  $src,$dst\t! convert in delay slot\n\t"
8282             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8283             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8284       "skip:" %}
8285   ins_encode(form_d2l_helper(src,dst));
8286   ins_pipe(fcvtD2L);
8287 %}
8288 
8289 instruct convD2L_stk(stackSlotL dst, regD src) %{
8290   match(Set dst (ConvD2L src));
8291   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8292   expand %{
8293     regD tmp;
8294     convD2L_helper(tmp, src);
8295     regD_to_stkL(dst, tmp);
8296   %}
8297 %}
8298 
8299 instruct convD2L_reg(iRegL dst, regD src) %{
8300   predicate(UseVIS >= 3);
8301   match(Set dst (ConvD2L src));
8302   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8303   expand %{
8304     regD tmp;
8305     convD2L_helper(tmp, src);
8306     MoveD2L_reg_reg(dst, tmp);
8307   %}
8308 %}
8309 
8310 
8311 instruct convF2D_reg(regD dst, regF src) %{
8312   match(Set dst (ConvF2D src));
8313   format %{ "FSTOD  $src,$dst" %}
8314   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8315   ins_encode(form3_opf_rs2F_rdD(src, dst));
8316   ins_pipe(fcvtF2D);
8317 %}
8318 
8319 
8320 // Convert a float to an int in a float register.
8321 // If the float is a NAN, stuff a zero in instead.
8322 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8323   effect(DEF dst, USE src, KILL fcc0);
8324   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8325             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8326             "FSTOI  $src,$dst\t! convert in delay slot\n\t"
8327             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8328             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8329       "skip:" %}
8330   ins_encode(form_f2i_helper(src,dst));
8331   ins_pipe(fcvtF2I);
8332 %}
8333 
8334 instruct convF2I_stk(stackSlotI dst, regF src) %{
8335   match(Set dst (ConvF2I src));
8336   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8337   expand %{
8338     regF tmp;
8339     convF2I_helper(tmp, src);
8340     regF_to_stkI(dst, tmp);
8341   %}
8342 %}
8343 
8344 instruct convF2I_reg(iRegI dst, regF src) %{
8345   predicate(UseVIS >= 3);
8346   match(Set dst (ConvF2I src));
8347   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8348   expand %{
8349     regF tmp;
8350     convF2I_helper(tmp, src);
8351     MoveF2I_reg_reg(dst, tmp);
8352   %}
8353 %}
8354 
8355 
8356 // Convert a float to a long in a float register.
8357 // If the float is a NAN, stuff a zero in instead.
8358 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8359   effect(DEF dst, USE src, KILL fcc0);
8360   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8361             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8362             "FSTOX  $src,$dst\t! convert in delay slot\n\t"
8363             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8364             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8365       "skip:" %}
8366   ins_encode(form_f2l_helper(src,dst));
8367   ins_pipe(fcvtF2L);
8368 %}
8369 
8370 instruct convF2L_stk(stackSlotL dst, regF src) %{
8371   match(Set dst (ConvF2L src));
8372   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8373   expand %{
8374     regD tmp;
8375     convF2L_helper(tmp, src);
8376     regD_to_stkL(dst, tmp);
8377   %}
8378 %}
8379 
8380 instruct convF2L_reg(iRegL dst, regF src) %{
8381   predicate(UseVIS >= 3);
8382   match(Set dst (ConvF2L src));
8383   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8384   expand %{
8385     regD tmp;
8386     convF2L_helper(tmp, src);
8387     MoveD2L_reg_reg(dst, tmp);
8388   %}
8389 %}
8390 
8391 
8392 instruct convI2D_helper(regD dst, regF tmp) %{
8393   effect(USE tmp, DEF dst);
8394   format %{ "FITOD  $tmp,$dst" %}
8395   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8396   ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8397   ins_pipe(fcvtI2D);
8398 %}
8399 
8400 instruct convI2D_stk(stackSlotI src, regD dst) %{
8401   match(Set dst (ConvI2D src));
8402   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8403   expand %{
8404     regF tmp;
8405     stkI_to_regF(tmp, src);
8406     convI2D_helper(dst, tmp);
8407   %}
8408 %}
8409 
8410 instruct convI2D_reg(regD_low dst, iRegI src) %{
8411   predicate(UseVIS >= 3);
8412   match(Set dst (ConvI2D src));
8413   expand %{
8414     regF tmp;
8415     MoveI2F_reg_reg(tmp, src);
8416     convI2D_helper(dst, tmp);
8417   %}
8418 %}
8419 
8420 instruct convI2D_mem(regD_low dst, memory mem) %{
8421   match(Set dst (ConvI2D (LoadI mem)));
8422   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8423   format %{ "LDF    $mem,$dst\n\t"
8424             "FITOD  $dst,$dst" %}
8425   opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8426   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8427   ins_pipe(floadF_mem);
8428 %}
8429 
8430 
8431 instruct convI2F_helper(regF dst, regF tmp) %{
8432   effect(DEF dst, USE tmp);
8433   format %{ "FITOS  $tmp,$dst" %}
8434   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8435   ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8436   ins_pipe(fcvtI2F);
8437 %}
8438 
8439 instruct convI2F_stk(regF dst, stackSlotI src) %{
8440   match(Set dst (ConvI2F src));
8441   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8442   expand %{
8443     regF tmp;
8444     stkI_to_regF(tmp,src);
8445     convI2F_helper(dst, tmp);
8446   %}
8447 %}
8448 
8449 instruct convI2F_reg(regF dst, iRegI src) %{
8450   predicate(UseVIS >= 3);
8451   match(Set dst (ConvI2F src));
8452   ins_cost(DEFAULT_COST);
8453   expand %{
8454     regF tmp;
8455     MoveI2F_reg_reg(tmp, src);
8456     convI2F_helper(dst, tmp);
8457   %}
8458 %}
8459 
8460 instruct convI2F_mem( regF dst, memory mem ) %{
8461   match(Set dst (ConvI2F (LoadI mem)));
8462   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8463   format %{ "LDF    $mem,$dst\n\t"
8464             "FITOS  $dst,$dst" %}
8465   opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8466   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8467   ins_pipe(floadF_mem);
8468 %}
8469 
8470 
8471 instruct convI2L_reg(iRegL dst, iRegI src) %{
8472   match(Set dst (ConvI2L src));
8473   size(4);
8474   format %{ "SRA    $src,0,$dst\t! int->long" %}
8475   opcode(Assembler::sra_op3, Assembler::arith_op);
8476   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8477   ins_pipe(ialu_reg_reg);
8478 %}
8479 
8480 // Zero-extend convert int to long
8481 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8482   match(Set dst (AndL (ConvI2L src) mask) );
8483   size(4);
8484   format %{ "SRL    $src,0,$dst\t! zero-extend int to long" %}
8485   opcode(Assembler::srl_op3, Assembler::arith_op);
8486   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8487   ins_pipe(ialu_reg_reg);
8488 %}
8489 
8490 // Zero-extend long
8491 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8492   match(Set dst (AndL src mask) );
8493   size(4);
8494   format %{ "SRL    $src,0,$dst\t! zero-extend long" %}
8495   opcode(Assembler::srl_op3, Assembler::arith_op);
8496   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8497   ins_pipe(ialu_reg_reg);
8498 %}
8499 
8500 
8501 //-----------
8502 // Long to Double conversion using V8 opcodes.
8503 // Still useful because cheetah traps and becomes
8504 // amazingly slow for some common numbers.
8505 
8506 // Magic constant, 0x43300000
8507 instruct loadConI_x43300000(iRegI dst) %{
8508   effect(DEF dst);
8509   size(4);
8510   format %{ "SETHI  HI(0x43300000),$dst\t! 2^52" %}
8511   ins_encode(SetHi22(0x43300000, dst));
8512   ins_pipe(ialu_none);
8513 %}
8514 
8515 // Magic constant, 0x41f00000
8516 instruct loadConI_x41f00000(iRegI dst) %{
8517   effect(DEF dst);
8518   size(4);
8519   format %{ "SETHI  HI(0x41f00000),$dst\t! 2^32" %}
8520   ins_encode(SetHi22(0x41f00000, dst));
8521   ins_pipe(ialu_none);
8522 %}
8523 
8524 // Construct a double from two float halves
8525 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8526   effect(DEF dst, USE src1, USE src2);
8527   size(8);
8528   format %{ "FMOVS  $src1.hi,$dst.hi\n\t"
8529             "FMOVS  $src2.lo,$dst.lo" %}
8530   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8531   ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8532   ins_pipe(faddD_reg_reg);
8533 %}
8534 
8535 // Convert integer in high half of a double register (in the lower half of
8536 // the double register file) to double
8537 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8538   effect(DEF dst, USE src);
8539   size(4);
8540   format %{ "FITOD  $src,$dst" %}
8541   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8542   ins_encode(form3_opf_rs2D_rdD(src, dst));
8543   ins_pipe(fcvtLHi2D);
8544 %}
8545 
8546 // Add float double precision
8547 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8548   effect(DEF dst, USE src1, USE src2);
8549   size(4);
8550   format %{ "FADDD  $src1,$src2,$dst" %}
8551   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8552   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8553   ins_pipe(faddD_reg_reg);
8554 %}
8555 
8556 // Sub float double precision
8557 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8558   effect(DEF dst, USE src1, USE src2);
8559   size(4);
8560   format %{ "FSUBD  $src1,$src2,$dst" %}
8561   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8562   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8563   ins_pipe(faddD_reg_reg);
8564 %}
8565 
8566 // Mul float double precision
8567 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8568   effect(DEF dst, USE src1, USE src2);
8569   size(4);
8570   format %{ "FMULD  $src1,$src2,$dst" %}
8571   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8572   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8573   ins_pipe(fmulD_reg_reg);
8574 %}
8575 
8576 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8577   match(Set dst (ConvL2D src));
8578   ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8579 
8580   expand %{
8581     regD_low   tmpsrc;
8582     iRegI      ix43300000;
8583     iRegI      ix41f00000;
8584     stackSlotL lx43300000;
8585     stackSlotL lx41f00000;
8586     regD_low   dx43300000;
8587     regD       dx41f00000;
8588     regD       tmp1;
8589     regD_low   tmp2;
8590     regD       tmp3;
8591     regD       tmp4;
8592 
8593     stkL_to_regD(tmpsrc, src);
8594 
8595     loadConI_x43300000(ix43300000);
8596     loadConI_x41f00000(ix41f00000);
8597     regI_to_stkLHi(lx43300000, ix43300000);
8598     regI_to_stkLHi(lx41f00000, ix41f00000);
8599     stkL_to_regD(dx43300000, lx43300000);
8600     stkL_to_regD(dx41f00000, lx41f00000);
8601 
8602     convI2D_regDHi_regD(tmp1, tmpsrc);
8603     regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8604     subD_regD_regD(tmp3, tmp2, dx43300000);
8605     mulD_regD_regD(tmp4, tmp1, dx41f00000);
8606     addD_regD_regD(dst, tmp3, tmp4);
8607   %}
8608 %}
8609 
8610 // Long to Double conversion using fast fxtof
8611 instruct convL2D_helper(regD dst, regD tmp) %{
8612   effect(DEF dst, USE tmp);
8613   size(4);
8614   format %{ "FXTOD  $tmp,$dst" %}
8615   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8616   ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8617   ins_pipe(fcvtL2D);
8618 %}
8619 
8620 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8621   predicate(VM_Version::has_fast_fxtof());
8622   match(Set dst (ConvL2D src));
8623   ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8624   expand %{
8625     regD tmp;
8626     stkL_to_regD(tmp, src);
8627     convL2D_helper(dst, tmp);
8628   %}
8629 %}
8630 
8631 instruct convL2D_reg(regD dst, iRegL src) %{
8632   predicate(UseVIS >= 3);
8633   match(Set dst (ConvL2D src));
8634   expand %{
8635     regD tmp;
8636     MoveL2D_reg_reg(tmp, src);
8637     convL2D_helper(dst, tmp);
8638   %}
8639 %}
8640 
8641 // Long to Float conversion using fast fxtof
8642 instruct convL2F_helper(regF dst, regD tmp) %{
8643   effect(DEF dst, USE tmp);
8644   size(4);
8645   format %{ "FXTOS  $tmp,$dst" %}
8646   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8647   ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8648   ins_pipe(fcvtL2F);
8649 %}
8650 
8651 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8652   match(Set dst (ConvL2F src));
8653   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8654   expand %{
8655     regD tmp;
8656     stkL_to_regD(tmp, src);
8657     convL2F_helper(dst, tmp);
8658   %}
8659 %}
8660 
8661 instruct convL2F_reg(regF dst, iRegL src) %{
8662   predicate(UseVIS >= 3);
8663   match(Set dst (ConvL2F src));
8664   ins_cost(DEFAULT_COST);
8665   expand %{
8666     regD tmp;
8667     MoveL2D_reg_reg(tmp, src);
8668     convL2F_helper(dst, tmp);
8669   %}
8670 %}
8671 
8672 //-----------
8673 
8674 instruct convL2I_reg(iRegI dst, iRegL src) %{
8675   match(Set dst (ConvL2I src));
8676 #ifndef _LP64
8677   format %{ "MOV    $src.lo,$dst\t! long->int" %}
8678   ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8679   ins_pipe(ialu_move_reg_I_to_L);
8680 #else
8681   size(4);
8682   format %{ "SRA    $src,R_G0,$dst\t! long->int" %}
8683   ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8684   ins_pipe(ialu_reg);
8685 #endif
8686 %}
8687 
8688 // Register Shift Right Immediate
8689 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8690   match(Set dst (ConvL2I (RShiftL src cnt)));
8691 
8692   size(4);
8693   format %{ "SRAX   $src,$cnt,$dst" %}
8694   opcode(Assembler::srax_op3, Assembler::arith_op);
8695   ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8696   ins_pipe(ialu_reg_imm);
8697 %}
8698 
8699 //----------Control Flow Instructions------------------------------------------
8700 // Compare Instructions
8701 // Compare Integers
8702 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8703   match(Set icc (CmpI op1 op2));
8704   effect( DEF icc, USE op1, USE op2 );
8705 
8706   size(4);
8707   format %{ "CMP    $op1,$op2" %}
8708   opcode(Assembler::subcc_op3, Assembler::arith_op);
8709   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8710   ins_pipe(ialu_cconly_reg_reg);
8711 %}
8712 
8713 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8714   match(Set icc (CmpU op1 op2));
8715 
8716   size(4);
8717   format %{ "CMP    $op1,$op2\t! unsigned" %}
8718   opcode(Assembler::subcc_op3, Assembler::arith_op);
8719   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8720   ins_pipe(ialu_cconly_reg_reg);
8721 %}
8722 
8723 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8724   match(Set icc (CmpI op1 op2));
8725   effect( DEF icc, USE op1 );
8726 
8727   size(4);
8728   format %{ "CMP    $op1,$op2" %}
8729   opcode(Assembler::subcc_op3, Assembler::arith_op);
8730   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8731   ins_pipe(ialu_cconly_reg_imm);
8732 %}
8733 
8734 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8735   match(Set icc (CmpI (AndI op1 op2) zero));
8736 
8737   size(4);
8738   format %{ "BTST   $op2,$op1" %}
8739   opcode(Assembler::andcc_op3, Assembler::arith_op);
8740   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8741   ins_pipe(ialu_cconly_reg_reg_zero);
8742 %}
8743 
8744 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8745   match(Set icc (CmpI (AndI op1 op2) zero));
8746 
8747   size(4);
8748   format %{ "BTST   $op2,$op1" %}
8749   opcode(Assembler::andcc_op3, Assembler::arith_op);
8750   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8751   ins_pipe(ialu_cconly_reg_imm_zero);
8752 %}
8753 
8754 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8755   match(Set xcc (CmpL op1 op2));
8756   effect( DEF xcc, USE op1, USE op2 );
8757 
8758   size(4);
8759   format %{ "CMP    $op1,$op2\t\t! long" %}
8760   opcode(Assembler::subcc_op3, Assembler::arith_op);
8761   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8762   ins_pipe(ialu_cconly_reg_reg);
8763 %}
8764 
8765 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8766   match(Set xcc (CmpL op1 con));
8767   effect( DEF xcc, USE op1, USE con );
8768 
8769   size(4);
8770   format %{ "CMP    $op1,$con\t\t! long" %}
8771   opcode(Assembler::subcc_op3, Assembler::arith_op);
8772   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8773   ins_pipe(ialu_cconly_reg_reg);
8774 %}
8775 
8776 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8777   match(Set xcc (CmpL (AndL op1 op2) zero));
8778   effect( DEF xcc, USE op1, USE op2 );
8779 
8780   size(4);
8781   format %{ "BTST   $op1,$op2\t\t! long" %}
8782   opcode(Assembler::andcc_op3, Assembler::arith_op);
8783   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8784   ins_pipe(ialu_cconly_reg_reg);
8785 %}
8786 
8787 // useful for checking the alignment of a pointer:
8788 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8789   match(Set xcc (CmpL (AndL op1 con) zero));
8790   effect( DEF xcc, USE op1, USE con );
8791 
8792   size(4);
8793   format %{ "BTST   $op1,$con\t\t! long" %}
8794   opcode(Assembler::andcc_op3, Assembler::arith_op);
8795   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8796   ins_pipe(ialu_cconly_reg_reg);
8797 %}
8798 
8799 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8800   match(Set icc (CmpU op1 op2));
8801 
8802   size(4);
8803   format %{ "CMP    $op1,$op2\t! unsigned" %}
8804   opcode(Assembler::subcc_op3, Assembler::arith_op);
8805   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8806   ins_pipe(ialu_cconly_reg_imm);
8807 %}
8808 
8809 // Compare Pointers
8810 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8811   match(Set pcc (CmpP op1 op2));
8812 
8813   size(4);
8814   format %{ "CMP    $op1,$op2\t! ptr" %}
8815   opcode(Assembler::subcc_op3, Assembler::arith_op);
8816   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8817   ins_pipe(ialu_cconly_reg_reg);
8818 %}
8819 
8820 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8821   match(Set pcc (CmpP op1 op2));
8822 
8823   size(4);
8824   format %{ "CMP    $op1,$op2\t! ptr" %}
8825   opcode(Assembler::subcc_op3, Assembler::arith_op);
8826   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8827   ins_pipe(ialu_cconly_reg_imm);
8828 %}
8829 
8830 // Compare Narrow oops
8831 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8832   match(Set icc (CmpN op1 op2));
8833 
8834   size(4);
8835   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
8836   opcode(Assembler::subcc_op3, Assembler::arith_op);
8837   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8838   ins_pipe(ialu_cconly_reg_reg);
8839 %}
8840 
8841 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8842   match(Set icc (CmpN op1 op2));
8843 
8844   size(4);
8845   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
8846   opcode(Assembler::subcc_op3, Assembler::arith_op);
8847   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8848   ins_pipe(ialu_cconly_reg_imm);
8849 %}
8850 
8851 //----------Max and Min--------------------------------------------------------
8852 // Min Instructions
8853 // Conditional move for min
8854 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8855   effect( USE_DEF op2, USE op1, USE icc );
8856 
8857   size(4);
8858   format %{ "MOVlt  icc,$op1,$op2\t! min" %}
8859   opcode(Assembler::less);
8860   ins_encode( enc_cmov_reg_minmax(op2,op1) );
8861   ins_pipe(ialu_reg_flags);
8862 %}
8863 
8864 // Min Register with Register.
8865 instruct minI_eReg(iRegI op1, iRegI op2) %{
8866   match(Set op2 (MinI op1 op2));
8867   ins_cost(DEFAULT_COST*2);
8868   expand %{
8869     flagsReg icc;
8870     compI_iReg(icc,op1,op2);
8871     cmovI_reg_lt(op2,op1,icc);
8872   %}
8873 %}
8874 
8875 // Max Instructions
8876 // Conditional move for max
8877 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8878   effect( USE_DEF op2, USE op1, USE icc );
8879   format %{ "MOVgt  icc,$op1,$op2\t! max" %}
8880   opcode(Assembler::greater);
8881   ins_encode( enc_cmov_reg_minmax(op2,op1) );
8882   ins_pipe(ialu_reg_flags);
8883 %}
8884 
8885 // Max Register with Register
8886 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8887   match(Set op2 (MaxI op1 op2));
8888   ins_cost(DEFAULT_COST*2);
8889   expand %{
8890     flagsReg icc;
8891     compI_iReg(icc,op1,op2);
8892     cmovI_reg_gt(op2,op1,icc);
8893   %}
8894 %}
8895 
8896 
8897 //----------Float Compares----------------------------------------------------
8898 // Compare floating, generate condition code
8899 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8900   match(Set fcc (CmpF src1 src2));
8901 
8902   size(4);
8903   format %{ "FCMPs  $fcc,$src1,$src2" %}
8904   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8905   ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8906   ins_pipe(faddF_fcc_reg_reg_zero);
8907 %}
8908 
8909 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8910   match(Set fcc (CmpD src1 src2));
8911 
8912   size(4);
8913   format %{ "FCMPd  $fcc,$src1,$src2" %}
8914   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8915   ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8916   ins_pipe(faddD_fcc_reg_reg_zero);
8917 %}
8918 
8919 
8920 // Compare floating, generate -1,0,1
8921 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8922   match(Set dst (CmpF3 src1 src2));
8923   effect(KILL fcc0);
8924   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8925   format %{ "fcmpl  $dst,$src1,$src2" %}
8926   // Primary = float
8927   opcode( true );
8928   ins_encode( floating_cmp( dst, src1, src2 ) );
8929   ins_pipe( floating_cmp );
8930 %}
8931 
8932 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8933   match(Set dst (CmpD3 src1 src2));
8934   effect(KILL fcc0);
8935   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8936   format %{ "dcmpl  $dst,$src1,$src2" %}
8937   // Primary = double (not float)
8938   opcode( false );
8939   ins_encode( floating_cmp( dst, src1, src2 ) );
8940   ins_pipe( floating_cmp );
8941 %}
8942 
8943 //----------Branches---------------------------------------------------------
8944 // Jump
8945 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8946 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8947   match(Jump switch_val);
8948   effect(TEMP table);
8949 
8950   ins_cost(350);
8951 
8952   format %{  "ADD    $constanttablebase, $constantoffset, O7\n\t"
8953              "LD     [O7 + $switch_val], O7\n\t"
8954              "JUMP   O7" %}
8955   ins_encode %{
8956     // Calculate table address into a register.
8957     Register table_reg;
8958     Register label_reg = O7;
8959     // If we are calculating the size of this instruction don't trust
8960     // zero offsets because they might change when
8961     // MachConstantBaseNode decides to optimize the constant table
8962     // base.
8963     if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8964       table_reg = $constanttablebase;
8965     } else {
8966       table_reg = O7;
8967       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8968       __ add($constanttablebase, con_offset, table_reg);
8969     }
8970 
8971     // Jump to base address + switch value
8972     __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8973     __ jmp(label_reg, G0);
8974     __ delayed()->nop();
8975   %}
8976   ins_pipe(ialu_reg_reg);
8977 %}
8978 
8979 // Direct Branch.  Use V8 version with longer range.
8980 instruct branch(label labl) %{
8981   match(Goto);
8982   effect(USE labl);
8983 
8984   size(8);
8985   ins_cost(BRANCH_COST);
8986   format %{ "BA     $labl" %}
8987   ins_encode %{
8988     Label* L = $labl$$label;
8989     __ ba(*L);
8990     __ delayed()->nop();
8991   %}
8992   ins_avoid_back_to_back(AVOID_BEFORE);
8993   ins_pipe(br);
8994 %}
8995 
8996 // Direct Branch, short with no delay slot
8997 instruct branch_short(label labl) %{
8998   match(Goto);
8999   predicate(UseCBCond);
9000   effect(USE labl);
9001 
9002   size(4);
9003   ins_cost(BRANCH_COST);
9004   format %{ "BA     $labl\t! short branch" %}
9005   ins_encode %{
9006     Label* L = $labl$$label;
9007     assert(__ use_cbcond(*L), "back to back cbcond");
9008     __ ba_short(*L);
9009   %}
9010   ins_short_branch(1);
9011   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9012   ins_pipe(cbcond_reg_imm);
9013 %}
9014 
9015 // Conditional Direct Branch
9016 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9017   match(If cmp icc);
9018   effect(USE labl);
9019 
9020   size(8);
9021   ins_cost(BRANCH_COST);
9022   format %{ "BP$cmp   $icc,$labl" %}
9023   // Prim = bits 24-22, Secnd = bits 31-30
9024   ins_encode( enc_bp( labl, cmp, icc ) );
9025   ins_avoid_back_to_back(AVOID_BEFORE);
9026   ins_pipe(br_cc);
9027 %}
9028 
9029 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9030   match(If cmp icc);
9031   effect(USE labl);
9032 
9033   ins_cost(BRANCH_COST);
9034   format %{ "BP$cmp  $icc,$labl" %}
9035   // Prim = bits 24-22, Secnd = bits 31-30
9036   ins_encode( enc_bp( labl, cmp, icc ) );
9037   ins_avoid_back_to_back(AVOID_BEFORE);
9038   ins_pipe(br_cc);
9039 %}
9040 
9041 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9042   match(If cmp pcc);
9043   effect(USE labl);
9044 
9045   size(8);
9046   ins_cost(BRANCH_COST);
9047   format %{ "BP$cmp  $pcc,$labl" %}
9048   ins_encode %{
9049     Label* L = $labl$$label;
9050     Assembler::Predict predict_taken =
9051       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9052 
9053     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9054     __ delayed()->nop();
9055   %}
9056   ins_avoid_back_to_back(AVOID_BEFORE);
9057   ins_pipe(br_cc);
9058 %}
9059 
9060 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9061   match(If cmp fcc);
9062   effect(USE labl);
9063 
9064   size(8);
9065   ins_cost(BRANCH_COST);
9066   format %{ "FBP$cmp $fcc,$labl" %}
9067   ins_encode %{
9068     Label* L = $labl$$label;
9069     Assembler::Predict predict_taken =
9070       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9071 
9072     __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9073     __ delayed()->nop();
9074   %}
9075   ins_avoid_back_to_back(AVOID_BEFORE);
9076   ins_pipe(br_fcc);
9077 %}
9078 
9079 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9080   match(CountedLoopEnd cmp icc);
9081   effect(USE labl);
9082 
9083   size(8);
9084   ins_cost(BRANCH_COST);
9085   format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
9086   // Prim = bits 24-22, Secnd = bits 31-30
9087   ins_encode( enc_bp( labl, cmp, icc ) );
9088   ins_avoid_back_to_back(AVOID_BEFORE);
9089   ins_pipe(br_cc);
9090 %}
9091 
9092 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9093   match(CountedLoopEnd cmp icc);
9094   effect(USE labl);
9095 
9096   size(8);
9097   ins_cost(BRANCH_COST);
9098   format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
9099   // Prim = bits 24-22, Secnd = bits 31-30
9100   ins_encode( enc_bp( labl, cmp, icc ) );
9101   ins_avoid_back_to_back(AVOID_BEFORE);
9102   ins_pipe(br_cc);
9103 %}
9104 
9105 // Compare and branch instructions
9106 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9107   match(If cmp (CmpI op1 op2));
9108   effect(USE labl, KILL icc);
9109 
9110   size(12);
9111   ins_cost(BRANCH_COST);
9112   format %{ "CMP    $op1,$op2\t! int\n\t"
9113             "BP$cmp   $labl" %}
9114   ins_encode %{
9115     Label* L = $labl$$label;
9116     Assembler::Predict predict_taken =
9117       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9118     __ cmp($op1$$Register, $op2$$Register);
9119     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9120     __ delayed()->nop();
9121   %}
9122   ins_pipe(cmp_br_reg_reg);
9123 %}
9124 
9125 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9126   match(If cmp (CmpI op1 op2));
9127   effect(USE labl, KILL icc);
9128 
9129   size(12);
9130   ins_cost(BRANCH_COST);
9131   format %{ "CMP    $op1,$op2\t! int\n\t"
9132             "BP$cmp   $labl" %}
9133   ins_encode %{
9134     Label* L = $labl$$label;
9135     Assembler::Predict predict_taken =
9136       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9137     __ cmp($op1$$Register, $op2$$constant);
9138     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9139     __ delayed()->nop();
9140   %}
9141   ins_pipe(cmp_br_reg_imm);
9142 %}
9143 
9144 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9145   match(If cmp (CmpU op1 op2));
9146   effect(USE labl, KILL icc);
9147 
9148   size(12);
9149   ins_cost(BRANCH_COST);
9150   format %{ "CMP    $op1,$op2\t! unsigned\n\t"
9151             "BP$cmp  $labl" %}
9152   ins_encode %{
9153     Label* L = $labl$$label;
9154     Assembler::Predict predict_taken =
9155       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9156     __ cmp($op1$$Register, $op2$$Register);
9157     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9158     __ delayed()->nop();
9159   %}
9160   ins_pipe(cmp_br_reg_reg);
9161 %}
9162 
9163 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9164   match(If cmp (CmpU op1 op2));
9165   effect(USE labl, KILL icc);
9166 
9167   size(12);
9168   ins_cost(BRANCH_COST);
9169   format %{ "CMP    $op1,$op2\t! unsigned\n\t"
9170             "BP$cmp  $labl" %}
9171   ins_encode %{
9172     Label* L = $labl$$label;
9173     Assembler::Predict predict_taken =
9174       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9175     __ cmp($op1$$Register, $op2$$constant);
9176     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9177     __ delayed()->nop();
9178   %}
9179   ins_pipe(cmp_br_reg_imm);
9180 %}
9181 
9182 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9183   match(If cmp (CmpL op1 op2));
9184   effect(USE labl, KILL xcc);
9185 
9186   size(12);
9187   ins_cost(BRANCH_COST);
9188   format %{ "CMP    $op1,$op2\t! long\n\t"
9189             "BP$cmp   $labl" %}
9190   ins_encode %{
9191     Label* L = $labl$$label;
9192     Assembler::Predict predict_taken =
9193       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9194     __ cmp($op1$$Register, $op2$$Register);
9195     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9196     __ delayed()->nop();
9197   %}
9198   ins_pipe(cmp_br_reg_reg);
9199 %}
9200 
9201 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9202   match(If cmp (CmpL op1 op2));
9203   effect(USE labl, KILL xcc);
9204 
9205   size(12);
9206   ins_cost(BRANCH_COST);
9207   format %{ "CMP    $op1,$op2\t! long\n\t"
9208             "BP$cmp   $labl" %}
9209   ins_encode %{
9210     Label* L = $labl$$label;
9211     Assembler::Predict predict_taken =
9212       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9213     __ cmp($op1$$Register, $op2$$constant);
9214     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9215     __ delayed()->nop();
9216   %}
9217   ins_pipe(cmp_br_reg_imm);
9218 %}
9219 
9220 // Compare Pointers and branch
9221 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9222   match(If cmp (CmpP op1 op2));
9223   effect(USE labl, KILL pcc);
9224 
9225   size(12);
9226   ins_cost(BRANCH_COST);
9227   format %{ "CMP    $op1,$op2\t! ptr\n\t"
9228             "B$cmp   $labl" %}
9229   ins_encode %{
9230     Label* L = $labl$$label;
9231     Assembler::Predict predict_taken =
9232       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9233     __ cmp($op1$$Register, $op2$$Register);
9234     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9235     __ delayed()->nop();
9236   %}
9237   ins_pipe(cmp_br_reg_reg);
9238 %}
9239 
9240 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9241   match(If cmp (CmpP op1 null));
9242   effect(USE labl, KILL pcc);
9243 
9244   size(12);
9245   ins_cost(BRANCH_COST);
9246   format %{ "CMP    $op1,0\t! ptr\n\t"
9247             "B$cmp   $labl" %}
9248   ins_encode %{
9249     Label* L = $labl$$label;
9250     Assembler::Predict predict_taken =
9251       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9252     __ cmp($op1$$Register, G0);
9253     // bpr() is not used here since it has shorter distance.
9254     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9255     __ delayed()->nop();
9256   %}
9257   ins_pipe(cmp_br_reg_reg);
9258 %}
9259 
9260 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9261   match(If cmp (CmpN op1 op2));
9262   effect(USE labl, KILL icc);
9263 
9264   size(12);
9265   ins_cost(BRANCH_COST);
9266   format %{ "CMP    $op1,$op2\t! compressed ptr\n\t"
9267             "BP$cmp   $labl" %}
9268   ins_encode %{
9269     Label* L = $labl$$label;
9270     Assembler::Predict predict_taken =
9271       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9272     __ cmp($op1$$Register, $op2$$Register);
9273     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9274     __ delayed()->nop();
9275   %}
9276   ins_pipe(cmp_br_reg_reg);
9277 %}
9278 
9279 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9280   match(If cmp (CmpN op1 null));
9281   effect(USE labl, KILL icc);
9282 
9283   size(12);
9284   ins_cost(BRANCH_COST);
9285   format %{ "CMP    $op1,0\t! compressed ptr\n\t"
9286             "BP$cmp   $labl" %}
9287   ins_encode %{
9288     Label* L = $labl$$label;
9289     Assembler::Predict predict_taken =
9290       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9291     __ cmp($op1$$Register, G0);
9292     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9293     __ delayed()->nop();
9294   %}
9295   ins_pipe(cmp_br_reg_reg);
9296 %}
9297 
9298 // Loop back branch
9299 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9300   match(CountedLoopEnd cmp (CmpI op1 op2));
9301   effect(USE labl, KILL icc);
9302 
9303   size(12);
9304   ins_cost(BRANCH_COST);
9305   format %{ "CMP    $op1,$op2\t! int\n\t"
9306             "BP$cmp   $labl\t! Loop end" %}
9307   ins_encode %{
9308     Label* L = $labl$$label;
9309     Assembler::Predict predict_taken =
9310       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9311     __ cmp($op1$$Register, $op2$$Register);
9312     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9313     __ delayed()->nop();
9314   %}
9315   ins_pipe(cmp_br_reg_reg);
9316 %}
9317 
9318 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9319   match(CountedLoopEnd cmp (CmpI op1 op2));
9320   effect(USE labl, KILL icc);
9321 
9322   size(12);
9323   ins_cost(BRANCH_COST);
9324   format %{ "CMP    $op1,$op2\t! int\n\t"
9325             "BP$cmp   $labl\t! Loop end" %}
9326   ins_encode %{
9327     Label* L = $labl$$label;
9328     Assembler::Predict predict_taken =
9329       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9330     __ cmp($op1$$Register, $op2$$constant);
9331     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9332     __ delayed()->nop();
9333   %}
9334   ins_pipe(cmp_br_reg_imm);
9335 %}
9336 
9337 // Short compare and branch instructions
9338 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9339   match(If cmp (CmpI op1 op2));
9340   predicate(UseCBCond);
9341   effect(USE labl, KILL icc);
9342 
9343   size(4);
9344   ins_cost(BRANCH_COST);
9345   format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
9346   ins_encode %{
9347     Label* L = $labl$$label;
9348     assert(__ use_cbcond(*L), "back to back cbcond");
9349     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9350   %}
9351   ins_short_branch(1);
9352   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9353   ins_pipe(cbcond_reg_reg);
9354 %}
9355 
9356 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9357   match(If cmp (CmpI op1 op2));
9358   predicate(UseCBCond);
9359   effect(USE labl, KILL icc);
9360 
9361   size(4);
9362   ins_cost(BRANCH_COST);
9363   format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
9364   ins_encode %{
9365     Label* L = $labl$$label;
9366     assert(__ use_cbcond(*L), "back to back cbcond");
9367     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9368   %}
9369   ins_short_branch(1);
9370   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9371   ins_pipe(cbcond_reg_imm);
9372 %}
9373 
9374 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9375   match(If cmp (CmpU op1 op2));
9376   predicate(UseCBCond);
9377   effect(USE labl, KILL icc);
9378 
9379   size(4);
9380   ins_cost(BRANCH_COST);
9381   format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9382   ins_encode %{
9383     Label* L = $labl$$label;
9384     assert(__ use_cbcond(*L), "back to back cbcond");
9385     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9386   %}
9387   ins_short_branch(1);
9388   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9389   ins_pipe(cbcond_reg_reg);
9390 %}
9391 
9392 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9393   match(If cmp (CmpU op1 op2));
9394   predicate(UseCBCond);
9395   effect(USE labl, KILL icc);
9396 
9397   size(4);
9398   ins_cost(BRANCH_COST);
9399   format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9400   ins_encode %{
9401     Label* L = $labl$$label;
9402     assert(__ use_cbcond(*L), "back to back cbcond");
9403     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9404   %}
9405   ins_short_branch(1);
9406   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9407   ins_pipe(cbcond_reg_imm);
9408 %}
9409 
9410 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9411   match(If cmp (CmpL op1 op2));
9412   predicate(UseCBCond);
9413   effect(USE labl, KILL xcc);
9414 
9415   size(4);
9416   ins_cost(BRANCH_COST);
9417   format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
9418   ins_encode %{
9419     Label* L = $labl$$label;
9420     assert(__ use_cbcond(*L), "back to back cbcond");
9421     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9422   %}
9423   ins_short_branch(1);
9424   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9425   ins_pipe(cbcond_reg_reg);
9426 %}
9427 
9428 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9429   match(If cmp (CmpL op1 op2));
9430   predicate(UseCBCond);
9431   effect(USE labl, KILL xcc);
9432 
9433   size(4);
9434   ins_cost(BRANCH_COST);
9435   format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
9436   ins_encode %{
9437     Label* L = $labl$$label;
9438     assert(__ use_cbcond(*L), "back to back cbcond");
9439     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9440   %}
9441   ins_short_branch(1);
9442   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9443   ins_pipe(cbcond_reg_imm);
9444 %}
9445 
9446 // Compare Pointers and branch
9447 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9448   match(If cmp (CmpP op1 op2));
9449   predicate(UseCBCond);
9450   effect(USE labl, KILL pcc);
9451 
9452   size(4);
9453   ins_cost(BRANCH_COST);
9454 #ifdef _LP64
9455   format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9456 #else
9457   format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9458 #endif
9459   ins_encode %{
9460     Label* L = $labl$$label;
9461     assert(__ use_cbcond(*L), "back to back cbcond");
9462     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9463   %}
9464   ins_short_branch(1);
9465   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9466   ins_pipe(cbcond_reg_reg);
9467 %}
9468 
9469 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9470   match(If cmp (CmpP op1 null));
9471   predicate(UseCBCond);
9472   effect(USE labl, KILL pcc);
9473 
9474   size(4);
9475   ins_cost(BRANCH_COST);
9476 #ifdef _LP64
9477   format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9478 #else
9479   format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9480 #endif
9481   ins_encode %{
9482     Label* L = $labl$$label;
9483     assert(__ use_cbcond(*L), "back to back cbcond");
9484     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9485   %}
9486   ins_short_branch(1);
9487   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9488   ins_pipe(cbcond_reg_reg);
9489 %}
9490 
9491 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9492   match(If cmp (CmpN op1 op2));
9493   predicate(UseCBCond);
9494   effect(USE labl, KILL icc);
9495 
9496   size(4);
9497   ins_cost(BRANCH_COST);
9498   format %{ "CWB$cmp  $op1,$op2,$labl\t! compressed ptr" %}
9499   ins_encode %{
9500     Label* L = $labl$$label;
9501     assert(__ use_cbcond(*L), "back to back cbcond");
9502     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9503   %}
9504   ins_short_branch(1);
9505   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9506   ins_pipe(cbcond_reg_reg);
9507 %}
9508 
9509 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9510   match(If cmp (CmpN op1 null));
9511   predicate(UseCBCond);
9512   effect(USE labl, KILL icc);
9513 
9514   size(4);
9515   ins_cost(BRANCH_COST);
9516   format %{ "CWB$cmp  $op1,0,$labl\t! compressed ptr" %}
9517   ins_encode %{
9518     Label* L = $labl$$label;
9519     assert(__ use_cbcond(*L), "back to back cbcond");
9520     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9521   %}
9522   ins_short_branch(1);
9523   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9524   ins_pipe(cbcond_reg_reg);
9525 %}
9526 
9527 // Loop back branch
9528 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9529   match(CountedLoopEnd cmp (CmpI op1 op2));
9530   predicate(UseCBCond);
9531   effect(USE labl, KILL icc);
9532 
9533   size(4);
9534   ins_cost(BRANCH_COST);
9535   format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
9536   ins_encode %{
9537     Label* L = $labl$$label;
9538     assert(__ use_cbcond(*L), "back to back cbcond");
9539     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9540   %}
9541   ins_short_branch(1);
9542   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9543   ins_pipe(cbcond_reg_reg);
9544 %}
9545 
9546 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9547   match(CountedLoopEnd cmp (CmpI op1 op2));
9548   predicate(UseCBCond);
9549   effect(USE labl, KILL icc);
9550 
9551   size(4);
9552   ins_cost(BRANCH_COST);
9553   format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
9554   ins_encode %{
9555     Label* L = $labl$$label;
9556     assert(__ use_cbcond(*L), "back to back cbcond");
9557     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9558   %}
9559   ins_short_branch(1);
9560   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9561   ins_pipe(cbcond_reg_imm);
9562 %}
9563 
9564 // Branch-on-register tests all 64 bits.  We assume that values
9565 // in 64-bit registers always remains zero or sign extended
9566 // unless our code munges the high bits.  Interrupts can chop
9567 // the high order bits to zero or sign at any time.
9568 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9569   match(If cmp (CmpI op1 zero));
9570   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9571   effect(USE labl);
9572 
9573   size(8);
9574   ins_cost(BRANCH_COST);
9575   format %{ "BR$cmp   $op1,$labl" %}
9576   ins_encode( enc_bpr( labl, cmp, op1 ) );
9577   ins_avoid_back_to_back(AVOID_BEFORE);
9578   ins_pipe(br_reg);
9579 %}
9580 
9581 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9582   match(If cmp (CmpP op1 null));
9583   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9584   effect(USE labl);
9585 
9586   size(8);
9587   ins_cost(BRANCH_COST);
9588   format %{ "BR$cmp   $op1,$labl" %}
9589   ins_encode( enc_bpr( labl, cmp, op1 ) );
9590   ins_avoid_back_to_back(AVOID_BEFORE);
9591   ins_pipe(br_reg);
9592 %}
9593 
9594 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9595   match(If cmp (CmpL op1 zero));
9596   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9597   effect(USE labl);
9598 
9599   size(8);
9600   ins_cost(BRANCH_COST);
9601   format %{ "BR$cmp   $op1,$labl" %}
9602   ins_encode( enc_bpr( labl, cmp, op1 ) );
9603   ins_avoid_back_to_back(AVOID_BEFORE);
9604   ins_pipe(br_reg);
9605 %}
9606 
9607 
9608 // ============================================================================
9609 // Long Compare
9610 //
9611 // Currently we hold longs in 2 registers.  Comparing such values efficiently
9612 // is tricky.  The flavor of compare used depends on whether we are testing
9613 // for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
9614 // The GE test is the negated LT test.  The LE test can be had by commuting
9615 // the operands (yielding a GE test) and then negating; negate again for the
9616 // GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
9617 // NE test is negated from that.
9618 
9619 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9620 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
9621 // difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
9622 // are collapsed internally in the ADLC's dfa-gen code.  The match for
9623 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9624 // foo match ends up with the wrong leaf.  One fix is to not match both
9625 // reg-reg and reg-zero forms of long-compare.  This is unfortunate because
9626 // both forms beat the trinary form of long-compare and both are very useful
9627 // on Intel which has so few registers.
9628 
9629 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9630   match(If cmp xcc);
9631   effect(USE labl);
9632 
9633   size(8);
9634   ins_cost(BRANCH_COST);
9635   format %{ "BP$cmp   $xcc,$labl" %}
9636   ins_encode %{
9637     Label* L = $labl$$label;
9638     Assembler::Predict predict_taken =
9639       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9640 
9641     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9642     __ delayed()->nop();
9643   %}
9644   ins_avoid_back_to_back(AVOID_BEFORE);
9645   ins_pipe(br_cc);
9646 %}
9647 
9648 // Manifest a CmpL3 result in an integer register.  Very painful.
9649 // This is the test to avoid.
9650 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9651   match(Set dst (CmpL3 src1 src2) );
9652   effect( KILL ccr );
9653   ins_cost(6*DEFAULT_COST);
9654   size(24);
9655   format %{ "CMP    $src1,$src2\t\t! long\n"
9656           "\tBLT,a,pn done\n"
9657           "\tMOV    -1,$dst\t! delay slot\n"
9658           "\tBGT,a,pn done\n"
9659           "\tMOV    1,$dst\t! delay slot\n"
9660           "\tCLR    $dst\n"
9661     "done:"     %}
9662   ins_encode( cmpl_flag(src1,src2,dst) );
9663   ins_pipe(cmpL_reg);
9664 %}
9665 
9666 // Conditional move
9667 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9668   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9669   ins_cost(150);
9670   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9671   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9672   ins_pipe(ialu_reg);
9673 %}
9674 
9675 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9676   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9677   ins_cost(140);
9678   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9679   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9680   ins_pipe(ialu_imm);
9681 %}
9682 
9683 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9684   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9685   ins_cost(150);
9686   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9687   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9688   ins_pipe(ialu_reg);
9689 %}
9690 
9691 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9692   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9693   ins_cost(140);
9694   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9695   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9696   ins_pipe(ialu_imm);
9697 %}
9698 
9699 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9700   match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9701   ins_cost(150);
9702   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9703   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9704   ins_pipe(ialu_reg);
9705 %}
9706 
9707 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9708   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9709   ins_cost(150);
9710   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9711   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9712   ins_pipe(ialu_reg);
9713 %}
9714 
9715 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9716   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9717   ins_cost(140);
9718   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9719   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9720   ins_pipe(ialu_imm);
9721 %}
9722 
9723 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9724   match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9725   ins_cost(150);
9726   opcode(0x101);
9727   format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9728   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9729   ins_pipe(int_conditional_float_move);
9730 %}
9731 
9732 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9733   match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9734   ins_cost(150);
9735   opcode(0x102);
9736   format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9737   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9738   ins_pipe(int_conditional_float_move);
9739 %}
9740 
9741 // ============================================================================
9742 // Safepoint Instruction
9743 instruct safePoint_poll(iRegP poll) %{
9744   match(SafePoint poll);
9745   effect(USE poll);
9746 
9747   size(4);
9748 #ifdef _LP64
9749   format %{ "LDX    [$poll],R_G0\t! Safepoint: poll for GC" %}
9750 #else
9751   format %{ "LDUW   [$poll],R_G0\t! Safepoint: poll for GC" %}
9752 #endif
9753   ins_encode %{
9754     __ relocate(relocInfo::poll_type);
9755     __ ld_ptr($poll$$Register, 0, G0);
9756   %}
9757   ins_pipe(loadPollP);
9758 %}
9759 
9760 // ============================================================================
9761 // Call Instructions
9762 // Call Java Static Instruction
9763 instruct CallStaticJavaDirect( method meth ) %{
9764   match(CallStaticJava);
9765   predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9766   effect(USE meth);
9767 
9768   size(8);
9769   ins_cost(CALL_COST);
9770   format %{ "CALL,static  ; NOP ==> " %}
9771   ins_encode( Java_Static_Call( meth ), call_epilog );
9772   ins_avoid_back_to_back(AVOID_BEFORE);
9773   ins_pipe(simple_call);
9774 %}
9775 
9776 // Call Java Static Instruction (method handle version)
9777 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9778   match(CallStaticJava);
9779   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9780   effect(USE meth, KILL l7_mh_SP_save);
9781 
9782   size(16);
9783   ins_cost(CALL_COST);
9784   format %{ "CALL,static/MethodHandle" %}
9785   ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9786   ins_pipe(simple_call);
9787 %}
9788 
9789 // Call Java Dynamic Instruction
9790 instruct CallDynamicJavaDirect( method meth ) %{
9791   match(CallDynamicJava);
9792   effect(USE meth);
9793 
9794   ins_cost(CALL_COST);
9795   format %{ "SET    (empty),R_G5\n\t"
9796             "CALL,dynamic  ; NOP ==> " %}
9797   ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9798   ins_pipe(call);
9799 %}
9800 
9801 // Call Runtime Instruction
9802 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9803   match(CallRuntime);
9804   effect(USE meth, KILL l7);
9805   ins_cost(CALL_COST);
9806   format %{ "CALL,runtime" %}
9807   ins_encode( Java_To_Runtime( meth ),
9808               call_epilog, adjust_long_from_native_call );
9809   ins_avoid_back_to_back(AVOID_BEFORE);
9810   ins_pipe(simple_call);
9811 %}
9812 
9813 // Call runtime without safepoint - same as CallRuntime
9814 instruct CallLeafDirect(method meth, l7RegP l7) %{
9815   match(CallLeaf);
9816   effect(USE meth, KILL l7);
9817   ins_cost(CALL_COST);
9818   format %{ "CALL,runtime leaf" %}
9819   ins_encode( Java_To_Runtime( meth ),
9820               call_epilog,
9821               adjust_long_from_native_call );
9822   ins_avoid_back_to_back(AVOID_BEFORE);
9823   ins_pipe(simple_call);
9824 %}
9825 
9826 // Call runtime without safepoint - same as CallLeaf
9827 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9828   match(CallLeafNoFP);
9829   effect(USE meth, KILL l7);
9830   ins_cost(CALL_COST);
9831   format %{ "CALL,runtime leaf nofp" %}
9832   ins_encode( Java_To_Runtime( meth ),
9833               call_epilog,
9834               adjust_long_from_native_call );
9835   ins_avoid_back_to_back(AVOID_BEFORE);
9836   ins_pipe(simple_call);
9837 %}
9838 
9839 // Tail Call; Jump from runtime stub to Java code.
9840 // Also known as an 'interprocedural jump'.
9841 // Target of jump will eventually return to caller.
9842 // TailJump below removes the return address.
9843 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9844   match(TailCall jump_target method_oop );
9845 
9846   ins_cost(CALL_COST);
9847   format %{ "Jmp     $jump_target  ; NOP \t! $method_oop holds method oop" %}
9848   ins_encode(form_jmpl(jump_target));
9849   ins_avoid_back_to_back(AVOID_BEFORE);
9850   ins_pipe(tail_call);
9851 %}
9852 
9853 
9854 // Return Instruction
9855 instruct Ret() %{
9856   match(Return);
9857 
9858   // The epilogue node did the ret already.
9859   size(0);
9860   format %{ "! return" %}
9861   ins_encode();
9862   ins_pipe(empty);
9863 %}
9864 
9865 
9866 // Tail Jump; remove the return address; jump to target.
9867 // TailCall above leaves the return address around.
9868 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9869 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9870 // "restore" before this instruction (in Epilogue), we need to materialize it
9871 // in %i0.
9872 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9873   match( TailJump jump_target ex_oop );
9874   ins_cost(CALL_COST);
9875   format %{ "! discard R_O7\n\t"
9876             "Jmp     $jump_target  ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9877   ins_encode(form_jmpl_set_exception_pc(jump_target));
9878   // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9879   // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9880   // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9881   ins_avoid_back_to_back(AVOID_BEFORE);
9882   ins_pipe(tail_call);
9883 %}
9884 
9885 // Create exception oop: created by stack-crawling runtime code.
9886 // Created exception is now available to this handler, and is setup
9887 // just prior to jumping to this handler.  No code emitted.
9888 instruct CreateException( o0RegP ex_oop )
9889 %{
9890   match(Set ex_oop (CreateEx));
9891   ins_cost(0);
9892 
9893   size(0);
9894   // use the following format syntax
9895   format %{ "! exception oop is in R_O0; no code emitted" %}
9896   ins_encode();
9897   ins_pipe(empty);
9898 %}
9899 
9900 
9901 // Rethrow exception:
9902 // The exception oop will come in the first argument position.
9903 // Then JUMP (not call) to the rethrow stub code.
9904 instruct RethrowException()
9905 %{
9906   match(Rethrow);
9907   ins_cost(CALL_COST);
9908 
9909   // use the following format syntax
9910   format %{ "Jmp    rethrow_stub" %}
9911   ins_encode(enc_rethrow);
9912   ins_avoid_back_to_back(AVOID_BEFORE);
9913   ins_pipe(tail_call);
9914 %}
9915 
9916 
9917 // Die now
9918 instruct ShouldNotReachHere( )
9919 %{
9920   match(Halt);
9921   ins_cost(CALL_COST);
9922 
9923   size(4);
9924   // Use the following format syntax
9925   format %{ "ILLTRAP   ; ShouldNotReachHere" %}
9926   ins_encode( form2_illtrap() );
9927   ins_pipe(tail_call);
9928 %}
9929 
9930 // ============================================================================
9931 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
9932 // array for an instance of the superklass.  Set a hidden internal cache on a
9933 // hit (cache is checked with exposed code in gen_subtype_check()).  Return
9934 // not zero for a miss or zero for a hit.  The encoding ALSO sets flags.
9935 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9936   match(Set index (PartialSubtypeCheck sub super));
9937   effect( KILL pcc, KILL o7 );
9938   ins_cost(DEFAULT_COST*10);
9939   format %{ "CALL   PartialSubtypeCheck\n\tNOP" %}
9940   ins_encode( enc_PartialSubtypeCheck() );
9941   ins_avoid_back_to_back(AVOID_BEFORE);
9942   ins_pipe(partial_subtype_check_pipe);
9943 %}
9944 
9945 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9946   match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9947   effect( KILL idx, KILL o7 );
9948   ins_cost(DEFAULT_COST*10);
9949   format %{ "CALL   PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9950   ins_encode( enc_PartialSubtypeCheck() );
9951   ins_avoid_back_to_back(AVOID_BEFORE);
9952   ins_pipe(partial_subtype_check_pipe);
9953 %}
9954 
9955 
9956 // ============================================================================
9957 // inlined locking and unlocking
9958 
9959 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9960   match(Set pcc (FastLock object box));
9961 
9962   effect(TEMP scratch2, USE_KILL box, KILL scratch);
9963   ins_cost(100);
9964 
9965   format %{ "FASTLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
9966   ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9967   ins_pipe(long_memory_op);
9968 %}
9969 
9970 
9971 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9972   match(Set pcc (FastUnlock object box));
9973   effect(TEMP scratch2, USE_KILL box, KILL scratch);
9974   ins_cost(100);
9975 
9976   format %{ "FASTUNLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
9977   ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9978   ins_pipe(long_memory_op);
9979 %}
9980 
9981 // The encodings are generic.
9982 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9983   predicate(!use_block_zeroing(n->in(2)) );
9984   match(Set dummy (ClearArray cnt base));
9985   effect(TEMP temp, KILL ccr);
9986   ins_cost(300);
9987   format %{ "MOV    $cnt,$temp\n"
9988     "loop:   SUBcc  $temp,8,$temp\t! Count down a dword of bytes\n"
9989     "        BRge   loop\t\t! Clearing loop\n"
9990     "        STX    G0,[$base+$temp]\t! delay slot" %}
9991 
9992   ins_encode %{
9993     // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9994     Register nof_bytes_arg    = $cnt$$Register;
9995     Register nof_bytes_tmp    = $temp$$Register;
9996     Register base_pointer_arg = $base$$Register;
9997 
9998     Label loop;
9999     __ mov(nof_bytes_arg, nof_bytes_tmp);
10000 
10001     // Loop and clear, walking backwards through the array.
10002     // nof_bytes_tmp (if >0) is always the number of bytes to zero
10003     __ bind(loop);
10004     __ deccc(nof_bytes_tmp, 8);
10005     __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10006     __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10007     // %%%% this mini-loop must not cross a cache boundary!
10008   %}
10009   ins_pipe(long_memory_op);
10010 %}
10011 
10012 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10013   predicate(use_block_zeroing(n->in(2)));
10014   match(Set dummy (ClearArray cnt base));
10015   effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10016   ins_cost(300);
10017   format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
10018 
10019   ins_encode %{
10020 
10021     assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10022     Register to    = $base$$Register;
10023     Register count = $cnt$$Register;
10024 
10025     Label Ldone;
10026     __ nop(); // Separate short branches
10027     // Use BIS for zeroing (temp is not used).
10028     __ bis_zeroing(to, count, G0, Ldone);
10029     __ bind(Ldone);
10030 
10031   %}
10032   ins_pipe(long_memory_op);
10033 %}
10034 
10035 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10036   predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10037   match(Set dummy (ClearArray cnt base));
10038   effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10039   ins_cost(300);
10040   format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
10041 
10042   ins_encode %{
10043 
10044     assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10045     Register to    = $base$$Register;
10046     Register count = $cnt$$Register;
10047     Register temp  = $tmp$$Register;
10048 
10049     Label Ldone;
10050     __ nop(); // Separate short branches
10051     // Use BIS for zeroing
10052     __ bis_zeroing(to, count, temp, Ldone);
10053     __ bind(Ldone);
10054 
10055   %}
10056   ins_pipe(long_memory_op);
10057 %}
10058 
10059 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10060                          o7RegI tmp, flagsReg ccr) %{
10061   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10062   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10063   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10064   ins_cost(300);
10065   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp" %}
10066   ins_encode %{
10067     __ string_compare($str1$$Register, $str2$$Register,
10068                       $cnt1$$Register, $cnt2$$Register,
10069                       $tmp$$Register, $tmp$$Register,
10070                       $result$$Register, StrIntrinsicNode::LL);
10071   %}
10072   ins_pipe(long_memory_op);
10073 %}
10074 
10075 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10076                          o7RegI tmp, flagsReg ccr) %{
10077   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10078   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10079   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10080   ins_cost(300);
10081   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp" %}
10082   ins_encode %{
10083     __ string_compare($str1$$Register, $str2$$Register,
10084                       $cnt1$$Register, $cnt2$$Register,
10085                       $tmp$$Register, $tmp$$Register,
10086                       $result$$Register, StrIntrinsicNode::UU);
10087   %}
10088   ins_pipe(long_memory_op);
10089 %}
10090 
10091 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10092                           o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10093   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10094   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10095   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10096   ins_cost(300);
10097   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1,$tmp2" %}
10098   ins_encode %{
10099     __ string_compare($str1$$Register, $str2$$Register,
10100                       $cnt1$$Register, $cnt2$$Register,
10101                       $tmp1$$Register, $tmp2$$Register,
10102                       $result$$Register, StrIntrinsicNode::LU);
10103   %}
10104   ins_pipe(long_memory_op);
10105 %}
10106 
10107 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10108                           o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10109   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10110   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10111   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10112   ins_cost(300);
10113   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1,$tmp2" %}
10114   ins_encode %{
10115     __ string_compare($str2$$Register, $str1$$Register,
10116                       $cnt2$$Register, $cnt1$$Register,
10117                       $tmp1$$Register, $tmp2$$Register,
10118                       $result$$Register, StrIntrinsicNode::UL);
10119   %}
10120   ins_pipe(long_memory_op);
10121 %}
10122 
10123 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10124                         o7RegI tmp, flagsReg ccr) %{
10125   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10126   match(Set result (StrEquals (Binary str1 str2) cnt));
10127   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10128   ins_cost(300);
10129   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result   // KILL $tmp" %}
10130   ins_encode %{
10131     __ array_equals(false, $str1$$Register, $str2$$Register,
10132                     $cnt$$Register, $tmp$$Register,
10133                     $result$$Register, true /* byte */);
10134   %}
10135   ins_pipe(long_memory_op);
10136 %}
10137 
10138 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10139                         o7RegI tmp, flagsReg ccr) %{
10140   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10141   match(Set result (StrEquals (Binary str1 str2) cnt));
10142   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10143   ins_cost(300);
10144   format %{ "String Equals char[]  $str1,$str2,$cnt -> $result   // KILL $tmp" %}
10145   ins_encode %{
10146     __ array_equals(false, $str1$$Register, $str2$$Register,
10147                     $cnt$$Register, $tmp$$Register,
10148                     $result$$Register, false /* byte */);
10149   %}
10150   ins_pipe(long_memory_op);
10151 %}
10152 
10153 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10154                        o7RegI tmp2, flagsReg ccr) %{
10155   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10156   match(Set result (AryEq ary1 ary2));
10157   effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10158   ins_cost(300);
10159   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
10160   ins_encode %{
10161     __ array_equals(true, $ary1$$Register, $ary2$$Register,
10162                     $tmp1$$Register, $tmp2$$Register,
10163                     $result$$Register, true /* byte */);
10164   %}
10165   ins_pipe(long_memory_op);
10166 %}
10167 
10168 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10169                        o7RegI tmp2, flagsReg ccr) %{
10170   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10171   match(Set result (AryEq ary1 ary2));
10172   effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10173   ins_cost(300);
10174   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
10175   ins_encode %{
10176     __ array_equals(true, $ary1$$Register, $ary2$$Register,
10177                     $tmp1$$Register, $tmp2$$Register,
10178                     $result$$Register, false /* byte */);
10179   %}
10180   ins_pipe(long_memory_op);
10181 %}
10182 
10183 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR,
10184                        iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L,
10185                        flagsReg ccr) 
10186 %{
10187   match(Set resultR (HasNegatives pAryR iSizeR));
10188   effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr);
10189   format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %}
10190   ins_encode %{
10191     __ has_negatives($pAryR$$Register, $iSizeR$$Register, 
10192                      $resultR$$Register,
10193                      $tmp1L$$Register, $tmp2L$$Register, 
10194                      $tmp3L$$Register, $tmp4L$$Register);
10195   %}
10196   ins_pipe(long_memory_op);
10197 %}
10198 
10199 // char[] to byte[] compression
10200 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10201   predicate(UseVIS < 3);
10202   match(Set result (StrCompressedCopy src (Binary dst len)));
10203   effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10204   ins_cost(300);
10205   format %{ "String Compress $src,$dst,$len -> $result    // KILL $tmp" %}
10206   ins_encode %{
10207     Label Ldone;
10208     __ signx($len$$Register);
10209     __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10210     __ delayed()->mov($len$$Register, $result$$Register); // copy count
10211     __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10212     __ bind(Ldone);
10213   %}
10214   ins_pipe(long_memory_op);
10215 %}
10216 
10217 // fast char[] to byte[] compression using VIS instructions
10218 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10219                               iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10220                               regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10221   predicate(UseVIS >= 3);
10222   match(Set result (StrCompressedCopy src (Binary dst len)));
10223   effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10224   ins_cost(300);
10225   format %{ "String Compress Fast $src,$dst,$len -> $result    // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10226   ins_encode %{
10227     Label Ldone;
10228     __ signx($len$$Register);
10229     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10230                           $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10231                           $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10232     __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10233     __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10234     __ bind(Ldone);
10235   %}
10236   ins_pipe(long_memory_op);
10237 %}
10238 
10239 // byte[] to char[] inflation
10240 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10241                         iRegL tmp, flagsReg ccr) %{
10242   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10243   effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10244   ins_cost(300);
10245   format %{ "String Inflate $src,$dst,$len    // KILL $tmp" %}
10246   ins_encode %{
10247     Label Ldone;
10248     __ signx($len$$Register);
10249     __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10250     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10251     __ bind(Ldone);
10252   %}
10253   ins_pipe(long_memory_op);
10254 %}
10255 
10256 // fast byte[] to char[] inflation using VIS instructions
10257 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10258                              iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10259   predicate(UseVIS >= 3);
10260   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10261   effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10262   ins_cost(300);
10263   format %{ "String Inflate Fast $src,$dst,$len    // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10264   ins_encode %{
10265     Label Ldone;
10266     __ signx($len$$Register);
10267     __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10268                          $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10269     __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10270     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10271     __ bind(Ldone);
10272   %}
10273   ins_pipe(long_memory_op);
10274 %}
10275 
10276 
10277 //---------- Zeros Count Instructions ------------------------------------------
10278 
10279 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10280   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10281   match(Set dst (CountLeadingZerosI src));
10282   effect(TEMP dst, TEMP tmp, KILL cr);
10283 
10284   // x |= (x >> 1);
10285   // x |= (x >> 2);
10286   // x |= (x >> 4);
10287   // x |= (x >> 8);
10288   // x |= (x >> 16);
10289   // return (WORDBITS - popc(x));
10290   format %{ "SRL     $src,1,$tmp\t! count leading zeros (int)\n\t"
10291             "SRL     $src,0,$dst\t! 32-bit zero extend\n\t"
10292             "OR      $dst,$tmp,$dst\n\t"
10293             "SRL     $dst,2,$tmp\n\t"
10294             "OR      $dst,$tmp,$dst\n\t"
10295             "SRL     $dst,4,$tmp\n\t"
10296             "OR      $dst,$tmp,$dst\n\t"
10297             "SRL     $dst,8,$tmp\n\t"
10298             "OR      $dst,$tmp,$dst\n\t"
10299             "SRL     $dst,16,$tmp\n\t"
10300             "OR      $dst,$tmp,$dst\n\t"
10301             "POPC    $dst,$dst\n\t"
10302             "MOV     32,$tmp\n\t"
10303             "SUB     $tmp,$dst,$dst" %}
10304   ins_encode %{
10305     Register Rdst = $dst$$Register;
10306     Register Rsrc = $src$$Register;
10307     Register Rtmp = $tmp$$Register;
10308     __ srl(Rsrc, 1,    Rtmp);
10309     __ srl(Rsrc, 0,    Rdst);
10310     __ or3(Rdst, Rtmp, Rdst);
10311     __ srl(Rdst, 2,    Rtmp);
10312     __ or3(Rdst, Rtmp, Rdst);
10313     __ srl(Rdst, 4,    Rtmp);
10314     __ or3(Rdst, Rtmp, Rdst);
10315     __ srl(Rdst, 8,    Rtmp);
10316     __ or3(Rdst, Rtmp, Rdst);
10317     __ srl(Rdst, 16,   Rtmp);
10318     __ or3(Rdst, Rtmp, Rdst);
10319     __ popc(Rdst, Rdst);
10320     __ mov(BitsPerInt, Rtmp);
10321     __ sub(Rtmp, Rdst, Rdst);
10322   %}
10323   ins_pipe(ialu_reg);
10324 %}
10325 
10326 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10327   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10328   match(Set dst (CountLeadingZerosL src));
10329   effect(TEMP dst, TEMP tmp, KILL cr);
10330 
10331   // x |= (x >> 1);
10332   // x |= (x >> 2);
10333   // x |= (x >> 4);
10334   // x |= (x >> 8);
10335   // x |= (x >> 16);
10336   // x |= (x >> 32);
10337   // return (WORDBITS - popc(x));
10338   format %{ "SRLX    $src,1,$tmp\t! count leading zeros (long)\n\t"
10339             "OR      $src,$tmp,$dst\n\t"
10340             "SRLX    $dst,2,$tmp\n\t"
10341             "OR      $dst,$tmp,$dst\n\t"
10342             "SRLX    $dst,4,$tmp\n\t"
10343             "OR      $dst,$tmp,$dst\n\t"
10344             "SRLX    $dst,8,$tmp\n\t"
10345             "OR      $dst,$tmp,$dst\n\t"
10346             "SRLX    $dst,16,$tmp\n\t"
10347             "OR      $dst,$tmp,$dst\n\t"
10348             "SRLX    $dst,32,$tmp\n\t"
10349             "OR      $dst,$tmp,$dst\n\t"
10350             "POPC    $dst,$dst\n\t"
10351             "MOV     64,$tmp\n\t"
10352             "SUB     $tmp,$dst,$dst" %}
10353   ins_encode %{
10354     Register Rdst = $dst$$Register;
10355     Register Rsrc = $src$$Register;
10356     Register Rtmp = $tmp$$Register;
10357     __ srlx(Rsrc, 1,    Rtmp);
10358     __ or3( Rsrc, Rtmp, Rdst);
10359     __ srlx(Rdst, 2,    Rtmp);
10360     __ or3( Rdst, Rtmp, Rdst);
10361     __ srlx(Rdst, 4,    Rtmp);
10362     __ or3( Rdst, Rtmp, Rdst);
10363     __ srlx(Rdst, 8,    Rtmp);
10364     __ or3( Rdst, Rtmp, Rdst);
10365     __ srlx(Rdst, 16,   Rtmp);
10366     __ or3( Rdst, Rtmp, Rdst);
10367     __ srlx(Rdst, 32,   Rtmp);
10368     __ or3( Rdst, Rtmp, Rdst);
10369     __ popc(Rdst, Rdst);
10370     __ mov(BitsPerLong, Rtmp);
10371     __ sub(Rtmp, Rdst, Rdst);
10372   %}
10373   ins_pipe(ialu_reg);
10374 %}
10375 
10376 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10377   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10378   match(Set dst (CountTrailingZerosI src));
10379   effect(TEMP dst, KILL cr);
10380 
10381   // return popc(~x & (x - 1));
10382   format %{ "SUB     $src,1,$dst\t! count trailing zeros (int)\n\t"
10383             "ANDN    $dst,$src,$dst\n\t"
10384             "SRL     $dst,R_G0,$dst\n\t"
10385             "POPC    $dst,$dst" %}
10386   ins_encode %{
10387     Register Rdst = $dst$$Register;
10388     Register Rsrc = $src$$Register;
10389     __ sub(Rsrc, 1, Rdst);
10390     __ andn(Rdst, Rsrc, Rdst);
10391     __ srl(Rdst, G0, Rdst);
10392     __ popc(Rdst, Rdst);
10393   %}
10394   ins_pipe(ialu_reg);
10395 %}
10396 
10397 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10398   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10399   match(Set dst (CountTrailingZerosL src));
10400   effect(TEMP dst, KILL cr);
10401 
10402   // return popc(~x & (x - 1));
10403   format %{ "SUB     $src,1,$dst\t! count trailing zeros (long)\n\t"
10404             "ANDN    $dst,$src,$dst\n\t"
10405             "POPC    $dst,$dst" %}
10406   ins_encode %{
10407     Register Rdst = $dst$$Register;
10408     Register Rsrc = $src$$Register;
10409     __ sub(Rsrc, 1, Rdst);
10410     __ andn(Rdst, Rsrc, Rdst);
10411     __ popc(Rdst, Rdst);
10412   %}
10413   ins_pipe(ialu_reg);
10414 %}
10415 
10416 
10417 //---------- Population Count Instructions -------------------------------------
10418 
10419 instruct popCountI(iRegIsafe dst, iRegI src) %{
10420   predicate(UsePopCountInstruction);
10421   match(Set dst (PopCountI src));
10422 
10423   format %{ "SRL    $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10424             "POPC   $dst, $dst" %}
10425   ins_encode %{
10426     __ srl($src$$Register, G0, $dst$$Register);
10427     __ popc($dst$$Register, $dst$$Register);
10428   %}
10429   ins_pipe(ialu_reg);
10430 %}
10431 
10432 // Note: Long.bitCount(long) returns an int.
10433 instruct popCountL(iRegIsafe dst, iRegL src) %{
10434   predicate(UsePopCountInstruction);
10435   match(Set dst (PopCountL src));
10436 
10437   format %{ "POPC   $src, $dst" %}
10438   ins_encode %{
10439     __ popc($src$$Register, $dst$$Register);
10440   %}
10441   ins_pipe(ialu_reg);
10442 %}
10443 
10444 
10445 // ============================================================================
10446 //------------Bytes reverse--------------------------------------------------
10447 
10448 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10449   match(Set dst (ReverseBytesI src));
10450 
10451   // Op cost is artificially doubled to make sure that load or store
10452   // instructions are preferred over this one which requires a spill
10453   // onto a stack slot.
10454   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10455   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
10456 
10457   ins_encode %{
10458     __ set($src$$disp + STACK_BIAS, O7);
10459     __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10460   %}
10461   ins_pipe( iload_mem );
10462 %}
10463 
10464 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10465   match(Set dst (ReverseBytesL src));
10466 
10467   // Op cost is artificially doubled to make sure that load or store
10468   // instructions are preferred over this one which requires a spill
10469   // onto a stack slot.
10470   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10471   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
10472 
10473   ins_encode %{
10474     __ set($src$$disp + STACK_BIAS, O7);
10475     __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10476   %}
10477   ins_pipe( iload_mem );
10478 %}
10479 
10480 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10481   match(Set dst (ReverseBytesUS src));
10482 
10483   // Op cost is artificially doubled to make sure that load or store
10484   // instructions are preferred over this one which requires a spill
10485   // onto a stack slot.
10486   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10487   format %{ "LDUHA  $src, $dst\t!asi=primary_little\n\t" %}
10488 
10489   ins_encode %{
10490     // the value was spilled as an int so bias the load
10491     __ set($src$$disp + STACK_BIAS + 2, O7);
10492     __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10493   %}
10494   ins_pipe( iload_mem );
10495 %}
10496 
10497 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10498   match(Set dst (ReverseBytesS src));
10499 
10500   // Op cost is artificially doubled to make sure that load or store
10501   // instructions are preferred over this one which requires a spill
10502   // onto a stack slot.
10503   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10504   format %{ "LDSHA  $src, $dst\t!asi=primary_little\n\t" %}
10505 
10506   ins_encode %{
10507     // the value was spilled as an int so bias the load
10508     __ set($src$$disp + STACK_BIAS + 2, O7);
10509     __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10510   %}
10511   ins_pipe( iload_mem );
10512 %}
10513 
10514 // Load Integer reversed byte order
10515 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10516   match(Set dst (ReverseBytesI (LoadI src)));
10517 
10518   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10519   size(4);
10520   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
10521 
10522   ins_encode %{
10523     __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10524   %}
10525   ins_pipe(iload_mem);
10526 %}
10527 
10528 // Load Long - aligned and reversed
10529 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10530   match(Set dst (ReverseBytesL (LoadL src)));
10531 
10532   ins_cost(MEMORY_REF_COST);
10533   size(4);
10534   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
10535 
10536   ins_encode %{
10537     __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10538   %}
10539   ins_pipe(iload_mem);
10540 %}
10541 
10542 // Load unsigned short / char reversed byte order
10543 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10544   match(Set dst (ReverseBytesUS (LoadUS src)));
10545 
10546   ins_cost(MEMORY_REF_COST);
10547   size(4);
10548   format %{ "LDUHA  $src, $dst\t!asi=primary_little" %}
10549 
10550   ins_encode %{
10551     __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10552   %}
10553   ins_pipe(iload_mem);
10554 %}
10555 
10556 // Load short reversed byte order
10557 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10558   match(Set dst (ReverseBytesS (LoadS src)));
10559 
10560   ins_cost(MEMORY_REF_COST);
10561   size(4);
10562   format %{ "LDSHA  $src, $dst\t!asi=primary_little" %}
10563 
10564   ins_encode %{
10565     __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10566   %}
10567   ins_pipe(iload_mem);
10568 %}
10569 
10570 // Store Integer reversed byte order
10571 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10572   match(Set dst (StoreI dst (ReverseBytesI src)));
10573 
10574   ins_cost(MEMORY_REF_COST);
10575   size(4);
10576   format %{ "STWA   $src, $dst\t!asi=primary_little" %}
10577 
10578   ins_encode %{
10579     __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10580   %}
10581   ins_pipe(istore_mem_reg);
10582 %}
10583 
10584 // Store Long reversed byte order
10585 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10586   match(Set dst (StoreL dst (ReverseBytesL src)));
10587 
10588   ins_cost(MEMORY_REF_COST);
10589   size(4);
10590   format %{ "STXA   $src, $dst\t!asi=primary_little" %}
10591 
10592   ins_encode %{
10593     __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10594   %}
10595   ins_pipe(istore_mem_reg);
10596 %}
10597 
10598 // Store unsighed short/char reversed byte order
10599 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10600   match(Set dst (StoreC dst (ReverseBytesUS src)));
10601 
10602   ins_cost(MEMORY_REF_COST);
10603   size(4);
10604   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10605 
10606   ins_encode %{
10607     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10608   %}
10609   ins_pipe(istore_mem_reg);
10610 %}
10611 
10612 // Store short reversed byte order
10613 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10614   match(Set dst (StoreC dst (ReverseBytesS src)));
10615 
10616   ins_cost(MEMORY_REF_COST);
10617   size(4);
10618   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10619 
10620   ins_encode %{
10621     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10622   %}
10623   ins_pipe(istore_mem_reg);
10624 %}
10625 
10626 // ====================VECTOR INSTRUCTIONS=====================================
10627 
10628 // Load Aligned Packed values into a Double Register
10629 instruct loadV8(regD dst, memory mem) %{
10630   predicate(n->as_LoadVector()->memory_size() == 8);
10631   match(Set dst (LoadVector mem));
10632   ins_cost(MEMORY_REF_COST);
10633   size(4);
10634   format %{ "LDDF   $mem,$dst\t! load vector (8 bytes)" %}
10635   ins_encode %{
10636     __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10637   %}
10638   ins_pipe(floadD_mem);
10639 %}
10640 
10641 // Store Vector in Double register to memory
10642 instruct storeV8(memory mem, regD src) %{
10643   predicate(n->as_StoreVector()->memory_size() == 8);
10644   match(Set mem (StoreVector mem src));
10645   ins_cost(MEMORY_REF_COST);
10646   size(4);
10647   format %{ "STDF   $src,$mem\t! store vector (8 bytes)" %}
10648   ins_encode %{
10649     __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10650   %}
10651   ins_pipe(fstoreD_mem_reg);
10652 %}
10653 
10654 // Store Zero into vector in memory
10655 instruct storeV8B_zero(memory mem, immI0 zero) %{
10656   predicate(n->as_StoreVector()->memory_size() == 8);
10657   match(Set mem (StoreVector mem (ReplicateB zero)));
10658   ins_cost(MEMORY_REF_COST);
10659   size(4);
10660   format %{ "STX    $zero,$mem\t! store zero vector (8 bytes)" %}
10661   ins_encode %{
10662     __ stx(G0, $mem$$Address);
10663   %}
10664   ins_pipe(fstoreD_mem_zero);
10665 %}
10666 
10667 instruct storeV4S_zero(memory mem, immI0 zero) %{
10668   predicate(n->as_StoreVector()->memory_size() == 8);
10669   match(Set mem (StoreVector mem (ReplicateS zero)));
10670   ins_cost(MEMORY_REF_COST);
10671   size(4);
10672   format %{ "STX    $zero,$mem\t! store zero vector (4 shorts)" %}
10673   ins_encode %{
10674     __ stx(G0, $mem$$Address);
10675   %}
10676   ins_pipe(fstoreD_mem_zero);
10677 %}
10678 
10679 instruct storeV2I_zero(memory mem, immI0 zero) %{
10680   predicate(n->as_StoreVector()->memory_size() == 8);
10681   match(Set mem (StoreVector mem (ReplicateI zero)));
10682   ins_cost(MEMORY_REF_COST);
10683   size(4);
10684   format %{ "STX    $zero,$mem\t! store zero vector (2 ints)" %}
10685   ins_encode %{
10686     __ stx(G0, $mem$$Address);
10687   %}
10688   ins_pipe(fstoreD_mem_zero);
10689 %}
10690 
10691 instruct storeV2F_zero(memory mem, immF0 zero) %{
10692   predicate(n->as_StoreVector()->memory_size() == 8);
10693   match(Set mem (StoreVector mem (ReplicateF zero)));
10694   ins_cost(MEMORY_REF_COST);
10695   size(4);
10696   format %{ "STX    $zero,$mem\t! store zero vector (2 floats)" %}
10697   ins_encode %{
10698     __ stx(G0, $mem$$Address);
10699   %}
10700   ins_pipe(fstoreD_mem_zero);
10701 %}
10702 
10703 // Replicate scalar to packed byte values into Double register
10704 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10705   predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10706   match(Set dst (ReplicateB src));
10707   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10708   format %{ "SLLX  $src,56,$tmp\n\t"
10709             "SRLX  $tmp, 8,$tmp2\n\t"
10710             "OR    $tmp,$tmp2,$tmp\n\t"
10711             "SRLX  $tmp,16,$tmp2\n\t"
10712             "OR    $tmp,$tmp2,$tmp\n\t"
10713             "SRLX  $tmp,32,$tmp2\n\t"
10714             "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10715             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10716   ins_encode %{
10717     Register Rsrc = $src$$Register;
10718     Register Rtmp = $tmp$$Register;
10719     Register Rtmp2 = $tmp2$$Register;
10720     __ sllx(Rsrc,    56, Rtmp);
10721     __ srlx(Rtmp,     8, Rtmp2);
10722     __ or3 (Rtmp, Rtmp2, Rtmp);
10723     __ srlx(Rtmp,    16, Rtmp2);
10724     __ or3 (Rtmp, Rtmp2, Rtmp);
10725     __ srlx(Rtmp,    32, Rtmp2);
10726     __ or3 (Rtmp, Rtmp2, Rtmp);
10727     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10728   %}
10729   ins_pipe(ialu_reg);
10730 %}
10731 
10732 // Replicate scalar to packed byte values into Double stack
10733 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10734   predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10735   match(Set dst (ReplicateB src));
10736   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10737   format %{ "SLLX  $src,56,$tmp\n\t"
10738             "SRLX  $tmp, 8,$tmp2\n\t"
10739             "OR    $tmp,$tmp2,$tmp\n\t"
10740             "SRLX  $tmp,16,$tmp2\n\t"
10741             "OR    $tmp,$tmp2,$tmp\n\t"
10742             "SRLX  $tmp,32,$tmp2\n\t"
10743             "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10744             "STX   $tmp,$dst\t! regL to stkD" %}
10745   ins_encode %{
10746     Register Rsrc = $src$$Register;
10747     Register Rtmp = $tmp$$Register;
10748     Register Rtmp2 = $tmp2$$Register;
10749     __ sllx(Rsrc,    56, Rtmp);
10750     __ srlx(Rtmp,     8, Rtmp2);
10751     __ or3 (Rtmp, Rtmp2, Rtmp);
10752     __ srlx(Rtmp,    16, Rtmp2);
10753     __ or3 (Rtmp, Rtmp2, Rtmp);
10754     __ srlx(Rtmp,    32, Rtmp2);
10755     __ or3 (Rtmp, Rtmp2, Rtmp);
10756     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10757     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10758   %}
10759   ins_pipe(ialu_reg);
10760 %}
10761 
10762 // Replicate scalar constant to packed byte values in Double register
10763 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10764   predicate(n->as_Vector()->length() == 8);
10765   match(Set dst (ReplicateB con));
10766   effect(KILL tmp);
10767   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10768   ins_encode %{
10769     // XXX This is a quick fix for 6833573.
10770     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10771     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10772     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10773   %}
10774   ins_pipe(loadConFD);
10775 %}
10776 
10777 // Replicate scalar to packed char/short values into Double register
10778 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10779   predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10780   match(Set dst (ReplicateS src));
10781   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10782   format %{ "SLLX  $src,48,$tmp\n\t"
10783             "SRLX  $tmp,16,$tmp2\n\t"
10784             "OR    $tmp,$tmp2,$tmp\n\t"
10785             "SRLX  $tmp,32,$tmp2\n\t"
10786             "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10787             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10788   ins_encode %{
10789     Register Rsrc = $src$$Register;
10790     Register Rtmp = $tmp$$Register;
10791     Register Rtmp2 = $tmp2$$Register;
10792     __ sllx(Rsrc,    48, Rtmp);
10793     __ srlx(Rtmp,    16, Rtmp2);
10794     __ or3 (Rtmp, Rtmp2, Rtmp);
10795     __ srlx(Rtmp,    32, Rtmp2);
10796     __ or3 (Rtmp, Rtmp2, Rtmp);
10797     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10798   %}
10799   ins_pipe(ialu_reg);
10800 %}
10801 
10802 // Replicate scalar to packed char/short values into Double stack
10803 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10804   predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10805   match(Set dst (ReplicateS src));
10806   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10807   format %{ "SLLX  $src,48,$tmp\n\t"
10808             "SRLX  $tmp,16,$tmp2\n\t"
10809             "OR    $tmp,$tmp2,$tmp\n\t"
10810             "SRLX  $tmp,32,$tmp2\n\t"
10811             "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10812             "STX   $tmp,$dst\t! regL to stkD" %}
10813   ins_encode %{
10814     Register Rsrc = $src$$Register;
10815     Register Rtmp = $tmp$$Register;
10816     Register Rtmp2 = $tmp2$$Register;
10817     __ sllx(Rsrc,    48, Rtmp);
10818     __ srlx(Rtmp,    16, Rtmp2);
10819     __ or3 (Rtmp, Rtmp2, Rtmp);
10820     __ srlx(Rtmp,    32, Rtmp2);
10821     __ or3 (Rtmp, Rtmp2, Rtmp);
10822     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10823     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10824   %}
10825   ins_pipe(ialu_reg);
10826 %}
10827 
10828 // Replicate scalar constant to packed char/short values in Double register
10829 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10830   predicate(n->as_Vector()->length() == 4);
10831   match(Set dst (ReplicateS con));
10832   effect(KILL tmp);
10833   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10834   ins_encode %{
10835     // XXX This is a quick fix for 6833573.
10836     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10837     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10838     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10839   %}
10840   ins_pipe(loadConFD);
10841 %}
10842 
10843 // Replicate scalar to packed int values into Double register
10844 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10845   predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10846   match(Set dst (ReplicateI src));
10847   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10848   format %{ "SLLX  $src,32,$tmp\n\t"
10849             "SRLX  $tmp,32,$tmp2\n\t"
10850             "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10851             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10852   ins_encode %{
10853     Register Rsrc = $src$$Register;
10854     Register Rtmp = $tmp$$Register;
10855     Register Rtmp2 = $tmp2$$Register;
10856     __ sllx(Rsrc,    32, Rtmp);
10857     __ srlx(Rtmp,    32, Rtmp2);
10858     __ or3 (Rtmp, Rtmp2, Rtmp);
10859     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10860   %}
10861   ins_pipe(ialu_reg);
10862 %}
10863 
10864 // Replicate scalar to packed int values into Double stack
10865 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10866   predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10867   match(Set dst (ReplicateI src));
10868   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10869   format %{ "SLLX  $src,32,$tmp\n\t"
10870             "SRLX  $tmp,32,$tmp2\n\t"
10871             "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10872             "STX   $tmp,$dst\t! regL to stkD" %}
10873   ins_encode %{
10874     Register Rsrc = $src$$Register;
10875     Register Rtmp = $tmp$$Register;
10876     Register Rtmp2 = $tmp2$$Register;
10877     __ sllx(Rsrc,    32, Rtmp);
10878     __ srlx(Rtmp,    32, Rtmp2);
10879     __ or3 (Rtmp, Rtmp2, Rtmp);
10880     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10881     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10882   %}
10883   ins_pipe(ialu_reg);
10884 %}
10885 
10886 // Replicate scalar zero constant to packed int values in Double register
10887 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10888   predicate(n->as_Vector()->length() == 2);
10889   match(Set dst (ReplicateI con));
10890   effect(KILL tmp);
10891   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10892   ins_encode %{
10893     // XXX This is a quick fix for 6833573.
10894     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10895     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10896     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10897   %}
10898   ins_pipe(loadConFD);
10899 %}
10900 
10901 // Replicate scalar to packed float values into Double stack
10902 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10903   predicate(n->as_Vector()->length() == 2);
10904   match(Set dst (ReplicateF src));
10905   ins_cost(MEMORY_REF_COST*2);
10906   format %{ "STF    $src,$dst.hi\t! packed2F\n\t"
10907             "STF    $src,$dst.lo" %}
10908   opcode(Assembler::stf_op3);
10909   ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10910   ins_pipe(fstoreF_stk_reg);
10911 %}
10912 
10913 // Replicate scalar zero constant to packed float values in Double register
10914 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10915   predicate(n->as_Vector()->length() == 2);
10916   match(Set dst (ReplicateF con));
10917   effect(KILL tmp);
10918   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10919   ins_encode %{
10920     // XXX This is a quick fix for 6833573.
10921     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10922     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10923     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10924   %}
10925   ins_pipe(loadConFD);
10926 %}
10927 
10928 //----------PEEPHOLE RULES-----------------------------------------------------
10929 // These must follow all instruction definitions as they use the names
10930 // defined in the instructions definitions.
10931 //
10932 // peepmatch ( root_instr_name [preceding_instruction]* );
10933 //
10934 // peepconstraint %{
10935 // (instruction_number.operand_name relational_op instruction_number.operand_name
10936 //  [, ...] );
10937 // // instruction numbers are zero-based using left to right order in peepmatch
10938 //
10939 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
10940 // // provide an instruction_number.operand_name for each operand that appears
10941 // // in the replacement instruction's match rule
10942 //
10943 // ---------VM FLAGS---------------------------------------------------------
10944 //
10945 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10946 //
10947 // Each peephole rule is given an identifying number starting with zero and
10948 // increasing by one in the order seen by the parser.  An individual peephole
10949 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10950 // on the command-line.
10951 //
10952 // ---------CURRENT LIMITATIONS----------------------------------------------
10953 //
10954 // Only match adjacent instructions in same basic block
10955 // Only equality constraints
10956 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10957 // Only one replacement instruction
10958 //
10959 // ---------EXAMPLE----------------------------------------------------------
10960 //
10961 // // pertinent parts of existing instructions in architecture description
10962 // instruct movI(eRegI dst, eRegI src) %{
10963 //   match(Set dst (CopyI src));
10964 // %}
10965 //
10966 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10967 //   match(Set dst (AddI dst src));
10968 //   effect(KILL cr);
10969 // %}
10970 //
10971 // // Change (inc mov) to lea
10972 // peephole %{
10973 //   // increment preceeded by register-register move
10974 //   peepmatch ( incI_eReg movI );
10975 //   // require that the destination register of the increment
10976 //   // match the destination register of the move
10977 //   peepconstraint ( 0.dst == 1.dst );
10978 //   // construct a replacement instruction that sets
10979 //   // the destination to ( move's source register + one )
10980 //   peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10981 // %}
10982 //
10983 
10984 // // Change load of spilled value to only a spill
10985 // instruct storeI(memory mem, eRegI src) %{
10986 //   match(Set mem (StoreI mem src));
10987 // %}
10988 //
10989 // instruct loadI(eRegI dst, memory mem) %{
10990 //   match(Set dst (LoadI mem));
10991 // %}
10992 //
10993 // peephole %{
10994 //   peepmatch ( loadI storeI );
10995 //   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10996 //   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10997 // %}
10998 
10999 //----------SMARTSPILL RULES---------------------------------------------------
11000 // These must follow all instruction definitions as they use the names
11001 // defined in the instructions definitions.
11002 //
11003 // SPARC will probably not have any of these rules due to RISC instruction set.
11004 
11005 //----------PIPELINE-----------------------------------------------------------
11006 // Rules which define the behavior of the target architectures pipeline.