32 case Component::DEF:
33 case Component::USE_DEF: return true; break;
34 }
35 return false;
36 }
37
38 // Define an array containing the machine register names, strings.
39 static void defineRegNames(FILE *fp, RegisterForm *registers) {
40 if (registers) {
41 fprintf(fp,"\n");
42 fprintf(fp,"// An array of character pointers to machine register names.\n");
43 fprintf(fp,"const char *Matcher::regName[REG_COUNT] = {\n");
44
45 // Output the register name for each register in the allocation classes
46 RegDef *reg_def = NULL;
47 RegDef *next = NULL;
48 registers->reset_RegDefs();
49 for (reg_def = registers->iter_RegDefs(); reg_def != NULL; reg_def = next) {
50 next = registers->iter_RegDefs();
51 const char *comma = (next != NULL) ? "," : " // no trailing comma";
52 fprintf(fp," \"%s\"%s\n", reg_def->_regname, comma);
53 }
54
55 // Finish defining enumeration
56 fprintf(fp,"};\n");
57
58 fprintf(fp,"\n");
59 fprintf(fp,"// An array of character pointers to machine register names.\n");
60 fprintf(fp,"const VMReg OptoReg::opto2vm[REG_COUNT] = {\n");
61 reg_def = NULL;
62 next = NULL;
63 registers->reset_RegDefs();
64 for (reg_def = registers->iter_RegDefs(); reg_def != NULL; reg_def = next) {
65 next = registers->iter_RegDefs();
66 const char *comma = (next != NULL) ? "," : " // no trailing comma";
67 fprintf(fp,"\t%s%s\n", reg_def->_concrete, comma);
68 }
69 // Finish defining array
70 fprintf(fp,"\t};\n");
71 fprintf(fp,"\n");
72
1696 }
1697 } else if (comp->isa(Component::KILL)) {
1698 fprintf(fp, " // DEF/KILL %s\n", comp->_name);
1699
1700 if (!declared_kill) {
1701 // Define the variable "kill" to hold new MachProjNodes
1702 fprintf(fp, " MachProjNode *kill;\n");
1703 declared_kill = true;
1704 }
1705
1706 assert(op, "Support additional KILLS for base operands");
1707 const char *regmask = reg_mask(*op);
1708 const char *ideal_type = op->ideal_type(_globalNames, _register);
1709
1710 if (!op->is_bound_register()) {
1711 syntax_err(node->_linenum, "In %s only bound registers can be killed: %s %s\n",
1712 node->_ident, comp->_type, comp->_name);
1713 }
1714
1715 fprintf(fp," kill = ");
1716 fprintf(fp,"new MachProjNode( %s, %d, (%s), Op_%s );\n",
1717 machNode, proj_no++, regmask, ideal_type);
1718 fprintf(fp," proj_list.push(kill);\n");
1719 }
1720 }
1721 }
1722
1723 if( !node->expands() && node->_matrule != NULL ) {
1724 // Remove duplicated operands and inputs which use the same name.
1725 // Seach through match operands for the same name usage.
1726 uint cur_num_opnds = node->num_opnds();
1727 if( cur_num_opnds > 1 && cur_num_opnds != node->num_unique_opnds() ) {
1728 Component *comp = NULL;
1729 // Build mapping from num_edges to local variables
1730 fprintf(fp," unsigned num0 = 0;\n");
1731 for( i = 1; i < cur_num_opnds; i++ ) {
1732 fprintf(fp," unsigned num%d = opnd_array(%d)->num_edges();",i,i);
1733 fprintf(fp, " \t// %s\n", node->opnd_ident(i));
1734 }
1735 // Build a mapping from operand index to input edges
1736 fprintf(fp," unsigned idx0 = oper_input_base();\n");
3620 // Output #defines from definition block
3621 globalDefs().print_defines(fp_hpp);
3622
3623 if (_pre_header.count() > 0)
3624 _pre_header.output(fp_hpp);
3625 }
3626
3627 //---------------------------buildReduceMaps-----------------------------
3628 // Build mapping from enumeration for densely packed operands
3629 // TO result and child types.
3630 void ArchDesc::buildReduceMaps(FILE *fp_hpp, FILE *fp_cpp) {
3631 RegDef *rdef;
3632 RegDef *next;
3633
3634 // The emit bodies currently require functions defined in the source block.
3635
3636 // Build external declarations for mappings
3637 fprintf(fp_hpp, "\n");
3638 fprintf(fp_hpp, "extern const char register_save_policy[];\n");
3639 fprintf(fp_hpp, "extern const char c_reg_save_policy[];\n");
3640 fprintf(fp_hpp, "extern const int register_save_type[];\n");
3641 fprintf(fp_hpp, "\n");
3642
3643 // Construct Save-Policy array
3644 fprintf(fp_cpp, "// Map from machine-independent register number to register_save_policy\n");
3645 fprintf(fp_cpp, "const char register_save_policy[] = {\n");
3646 _register->reset_RegDefs();
3647 for( rdef = _register->iter_RegDefs(); rdef != NULL; rdef = next ) {
3648 next = _register->iter_RegDefs();
3649 char policy = reg_save_policy(rdef->_callconv);
3650 const char *comma = (next != NULL) ? "," : " // no trailing comma";
3651 fprintf(fp_cpp, " '%c'%s // %s\n", policy, comma, rdef->_regname);
3652 }
3653 fprintf(fp_cpp, "};\n\n");
3654
3655 // Construct Native Save-Policy array
3656 fprintf(fp_cpp, "// Map from machine-independent register number to c_reg_save_policy\n");
3657 fprintf(fp_cpp, "const char c_reg_save_policy[] = {\n");
3658 _register->reset_RegDefs();
3659 for( rdef = _register->iter_RegDefs(); rdef != NULL; rdef = next ) {
3660 next = _register->iter_RegDefs();
3661 char policy = reg_save_policy(rdef->_c_conv);
3662 const char *comma = (next != NULL) ? "," : " // no trailing comma";
3663 fprintf(fp_cpp, " '%c'%s // %s\n", policy, comma, rdef->_regname);
3664 }
3665 fprintf(fp_cpp, "};\n\n");
3666
3667 // Construct Register Save Type array
3668 fprintf(fp_cpp, "// Map from machine-independent register number to register_save_type\n");
3669 fprintf(fp_cpp, "const int register_save_type[] = {\n");
3670 _register->reset_RegDefs();
3671 for( rdef = _register->iter_RegDefs(); rdef != NULL; rdef = next ) {
3672 next = _register->iter_RegDefs();
3673 const char *comma = (next != NULL) ? "," : " // no trailing comma";
3674 fprintf(fp_cpp, " %s%s\n", rdef->_idealtype, comma);
3675 }
3676 fprintf(fp_cpp, "};\n\n");
3677
3678 // Construct the table for reduceOp
3679 OutputReduceOp output_reduce_op(fp_hpp, fp_cpp, _globalNames, *this);
3680 build_map(output_reduce_op);
3681 // Construct the table for leftOp
3682 OutputLeftOp output_left_op(fp_hpp, fp_cpp, _globalNames, *this);
3683 build_map(output_left_op);
3684 // Construct the table for rightOp
3685 OutputRightOp output_right_op(fp_hpp, fp_cpp, _globalNames, *this);
3686 build_map(output_right_op);
3687 // Construct the table of rule names
3688 OutputRuleName output_rule_name(fp_hpp, fp_cpp, _globalNames, *this);
3689 build_map(output_rule_name);
3690 // Construct the boolean table for subsumed operands
3691 OutputSwallowed output_swallowed(fp_hpp, fp_cpp, _globalNames, *this);
3692 build_map(output_swallowed);
3693 // // // Preserve in case we decide to use this table instead of another
3694 //// Construct the boolean table for instruction chain rules
4080
4081 // Generate the default case for switch(opcode)
4082 fprintf(fp_cpp, " \n");
4083 fprintf(fp_cpp, " default:\n");
4084 fprintf(fp_cpp, " fprintf(stderr, \"Default MachNode Generator invoked for: \\n\");\n");
4085 fprintf(fp_cpp, " fprintf(stderr, \" opcode = %cd\\n\", opcode);\n", '%');
4086 fprintf(fp_cpp, " break;\n");
4087 fprintf(fp_cpp, " };\n");
4088
4089 // Generate the closing for method Matcher::MachNodeGenerator
4090 fprintf(fp_cpp, " return NULL;\n");
4091 fprintf(fp_cpp, "}\n");
4092 }
4093
4094
4095 //---------------------------buildInstructMatchCheck--------------------------
4096 // Output the method to Matcher which checks whether or not a specific
4097 // instruction has a matching rule for the host architecture.
4098 void ArchDesc::buildInstructMatchCheck(FILE *fp_cpp) const {
4099 fprintf(fp_cpp, "\n\n");
4100 fprintf(fp_cpp, "const bool Matcher::has_match_rule(int opcode) {\n");
4101 fprintf(fp_cpp, " assert(_last_machine_leaf < opcode && opcode < _last_opcode, \"opcode in range\");\n");
4102 fprintf(fp_cpp, " return _hasMatchRule[opcode];\n");
4103 fprintf(fp_cpp, "}\n\n");
4104
4105 fprintf(fp_cpp, "const bool Matcher::_hasMatchRule[_last_opcode] = {\n");
4106 int i;
4107 for (i = 0; i < _last_opcode - 1; i++) {
4108 fprintf(fp_cpp, " %-5s, // %s\n",
4109 _has_match_rule[i] ? "true" : "false",
4110 NodeClassNames[i]);
4111 }
4112 fprintf(fp_cpp, " %-5s // %s\n",
4113 _has_match_rule[i] ? "true" : "false",
4114 NodeClassNames[i]);
4115 fprintf(fp_cpp, "};\n");
4116 }
4117
4118 //---------------------------buildFrameMethods---------------------------------
4119 // Output the methods to Matcher which specify frame behavior
4120 void ArchDesc::buildFrameMethods(FILE *fp_cpp) {
4121 fprintf(fp_cpp,"\n\n");
4122 // Stack Direction
4123 fprintf(fp_cpp,"bool Matcher::stack_direction() const { return %s; }\n\n",
4124 _frame->_direction ? "true" : "false");
4125 // Sync Stack Slots
4126 fprintf(fp_cpp,"int Compile::sync_stack_slots() const { return %s; }\n\n",
4127 _frame->_sync_stack_slots);
4139 _frame->_return_addr);
4140 }
4141 // Java Stack Slot Preservation
4142 fprintf(fp_cpp,"uint Compile::in_preserve_stack_slots() ");
4143 fprintf(fp_cpp,"{ return %s; }\n\n", _frame->_in_preserve_slots);
4144 // Top Of Stack Slot Preservation, for both Java and C
4145 fprintf(fp_cpp,"uint Compile::out_preserve_stack_slots() ");
4146 fprintf(fp_cpp,"{ return SharedRuntime::out_preserve_stack_slots(); }\n\n");
4147 // varargs C out slots killed
4148 fprintf(fp_cpp,"uint Compile::varargs_C_out_slots_killed() const ");
4149 fprintf(fp_cpp,"{ return %s; }\n\n", _frame->_varargs_C_out_slots_killed);
4150 // Java Argument Position
4151 fprintf(fp_cpp,"void Matcher::calling_convention(BasicType *sig_bt, VMRegPair *regs, uint length, bool is_outgoing) {\n");
4152 fprintf(fp_cpp,"%s\n", _frame->_calling_convention);
4153 fprintf(fp_cpp,"}\n\n");
4154 // Native Argument Position
4155 fprintf(fp_cpp,"void Matcher::c_calling_convention(BasicType *sig_bt, VMRegPair *regs, uint length) {\n");
4156 fprintf(fp_cpp,"%s\n", _frame->_c_calling_convention);
4157 fprintf(fp_cpp,"}\n\n");
4158 // Java Return Value Location
4159 fprintf(fp_cpp,"OptoRegPair Matcher::return_value(int ideal_reg, bool is_outgoing) {\n");
4160 fprintf(fp_cpp,"%s\n", _frame->_return_value);
4161 fprintf(fp_cpp,"}\n\n");
4162 // Native Return Value Location
4163 fprintf(fp_cpp,"OptoRegPair Matcher::c_return_value(int ideal_reg, bool is_outgoing) {\n");
4164 fprintf(fp_cpp,"%s\n", _frame->_c_return_value);
4165 fprintf(fp_cpp,"}\n\n");
4166
4167 // Inline Cache Register, mask definition, and encoding
4168 fprintf(fp_cpp,"OptoReg::Name Matcher::inline_cache_reg() {");
4169 fprintf(fp_cpp," return OptoReg::Name(%s_num); }\n\n",
4170 _frame->_inline_cache_reg);
4171 fprintf(fp_cpp,"int Matcher::inline_cache_reg_encode() {");
4172 fprintf(fp_cpp," return _regEncode[inline_cache_reg()]; }\n\n");
4173
4174 // Interpreter's Method Oop Register, mask definition, and encoding
4175 fprintf(fp_cpp,"OptoReg::Name Matcher::interpreter_method_oop_reg() {");
4176 fprintf(fp_cpp," return OptoReg::Name(%s_num); }\n\n",
4177 _frame->_interpreter_method_oop_reg);
4178 fprintf(fp_cpp,"int Matcher::interpreter_method_oop_reg_encode() {");
4179 fprintf(fp_cpp," return _regEncode[interpreter_method_oop_reg()]; }\n\n");
4180
4181 // Interpreter's Frame Pointer Register, mask definition, and encoding
4182 fprintf(fp_cpp,"OptoReg::Name Matcher::interpreter_frame_pointer_reg() {");
4183 if (_frame->_interpreter_frame_pointer_reg == NULL)
|
32 case Component::DEF:
33 case Component::USE_DEF: return true; break;
34 }
35 return false;
36 }
37
38 // Define an array containing the machine register names, strings.
39 static void defineRegNames(FILE *fp, RegisterForm *registers) {
40 if (registers) {
41 fprintf(fp,"\n");
42 fprintf(fp,"// An array of character pointers to machine register names.\n");
43 fprintf(fp,"const char *Matcher::regName[REG_COUNT] = {\n");
44
45 // Output the register name for each register in the allocation classes
46 RegDef *reg_def = NULL;
47 RegDef *next = NULL;
48 registers->reset_RegDefs();
49 for (reg_def = registers->iter_RegDefs(); reg_def != NULL; reg_def = next) {
50 next = registers->iter_RegDefs();
51 const char *comma = (next != NULL) ? "," : " // no trailing comma";
52 fprintf(fp," \"Opcodes::%s\"%s\n", reg_def->_regname, comma);
53 }
54
55 // Finish defining enumeration
56 fprintf(fp,"};\n");
57
58 fprintf(fp,"\n");
59 fprintf(fp,"// An array of character pointers to machine register names.\n");
60 fprintf(fp,"const VMReg OptoReg::opto2vm[REG_COUNT] = {\n");
61 reg_def = NULL;
62 next = NULL;
63 registers->reset_RegDefs();
64 for (reg_def = registers->iter_RegDefs(); reg_def != NULL; reg_def = next) {
65 next = registers->iter_RegDefs();
66 const char *comma = (next != NULL) ? "," : " // no trailing comma";
67 fprintf(fp,"\t%s%s\n", reg_def->_concrete, comma);
68 }
69 // Finish defining array
70 fprintf(fp,"\t};\n");
71 fprintf(fp,"\n");
72
1696 }
1697 } else if (comp->isa(Component::KILL)) {
1698 fprintf(fp, " // DEF/KILL %s\n", comp->_name);
1699
1700 if (!declared_kill) {
1701 // Define the variable "kill" to hold new MachProjNodes
1702 fprintf(fp, " MachProjNode *kill;\n");
1703 declared_kill = true;
1704 }
1705
1706 assert(op, "Support additional KILLS for base operands");
1707 const char *regmask = reg_mask(*op);
1708 const char *ideal_type = op->ideal_type(_globalNames, _register);
1709
1710 if (!op->is_bound_register()) {
1711 syntax_err(node->_linenum, "In %s only bound registers can be killed: %s %s\n",
1712 node->_ident, comp->_type, comp->_name);
1713 }
1714
1715 fprintf(fp," kill = ");
1716 fprintf(fp,"new MachProjNode( %s, %d, (%s), Opcodes::Op_%s );\n",
1717 machNode, proj_no++, regmask, ideal_type);
1718 fprintf(fp," proj_list.push(kill);\n");
1719 }
1720 }
1721 }
1722
1723 if( !node->expands() && node->_matrule != NULL ) {
1724 // Remove duplicated operands and inputs which use the same name.
1725 // Seach through match operands for the same name usage.
1726 uint cur_num_opnds = node->num_opnds();
1727 if( cur_num_opnds > 1 && cur_num_opnds != node->num_unique_opnds() ) {
1728 Component *comp = NULL;
1729 // Build mapping from num_edges to local variables
1730 fprintf(fp," unsigned num0 = 0;\n");
1731 for( i = 1; i < cur_num_opnds; i++ ) {
1732 fprintf(fp," unsigned num%d = opnd_array(%d)->num_edges();",i,i);
1733 fprintf(fp, " \t// %s\n", node->opnd_ident(i));
1734 }
1735 // Build a mapping from operand index to input edges
1736 fprintf(fp," unsigned idx0 = oper_input_base();\n");
3620 // Output #defines from definition block
3621 globalDefs().print_defines(fp_hpp);
3622
3623 if (_pre_header.count() > 0)
3624 _pre_header.output(fp_hpp);
3625 }
3626
3627 //---------------------------buildReduceMaps-----------------------------
3628 // Build mapping from enumeration for densely packed operands
3629 // TO result and child types.
3630 void ArchDesc::buildReduceMaps(FILE *fp_hpp, FILE *fp_cpp) {
3631 RegDef *rdef;
3632 RegDef *next;
3633
3634 // The emit bodies currently require functions defined in the source block.
3635
3636 // Build external declarations for mappings
3637 fprintf(fp_hpp, "\n");
3638 fprintf(fp_hpp, "extern const char register_save_policy[];\n");
3639 fprintf(fp_hpp, "extern const char c_reg_save_policy[];\n");
3640 fprintf(fp_hpp, "extern const Opcodes register_save_type[];\n");
3641 fprintf(fp_hpp, "\n");
3642
3643 // Construct Save-Policy array
3644 fprintf(fp_cpp, "// Map from machine-independent register number to register_save_policy\n");
3645 fprintf(fp_cpp, "const char register_save_policy[] = {\n");
3646 _register->reset_RegDefs();
3647 for( rdef = _register->iter_RegDefs(); rdef != NULL; rdef = next ) {
3648 next = _register->iter_RegDefs();
3649 char policy = reg_save_policy(rdef->_callconv);
3650 const char *comma = (next != NULL) ? "," : " // no trailing comma";
3651 fprintf(fp_cpp, " '%c'%s // %s\n", policy, comma, rdef->_regname);
3652 }
3653 fprintf(fp_cpp, "};\n\n");
3654
3655 // Construct Native Save-Policy array
3656 fprintf(fp_cpp, "// Map from machine-independent register number to c_reg_save_policy\n");
3657 fprintf(fp_cpp, "const char c_reg_save_policy[] = {\n");
3658 _register->reset_RegDefs();
3659 for( rdef = _register->iter_RegDefs(); rdef != NULL; rdef = next ) {
3660 next = _register->iter_RegDefs();
3661 char policy = reg_save_policy(rdef->_c_conv);
3662 const char *comma = (next != NULL) ? "," : " // no trailing comma";
3663 fprintf(fp_cpp, " '%c'%s // %s\n", policy, comma, rdef->_regname);
3664 }
3665 fprintf(fp_cpp, "};\n\n");
3666
3667 // Construct Register Save Type array
3668 fprintf(fp_cpp, "// Map from machine-independent register number to register_save_type\n");
3669 fprintf(fp_cpp, "const Opcodes register_save_type[] = {\n");
3670 _register->reset_RegDefs();
3671 for( rdef = _register->iter_RegDefs(); rdef != NULL; rdef = next ) {
3672 next = _register->iter_RegDefs();
3673 const char *comma = (next != NULL) ? "," : " // no trailing comma";
3674 const char *idealtype = (next != NULL) ? rdef->_idealtype : "Op_Node";
3675 fprintf(fp_cpp, " Opcodes::%s%s\n", idealtype, comma);
3676 }
3677 fprintf(fp_cpp, "};\n\n");
3678
3679 // Construct the table for reduceOp
3680 OutputReduceOp output_reduce_op(fp_hpp, fp_cpp, _globalNames, *this);
3681 build_map(output_reduce_op);
3682 // Construct the table for leftOp
3683 OutputLeftOp output_left_op(fp_hpp, fp_cpp, _globalNames, *this);
3684 build_map(output_left_op);
3685 // Construct the table for rightOp
3686 OutputRightOp output_right_op(fp_hpp, fp_cpp, _globalNames, *this);
3687 build_map(output_right_op);
3688 // Construct the table of rule names
3689 OutputRuleName output_rule_name(fp_hpp, fp_cpp, _globalNames, *this);
3690 build_map(output_rule_name);
3691 // Construct the boolean table for subsumed operands
3692 OutputSwallowed output_swallowed(fp_hpp, fp_cpp, _globalNames, *this);
3693 build_map(output_swallowed);
3694 // // // Preserve in case we decide to use this table instead of another
3695 //// Construct the boolean table for instruction chain rules
4081
4082 // Generate the default case for switch(opcode)
4083 fprintf(fp_cpp, " \n");
4084 fprintf(fp_cpp, " default:\n");
4085 fprintf(fp_cpp, " fprintf(stderr, \"Default MachNode Generator invoked for: \\n\");\n");
4086 fprintf(fp_cpp, " fprintf(stderr, \" opcode = %cd\\n\", opcode);\n", '%');
4087 fprintf(fp_cpp, " break;\n");
4088 fprintf(fp_cpp, " };\n");
4089
4090 // Generate the closing for method Matcher::MachNodeGenerator
4091 fprintf(fp_cpp, " return NULL;\n");
4092 fprintf(fp_cpp, "}\n");
4093 }
4094
4095
4096 //---------------------------buildInstructMatchCheck--------------------------
4097 // Output the method to Matcher which checks whether or not a specific
4098 // instruction has a matching rule for the host architecture.
4099 void ArchDesc::buildInstructMatchCheck(FILE *fp_cpp) const {
4100 fprintf(fp_cpp, "\n\n");
4101 fprintf(fp_cpp, "const bool Matcher::has_match_rule(Opcodes opcode) {\n");
4102 fprintf(fp_cpp, " assert(Opcodes::_last_machine_leaf < opcode && opcode < Opcodes::_last_opcode, \"opcode in range\");\n");
4103 fprintf(fp_cpp, " return _hasMatchRule[static_cast<uint>(opcode)];\n");
4104 fprintf(fp_cpp, "}\n\n");
4105
4106 fprintf(fp_cpp, "const bool Matcher::_hasMatchRule[static_cast<uint>(Opcodes::_last_opcode)] = {\n");
4107 uint i;
4108 for (i = 0; i < static_cast<uint>(Opcodes::_last_opcode) - 1; i++) {
4109 fprintf(fp_cpp, " %-5s, // %s\n",
4110 _has_match_rule[i] ? "true" : "false",
4111 NodeClassNames[i]);
4112 }
4113 fprintf(fp_cpp, " %-5s // %s\n",
4114 _has_match_rule[i] ? "true" : "false",
4115 NodeClassNames[i]);
4116 fprintf(fp_cpp, "};\n");
4117 }
4118
4119 //---------------------------buildFrameMethods---------------------------------
4120 // Output the methods to Matcher which specify frame behavior
4121 void ArchDesc::buildFrameMethods(FILE *fp_cpp) {
4122 fprintf(fp_cpp,"\n\n");
4123 // Stack Direction
4124 fprintf(fp_cpp,"bool Matcher::stack_direction() const { return %s; }\n\n",
4125 _frame->_direction ? "true" : "false");
4126 // Sync Stack Slots
4127 fprintf(fp_cpp,"int Compile::sync_stack_slots() const { return %s; }\n\n",
4128 _frame->_sync_stack_slots);
4140 _frame->_return_addr);
4141 }
4142 // Java Stack Slot Preservation
4143 fprintf(fp_cpp,"uint Compile::in_preserve_stack_slots() ");
4144 fprintf(fp_cpp,"{ return %s; }\n\n", _frame->_in_preserve_slots);
4145 // Top Of Stack Slot Preservation, for both Java and C
4146 fprintf(fp_cpp,"uint Compile::out_preserve_stack_slots() ");
4147 fprintf(fp_cpp,"{ return SharedRuntime::out_preserve_stack_slots(); }\n\n");
4148 // varargs C out slots killed
4149 fprintf(fp_cpp,"uint Compile::varargs_C_out_slots_killed() const ");
4150 fprintf(fp_cpp,"{ return %s; }\n\n", _frame->_varargs_C_out_slots_killed);
4151 // Java Argument Position
4152 fprintf(fp_cpp,"void Matcher::calling_convention(BasicType *sig_bt, VMRegPair *regs, uint length, bool is_outgoing) {\n");
4153 fprintf(fp_cpp,"%s\n", _frame->_calling_convention);
4154 fprintf(fp_cpp,"}\n\n");
4155 // Native Argument Position
4156 fprintf(fp_cpp,"void Matcher::c_calling_convention(BasicType *sig_bt, VMRegPair *regs, uint length) {\n");
4157 fprintf(fp_cpp,"%s\n", _frame->_c_calling_convention);
4158 fprintf(fp_cpp,"}\n\n");
4159 // Java Return Value Location
4160 fprintf(fp_cpp,"OptoRegPair Matcher::return_value(Opcodes ideal_reg, bool is_outgoing) {\n");
4161 fprintf(fp_cpp,"%s\n", _frame->_return_value);
4162 fprintf(fp_cpp,"}\n\n");
4163 // Native Return Value Location
4164 fprintf(fp_cpp,"OptoRegPair Matcher::c_return_value(Opcodes ideal_reg, bool is_outgoing) {\n");
4165 fprintf(fp_cpp,"%s\n", _frame->_c_return_value);
4166 fprintf(fp_cpp,"}\n\n");
4167
4168 // Inline Cache Register, mask definition, and encoding
4169 fprintf(fp_cpp,"OptoReg::Name Matcher::inline_cache_reg() {");
4170 fprintf(fp_cpp," return OptoReg::Name(%s_num); }\n\n",
4171 _frame->_inline_cache_reg);
4172 fprintf(fp_cpp,"int Matcher::inline_cache_reg_encode() {");
4173 fprintf(fp_cpp," return _regEncode[inline_cache_reg()]; }\n\n");
4174
4175 // Interpreter's Method Oop Register, mask definition, and encoding
4176 fprintf(fp_cpp,"OptoReg::Name Matcher::interpreter_method_oop_reg() {");
4177 fprintf(fp_cpp," return OptoReg::Name(%s_num); }\n\n",
4178 _frame->_interpreter_method_oop_reg);
4179 fprintf(fp_cpp,"int Matcher::interpreter_method_oop_reg_encode() {");
4180 fprintf(fp_cpp," return _regEncode[interpreter_method_oop_reg()]; }\n\n");
4181
4182 // Interpreter's Frame Pointer Register, mask definition, and encoding
4183 fprintf(fp_cpp,"OptoReg::Name Matcher::interpreter_frame_pointer_reg() {");
4184 if (_frame->_interpreter_frame_pointer_reg == NULL)
|