776 #ifndef PRODUCT
777 if (trace_spilling() && lrg._def != NULL) {
778 // collect defs for MultiDef printing
779 if (lrg._defs == NULL) {
780 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
781 lrg._defs->append(lrg._def);
782 }
783 lrg._defs->append(n);
784 }
785 #endif
786
787 // Check for a single def LRG; these can spill nicely
788 // via rematerialization. Flag as NULL for no def found
789 // yet, or 'n' for single def or -1 for many defs.
790 lrg._def = lrg._def ? NodeSentinel : n;
791
792 // Limit result register mask to acceptable registers
793 const RegMask &rm = n->out_RegMask();
794 lrg.AND( rm );
795
796 int ireg = n->ideal_reg();
797 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
798 "oops must be in Op_RegP's" );
799
800 // Check for vector live range (only if vector register is used).
801 // On SPARC vector uses RegD which could be misaligned so it is not
802 // processes as vector in RA.
803 if (RegMask::is_vector(ireg))
804 lrg._is_vector = 1;
805 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL,
806 "vector must be in vector registers");
807
808 // Check for bound register masks
809 const RegMask &lrgmask = lrg.mask();
810 if (lrgmask.is_bound(ireg)) {
811 lrg._is_bound = 1;
812 }
813
814 // Check for maximum frequency value
815 if (lrg._maxfreq < block->_freq) {
816 lrg._maxfreq = block->_freq;
817 }
818
819 // Check for oop-iness, or long/double
820 // Check for multi-kill projection
821 switch (ireg) {
822 case MachProjNode::fat_proj:
823 // Fat projections have size equal to number of registers killed
824 lrg.set_num_regs(rm.Size());
825 lrg.set_reg_pressure(lrg.num_regs());
826 lrg._fat_proj = 1;
827 lrg._is_bound = 1;
828 break;
829 case Op_RegP:
830 #ifdef _LP64
831 lrg.set_num_regs(2); // Size is 2 stack words
832 #else
833 lrg.set_num_regs(1); // Size is 1 stack word
834 #endif
835 // Register pressure is tracked relative to the maximum values
836 // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
837 // and relative to other types which compete for the same regs.
838 //
839 // The following table contains suggested values based on the
840 // architectures as defined in each .ad file.
841 // INTPRESSURE and FLOATPRESSURE may be tuned differently for
842 // compile-speed or performance.
843 // Note1:
844 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
845 // since .ad registers are defined as high and low halves.
846 // These reg_pressure values remain compatible with the code
847 // in is_high_pressure() which relates get_invalid_mask_size(),
848 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
849 // Note2:
857 // many long values which are being run on 32-bit SPARC.
858 //
859 // ------------------- reg_pressure --------------------
860 // Each entry is reg_pressure_per_value,number_of_regs
861 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
862 // IA32 2 1 1 1 1 6 6
863 // IA64 1 1 1 1 1 50 41
864 // SPARC 2 2 2 2 2 48 (24) 52 (26)
865 // SPARCV9 2 2 2 2 2 48 (24) 52 (26)
866 // AMD64 1 1 1 1 1 14 15
867 // -----------------------------------------------------
868 #if defined(SPARC)
869 lrg.set_reg_pressure(2); // use for v9 as well
870 #else
871 lrg.set_reg_pressure(1); // normally one value per register
872 #endif
873 if( n_type->isa_oop_ptr() ) {
874 lrg._is_oop = 1;
875 }
876 break;
877 case Op_RegL: // Check for long or double
878 case Op_RegD:
879 lrg.set_num_regs(2);
880 // Define platform specific register pressure
881 #if defined(SPARC) || defined(ARM32)
882 lrg.set_reg_pressure(2);
883 #elif defined(IA32)
884 if( ireg == Op_RegL ) {
885 lrg.set_reg_pressure(2);
886 } else {
887 lrg.set_reg_pressure(1);
888 }
889 #else
890 lrg.set_reg_pressure(1); // normally one value per register
891 #endif
892 // If this def of a double forces a mis-aligned double,
893 // flag as '_fat_proj' - really flag as allowing misalignment
894 // AND changes how we count interferences. A mis-aligned
895 // double can interfere with TWO aligned pairs, or effectively
896 // FOUR registers!
897 if (rm.is_misaligned_pair()) {
898 lrg._fat_proj = 1;
899 lrg._is_bound = 1;
900 }
901 break;
902 case Op_RegF:
903 case Op_RegI:
904 case Op_RegN:
905 case Op_RegFlags:
906 case 0: // not an ideal register
907 lrg.set_num_regs(1);
908 #ifdef SPARC
909 lrg.set_reg_pressure(2);
910 #else
911 lrg.set_reg_pressure(1);
912 #endif
913 break;
914 case Op_VecS:
915 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
916 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
917 lrg.set_num_regs(RegMask::SlotsPerVecS);
918 lrg.set_reg_pressure(1);
919 break;
920 case Op_VecD:
921 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
922 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
923 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
924 lrg.set_num_regs(RegMask::SlotsPerVecD);
925 lrg.set_reg_pressure(1);
926 break;
927 case Op_VecX:
928 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
929 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
930 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
931 lrg.set_num_regs(RegMask::SlotsPerVecX);
932 lrg.set_reg_pressure(1);
933 break;
934 case Op_VecY:
935 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
936 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
937 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
938 lrg.set_num_regs(RegMask::SlotsPerVecY);
939 lrg.set_reg_pressure(1);
940 break;
941 case Op_VecZ:
942 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecZ), "sanity");
943 assert(RegMask::num_registers(Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
944 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned");
945 lrg.set_num_regs(RegMask::SlotsPerVecZ);
946 lrg.set_reg_pressure(1);
947 break;
948 default:
949 ShouldNotReachHere();
950 }
951 }
952
953 // Now do the same for inputs
954 uint cnt = n->req();
955 // Setup for CISC SPILLING
956 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
957 if( UseCISCSpill && after_aggressive ) {
958 inp = n->cisc_operand();
959 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
960 // Convert operand number to edge index number
961 inp = n->as_Mach()->operand_index(inp);
962 }
963
996 // int zzz = 1;
997 // }
998 // }
999
1000 // Limit result register mask to acceptable registers.
1001 // Do not limit registers from uncommon uses before
1002 // AggressiveCoalesce. This effectively pre-virtual-splits
1003 // around uncommon uses of common defs.
1004 const RegMask &rm = n->in_RegMask(k);
1005 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
1006 // Since we are BEFORE aggressive coalesce, leave the register
1007 // mask untrimmed by the call. This encourages more coalescing.
1008 // Later, AFTER aggressive, this live range will have to spill
1009 // but the spiller handles slow-path calls very nicely.
1010 } else {
1011 lrg.AND( rm );
1012 }
1013
1014 // Check for bound register masks
1015 const RegMask &lrgmask = lrg.mask();
1016 int kreg = n->in(k)->ideal_reg();
1017 bool is_vect = RegMask::is_vector(kreg);
1018 assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
1019 is_vect || kreg == Op_RegD || kreg == Op_RegL,
1020 "vector must be in vector registers");
1021 if (lrgmask.is_bound(kreg))
1022 lrg._is_bound = 1;
1023
1024 // If this use of a double forces a mis-aligned double,
1025 // flag as '_fat_proj' - really flag as allowing misalignment
1026 // AND changes how we count interferences. A mis-aligned
1027 // double can interfere with TWO aligned pairs, or effectively
1028 // FOUR registers!
1029 #ifdef ASSERT
1030 if (is_vect && !_scheduling_info_generated) {
1031 if (lrg.num_regs() != 0) {
1032 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
1033 assert(!lrg._fat_proj, "sanity");
1034 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
1035 } else {
1036 assert(n->is_Phi(), "not all inputs processed only if Phi");
1037 }
1038 }
1039 #endif
1754 // Add the projection nodes to the CFG
1755 for (DUIterator_Fast imax, i = base->fast_outs(imax); i < imax; i++) {
1756 Node* use = base->fast_out(i);
1757 if (use->is_MachProj()) {
1758 startb->insert_node(use, ++node_pos);
1759 _cfg.map_node_to_block(use, startb);
1760 new_lrg(use, maxlrg++);
1761 }
1762 }
1763 }
1764 if (_lrg_map.live_range_id(base) == 0) {
1765 new_lrg(base, maxlrg++);
1766 }
1767 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1768 derived_base_map[derived->_idx] = base;
1769 return base;
1770 }
1771
1772 // Check for AddP-related opcodes
1773 if (!derived->is_Phi()) {
1774 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, "but is: %s", derived->Name());
1775 Node *base = derived->in(AddPNode::Base);
1776 derived_base_map[derived->_idx] = base;
1777 return base;
1778 }
1779
1780 // Recursively find bases for Phis.
1781 // First check to see if we can avoid a base Phi here.
1782 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1783 uint i;
1784 for( i = 2; i < derived->req(); i++ )
1785 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1786 break;
1787 // Went to the end without finding any different bases?
1788 if( i == derived->req() ) { // No need for a base Phi here
1789 derived_base_map[derived->_idx] = base;
1790 return base;
1791 }
1792
1793 // Now we see we need a base-Phi here to merge the bases
1794 const Type *t = base->bottom_type();
1839
1840 // For all blocks in RPO do...
1841 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1842 Block* block = _cfg.get_block(i);
1843 // Note use of deep-copy constructor. I cannot hammer the original
1844 // liveout bits, because they are needed by the following coalesce pass.
1845 IndexSet liveout(_live->live(block));
1846
1847 for (uint j = block->end_idx() + 1; j > 1; j--) {
1848 Node* n = block->get_node(j - 1);
1849
1850 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1851 // like to see in the same register. Compare uses the loop-phi and so
1852 // extends its live range BUT cannot be part of the cycle. If this
1853 // extended live range overlaps with the update of the loop-phi value
1854 // we need both alive at the same time -- which requires at least 1
1855 // copy. But because Intel has only 2-address registers we end up with
1856 // at least 2 copies, one before the loop-phi update instruction and
1857 // one after. Instead we split the input to the compare just after the
1858 // phi.
1859 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1860 Node *phi = n->in(1);
1861 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1862 Block *phi_block = _cfg.get_block_for_node(phi);
1863 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1864 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1865 Node *spill = new MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask);
1866 insert_proj( phi_block, 1, spill, maxlrg++ );
1867 n->set_req(1,spill);
1868 must_recompute_live = true;
1869 }
1870 }
1871 }
1872
1873 // Get value being defined
1874 uint lidx = _lrg_map.live_range_id(n);
1875 // Ignore the occasional brand-new live range
1876 if (lidx && lidx < _lrg_map.max_lrg_id()) {
1877 // Remove from live-out set
1878 liveout.remove(lidx);
1879
1880 // Copies do not define a new value and so do not interfere.
1881 // Remove the copies source from the liveout set before interfering.
1882 uint idx = n->is_Copy();
1883 if (idx) {
1884 liveout.remove(_lrg_map.live_range_id(n->in(idx)));
1942 _lrg_map.set_max_lrg_id(maxlrg);
1943
1944 // If I created a new live range I need to recompute live
1945 if (maxlrg != _ifg->_maxlrg) {
1946 must_recompute_live = true;
1947 }
1948
1949 return must_recompute_live != 0;
1950 }
1951
1952 // Extend the node to LRG mapping
1953
1954 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
1955 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1956 }
1957
1958 #ifndef PRODUCT
1959 void PhaseChaitin::dump(const Node *n) const {
1960 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1961 tty->print("L%d",r);
1962 if (r && n->Opcode() != Op_Phi) {
1963 if( _node_regs ) { // Got a post-allocation copy of allocation?
1964 tty->print("[");
1965 OptoReg::Name second = get_reg_second(n);
1966 if( OptoReg::is_valid(second) ) {
1967 if( OptoReg::is_reg(second) )
1968 tty->print("%s:",Matcher::regName[second]);
1969 else
1970 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1971 }
1972 OptoReg::Name first = get_reg_first(n);
1973 if( OptoReg::is_reg(first) )
1974 tty->print("%s]",Matcher::regName[first]);
1975 else
1976 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1977 } else
1978 n->out_RegMask().dump();
1979 }
1980 tty->print("/N%d\t",n->_idx);
1981 tty->print("%s === ", n->Name());
1982 uint k;
1983 for (k = 0; k < n->req(); k++) {
1984 Node *m = n->in(k);
1985 if (!m) {
1986 tty->print("_ ");
1987 }
1988 else {
1989 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1990 tty->print("L%d",r);
1991 // Data MultiNode's can have projections with no real registers.
1992 // Don't die while dumping them.
1993 int op = n->Opcode();
1994 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
1995 if( _node_regs ) {
1996 tty->print("[");
1997 OptoReg::Name second = get_reg_second(n->in(k));
1998 if( OptoReg::is_valid(second) ) {
1999 if( OptoReg::is_reg(second) )
2000 tty->print("%s:",Matcher::regName[second]);
2001 else
2002 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
2003 reg2offset_unchecked(second));
2004 }
2005 OptoReg::Name first = get_reg_first(n->in(k));
2006 if( OptoReg::is_reg(first) )
2007 tty->print("%s]",Matcher::regName[first]);
2008 else
2009 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
2010 reg2offset_unchecked(first));
2011 } else
2012 n->in_RegMask(k).dump();
2013 }
2014 tty->print("/N%d ",m->_idx);
|
776 #ifndef PRODUCT
777 if (trace_spilling() && lrg._def != NULL) {
778 // collect defs for MultiDef printing
779 if (lrg._defs == NULL) {
780 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
781 lrg._defs->append(lrg._def);
782 }
783 lrg._defs->append(n);
784 }
785 #endif
786
787 // Check for a single def LRG; these can spill nicely
788 // via rematerialization. Flag as NULL for no def found
789 // yet, or 'n' for single def or -1 for many defs.
790 lrg._def = lrg._def ? NodeSentinel : n;
791
792 // Limit result register mask to acceptable registers
793 const RegMask &rm = n->out_RegMask();
794 lrg.AND( rm );
795
796 Opcodes ireg = n->ideal_reg();
797 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Opcodes::Op_RegP,
798 "oops must be in Op_RegP's" );
799
800 // Check for vector live range (only if vector register is used).
801 // On SPARC vector uses RegD which could be misaligned so it is not
802 // processes as vector in RA.
803 if (RegMask::is_vector(ireg))
804 lrg._is_vector = 1;
805 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Opcodes::Op_RegD || ireg == Opcodes::Op_RegL,
806 "vector must be in vector registers");
807
808 // Check for bound register masks
809 const RegMask &lrgmask = lrg.mask();
810 if (lrgmask.is_bound(ireg)) {
811 lrg._is_bound = 1;
812 }
813
814 // Check for maximum frequency value
815 if (lrg._maxfreq < block->_freq) {
816 lrg._maxfreq = block->_freq;
817 }
818
819 // Check for oop-iness, or long/double
820 // Check for multi-kill projection
821 switch (ireg) {
822 case static_cast<Opcodes>(MachProjNode::projType::fat_proj):
823 // Fat projections have size equal to number of registers killed
824 lrg.set_num_regs(rm.Size());
825 lrg.set_reg_pressure(lrg.num_regs());
826 lrg._fat_proj = 1;
827 lrg._is_bound = 1;
828 break;
829 case Opcodes::Op_RegP:
830 #ifdef _LP64
831 lrg.set_num_regs(2); // Size is 2 stack words
832 #else
833 lrg.set_num_regs(1); // Size is 1 stack word
834 #endif
835 // Register pressure is tracked relative to the maximum values
836 // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
837 // and relative to other types which compete for the same regs.
838 //
839 // The following table contains suggested values based on the
840 // architectures as defined in each .ad file.
841 // INTPRESSURE and FLOATPRESSURE may be tuned differently for
842 // compile-speed or performance.
843 // Note1:
844 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
845 // since .ad registers are defined as high and low halves.
846 // These reg_pressure values remain compatible with the code
847 // in is_high_pressure() which relates get_invalid_mask_size(),
848 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
849 // Note2:
857 // many long values which are being run on 32-bit SPARC.
858 //
859 // ------------------- reg_pressure --------------------
860 // Each entry is reg_pressure_per_value,number_of_regs
861 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
862 // IA32 2 1 1 1 1 6 6
863 // IA64 1 1 1 1 1 50 41
864 // SPARC 2 2 2 2 2 48 (24) 52 (26)
865 // SPARCV9 2 2 2 2 2 48 (24) 52 (26)
866 // AMD64 1 1 1 1 1 14 15
867 // -----------------------------------------------------
868 #if defined(SPARC)
869 lrg.set_reg_pressure(2); // use for v9 as well
870 #else
871 lrg.set_reg_pressure(1); // normally one value per register
872 #endif
873 if( n_type->isa_oop_ptr() ) {
874 lrg._is_oop = 1;
875 }
876 break;
877 case Opcodes::Op_RegL: // Check for long or double
878 case Opcodes::Op_RegD:
879 lrg.set_num_regs(2);
880 // Define platform specific register pressure
881 #if defined(SPARC) || defined(ARM32)
882 lrg.set_reg_pressure(2);
883 #elif defined(IA32)
884 if( ireg == Opcodes::Op_RegL ) {
885 lrg.set_reg_pressure(2);
886 } else {
887 lrg.set_reg_pressure(1);
888 }
889 #else
890 lrg.set_reg_pressure(1); // normally one value per register
891 #endif
892 // If this def of a double forces a mis-aligned double,
893 // flag as '_fat_proj' - really flag as allowing misalignment
894 // AND changes how we count interferences. A mis-aligned
895 // double can interfere with TWO aligned pairs, or effectively
896 // FOUR registers!
897 if (rm.is_misaligned_pair()) {
898 lrg._fat_proj = 1;
899 lrg._is_bound = 1;
900 }
901 break;
902 case Opcodes::Op_RegF:
903 case Opcodes::Op_RegI:
904 case Opcodes::Op_RegN:
905 case Opcodes::Op_RegFlags:
906 case Opcodes::Op_Node: // not an ideal register
907 lrg.set_num_regs(1);
908 #ifdef SPARC
909 lrg.set_reg_pressure(2);
910 #else
911 lrg.set_reg_pressure(1);
912 #endif
913 break;
914 case Opcodes::Op_VecS:
915 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
916 assert(RegMask::num_registers(Opcodes::Op_VecS) == RegMask::SlotsPerVecS, "sanity");
917 lrg.set_num_regs(RegMask::SlotsPerVecS);
918 lrg.set_reg_pressure(1);
919 break;
920 case Opcodes::Op_VecD:
921 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
922 assert(RegMask::num_registers(Opcodes::Op_VecD) == RegMask::SlotsPerVecD, "sanity");
923 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
924 lrg.set_num_regs(RegMask::SlotsPerVecD);
925 lrg.set_reg_pressure(1);
926 break;
927 case Opcodes::Op_VecX:
928 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
929 assert(RegMask::num_registers(Opcodes::Op_VecX) == RegMask::SlotsPerVecX, "sanity");
930 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
931 lrg.set_num_regs(RegMask::SlotsPerVecX);
932 lrg.set_reg_pressure(1);
933 break;
934 case Opcodes::Op_VecY:
935 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
936 assert(RegMask::num_registers(Opcodes::Op_VecY) == RegMask::SlotsPerVecY, "sanity");
937 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
938 lrg.set_num_regs(RegMask::SlotsPerVecY);
939 lrg.set_reg_pressure(1);
940 break;
941 case Opcodes::Op_VecZ:
942 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecZ), "sanity");
943 assert(RegMask::num_registers(Opcodes::Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
944 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned");
945 lrg.set_num_regs(RegMask::SlotsPerVecZ);
946 lrg.set_reg_pressure(1);
947 break;
948 default:
949 ShouldNotReachHere();
950 }
951 }
952
953 // Now do the same for inputs
954 uint cnt = n->req();
955 // Setup for CISC SPILLING
956 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
957 if( UseCISCSpill && after_aggressive ) {
958 inp = n->cisc_operand();
959 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
960 // Convert operand number to edge index number
961 inp = n->as_Mach()->operand_index(inp);
962 }
963
996 // int zzz = 1;
997 // }
998 // }
999
1000 // Limit result register mask to acceptable registers.
1001 // Do not limit registers from uncommon uses before
1002 // AggressiveCoalesce. This effectively pre-virtual-splits
1003 // around uncommon uses of common defs.
1004 const RegMask &rm = n->in_RegMask(k);
1005 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
1006 // Since we are BEFORE aggressive coalesce, leave the register
1007 // mask untrimmed by the call. This encourages more coalescing.
1008 // Later, AFTER aggressive, this live range will have to spill
1009 // but the spiller handles slow-path calls very nicely.
1010 } else {
1011 lrg.AND( rm );
1012 }
1013
1014 // Check for bound register masks
1015 const RegMask &lrgmask = lrg.mask();
1016 Opcodes kreg = n->in(k)->ideal_reg();
1017 bool is_vect = RegMask::is_vector(kreg);
1018 assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
1019 is_vect || kreg == Opcodes::Op_RegD || kreg == Opcodes::Op_RegL,
1020 "vector must be in vector registers");
1021 if (lrgmask.is_bound(kreg))
1022 lrg._is_bound = 1;
1023
1024 // If this use of a double forces a mis-aligned double,
1025 // flag as '_fat_proj' - really flag as allowing misalignment
1026 // AND changes how we count interferences. A mis-aligned
1027 // double can interfere with TWO aligned pairs, or effectively
1028 // FOUR registers!
1029 #ifdef ASSERT
1030 if (is_vect && !_scheduling_info_generated) {
1031 if (lrg.num_regs() != 0) {
1032 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
1033 assert(!lrg._fat_proj, "sanity");
1034 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
1035 } else {
1036 assert(n->is_Phi(), "not all inputs processed only if Phi");
1037 }
1038 }
1039 #endif
1754 // Add the projection nodes to the CFG
1755 for (DUIterator_Fast imax, i = base->fast_outs(imax); i < imax; i++) {
1756 Node* use = base->fast_out(i);
1757 if (use->is_MachProj()) {
1758 startb->insert_node(use, ++node_pos);
1759 _cfg.map_node_to_block(use, startb);
1760 new_lrg(use, maxlrg++);
1761 }
1762 }
1763 }
1764 if (_lrg_map.live_range_id(base) == 0) {
1765 new_lrg(base, maxlrg++);
1766 }
1767 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1768 derived_base_map[derived->_idx] = base;
1769 return base;
1770 }
1771
1772 // Check for AddP-related opcodes
1773 if (!derived->is_Phi()) {
1774 assert(derived->as_Mach()->ideal_Opcode() == Opcodes::Op_AddP, "but is: %s", derived->Name());
1775 Node *base = derived->in(AddPNode::Base);
1776 derived_base_map[derived->_idx] = base;
1777 return base;
1778 }
1779
1780 // Recursively find bases for Phis.
1781 // First check to see if we can avoid a base Phi here.
1782 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1783 uint i;
1784 for( i = 2; i < derived->req(); i++ )
1785 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1786 break;
1787 // Went to the end without finding any different bases?
1788 if( i == derived->req() ) { // No need for a base Phi here
1789 derived_base_map[derived->_idx] = base;
1790 return base;
1791 }
1792
1793 // Now we see we need a base-Phi here to merge the bases
1794 const Type *t = base->bottom_type();
1839
1840 // For all blocks in RPO do...
1841 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1842 Block* block = _cfg.get_block(i);
1843 // Note use of deep-copy constructor. I cannot hammer the original
1844 // liveout bits, because they are needed by the following coalesce pass.
1845 IndexSet liveout(_live->live(block));
1846
1847 for (uint j = block->end_idx() + 1; j > 1; j--) {
1848 Node* n = block->get_node(j - 1);
1849
1850 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1851 // like to see in the same register. Compare uses the loop-phi and so
1852 // extends its live range BUT cannot be part of the cycle. If this
1853 // extended live range overlaps with the update of the loop-phi value
1854 // we need both alive at the same time -- which requires at least 1
1855 // copy. But because Intel has only 2-address registers we end up with
1856 // at least 2 copies, one before the loop-phi update instruction and
1857 // one after. Instead we split the input to the compare just after the
1858 // phi.
1859 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Opcodes::Op_CmpI ) {
1860 Node *phi = n->in(1);
1861 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1862 Block *phi_block = _cfg.get_block_for_node(phi);
1863 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1864 const RegMask *mask = C->matcher()->idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegI)];
1865 Node *spill = new MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask);
1866 insert_proj( phi_block, 1, spill, maxlrg++ );
1867 n->set_req(1,spill);
1868 must_recompute_live = true;
1869 }
1870 }
1871 }
1872
1873 // Get value being defined
1874 uint lidx = _lrg_map.live_range_id(n);
1875 // Ignore the occasional brand-new live range
1876 if (lidx && lidx < _lrg_map.max_lrg_id()) {
1877 // Remove from live-out set
1878 liveout.remove(lidx);
1879
1880 // Copies do not define a new value and so do not interfere.
1881 // Remove the copies source from the liveout set before interfering.
1882 uint idx = n->is_Copy();
1883 if (idx) {
1884 liveout.remove(_lrg_map.live_range_id(n->in(idx)));
1942 _lrg_map.set_max_lrg_id(maxlrg);
1943
1944 // If I created a new live range I need to recompute live
1945 if (maxlrg != _ifg->_maxlrg) {
1946 must_recompute_live = true;
1947 }
1948
1949 return must_recompute_live != 0;
1950 }
1951
1952 // Extend the node to LRG mapping
1953
1954 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
1955 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1956 }
1957
1958 #ifndef PRODUCT
1959 void PhaseChaitin::dump(const Node *n) const {
1960 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1961 tty->print("L%d",r);
1962 if (r && n->Opcode() != Opcodes::Op_Phi) {
1963 if( _node_regs ) { // Got a post-allocation copy of allocation?
1964 tty->print("[");
1965 OptoReg::Name second = get_reg_second(n);
1966 if( OptoReg::is_valid(second) ) {
1967 if( OptoReg::is_reg(second) )
1968 tty->print("%s:",Matcher::regName[second]);
1969 else
1970 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1971 }
1972 OptoReg::Name first = get_reg_first(n);
1973 if( OptoReg::is_reg(first) )
1974 tty->print("%s]",Matcher::regName[first]);
1975 else
1976 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1977 } else
1978 n->out_RegMask().dump();
1979 }
1980 tty->print("/N%d\t",n->_idx);
1981 tty->print("%s === ", n->Name());
1982 uint k;
1983 for (k = 0; k < n->req(); k++) {
1984 Node *m = n->in(k);
1985 if (!m) {
1986 tty->print("_ ");
1987 }
1988 else {
1989 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1990 tty->print("L%d",r);
1991 // Data MultiNode's can have projections with no real registers.
1992 // Don't die while dumping them.
1993 Opcodes op = n->Opcode();
1994 if( r && op != Opcodes::Op_Phi && op != Opcodes::Op_Proj && op != Opcodes::Op_SCMemProj) {
1995 if( _node_regs ) {
1996 tty->print("[");
1997 OptoReg::Name second = get_reg_second(n->in(k));
1998 if( OptoReg::is_valid(second) ) {
1999 if( OptoReg::is_reg(second) )
2000 tty->print("%s:",Matcher::regName[second]);
2001 else
2002 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
2003 reg2offset_unchecked(second));
2004 }
2005 OptoReg::Name first = get_reg_first(n->in(k));
2006 if( OptoReg::is_reg(first) )
2007 tty->print("%s]",Matcher::regName[first]);
2008 else
2009 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
2010 reg2offset_unchecked(first));
2011 } else
2012 n->in_RegMask(k).dump();
2013 }
2014 tty->print("/N%d ",m->_idx);
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