< prev index next >

src/share/vm/opto/chaitin.cpp

Print this page

        

@@ -791,20 +791,20 @@
 
         // Limit result register mask to acceptable registers
         const RegMask &rm = n->out_RegMask();
         lrg.AND( rm );
 
-        int ireg = n->ideal_reg();
-        assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
+        Opcodes ireg = n->ideal_reg();
+        assert( !n->bottom_type()->isa_oop_ptr() || ireg == Opcodes::Op_RegP,
                 "oops must be in Op_RegP's" );
 
         // Check for vector live range (only if vector register is used).
         // On SPARC vector uses RegD which could be misaligned so it is not
         // processes as vector in RA.
         if (RegMask::is_vector(ireg))
           lrg._is_vector = 1;
-        assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL,
+        assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Opcodes::Op_RegD || ireg == Opcodes::Op_RegL,
                "vector must be in vector registers");
 
         // Check for bound register masks
         const RegMask &lrgmask = lrg.mask();
         if (lrgmask.is_bound(ireg)) {

@@ -817,18 +817,18 @@
         }
 
         // Check for oop-iness, or long/double
         // Check for multi-kill projection
         switch (ireg) {
-        case MachProjNode::fat_proj:
+        case static_cast<Opcodes>(MachProjNode::projType::fat_proj):
           // Fat projections have size equal to number of registers killed
           lrg.set_num_regs(rm.Size());
           lrg.set_reg_pressure(lrg.num_regs());
           lrg._fat_proj = 1;
           lrg._is_bound = 1;
           break;
-        case Op_RegP:
+        case Opcodes::Op_RegP:
 #ifdef _LP64
           lrg.set_num_regs(2);  // Size is 2 stack words
 #else
           lrg.set_num_regs(1);  // Size is 1 stack word
 #endif

@@ -872,18 +872,18 @@
 #endif
           if( n_type->isa_oop_ptr() ) {
             lrg._is_oop = 1;
           }
           break;
-        case Op_RegL:           // Check for long or double
-        case Op_RegD:
+        case Opcodes::Op_RegL:           // Check for long or double
+        case Opcodes::Op_RegD:
           lrg.set_num_regs(2);
           // Define platform specific register pressure
 #if defined(SPARC) || defined(ARM32)
           lrg.set_reg_pressure(2);
 #elif defined(IA32)
-          if( ireg == Op_RegL ) {
+          if( ireg == Opcodes::Op_RegL ) {
             lrg.set_reg_pressure(2);
           } else {
             lrg.set_reg_pressure(1);
           }
 #else

@@ -897,52 +897,52 @@
           if (rm.is_misaligned_pair()) {
             lrg._fat_proj = 1;
             lrg._is_bound = 1;
           }
           break;
-        case Op_RegF:
-        case Op_RegI:
-        case Op_RegN:
-        case Op_RegFlags:
-        case 0:                 // not an ideal register
+        case Opcodes::Op_RegF:
+        case Opcodes::Op_RegI:
+        case Opcodes::Op_RegN:
+        case Opcodes::Op_RegFlags:
+        case Opcodes::Op_Node: // not an ideal register
           lrg.set_num_regs(1);
 #ifdef SPARC
           lrg.set_reg_pressure(2);
 #else
           lrg.set_reg_pressure(1);
 #endif
           break;
-        case Op_VecS:
+        case Opcodes::Op_VecS:
           assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
-          assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
+          assert(RegMask::num_registers(Opcodes::Op_VecS) == RegMask::SlotsPerVecS, "sanity");
           lrg.set_num_regs(RegMask::SlotsPerVecS);
           lrg.set_reg_pressure(1);
           break;
-        case Op_VecD:
+        case Opcodes::Op_VecD:
           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
-          assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
+          assert(RegMask::num_registers(Opcodes::Op_VecD) == RegMask::SlotsPerVecD, "sanity");
           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
           lrg.set_num_regs(RegMask::SlotsPerVecD);
           lrg.set_reg_pressure(1);
           break;
-        case Op_VecX:
+        case Opcodes::Op_VecX:
           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
-          assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
+          assert(RegMask::num_registers(Opcodes::Op_VecX) == RegMask::SlotsPerVecX, "sanity");
           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
           lrg.set_num_regs(RegMask::SlotsPerVecX);
           lrg.set_reg_pressure(1);
           break;
-        case Op_VecY:
+        case Opcodes::Op_VecY:
           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
-          assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
+          assert(RegMask::num_registers(Opcodes::Op_VecY) == RegMask::SlotsPerVecY, "sanity");
           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
           lrg.set_num_regs(RegMask::SlotsPerVecY);
           lrg.set_reg_pressure(1);
           break;
-        case Op_VecZ:
+        case Opcodes::Op_VecZ:
           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecZ), "sanity");
-          assert(RegMask::num_registers(Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
+          assert(RegMask::num_registers(Opcodes::Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned");
           lrg.set_num_regs(RegMask::SlotsPerVecZ);
           lrg.set_reg_pressure(1);
           break;
         default:

@@ -1011,14 +1011,14 @@
           lrg.AND( rm );
         }
 
         // Check for bound register masks
         const RegMask &lrgmask = lrg.mask();
-        int kreg = n->in(k)->ideal_reg();
+        Opcodes kreg = n->in(k)->ideal_reg();
         bool is_vect = RegMask::is_vector(kreg);
         assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
-               is_vect || kreg == Op_RegD || kreg == Op_RegL,
+               is_vect || kreg == Opcodes::Op_RegD || kreg == Opcodes::Op_RegL,
                "vector must be in vector registers");
         if (lrgmask.is_bound(kreg))
           lrg._is_bound = 1;
 
         // If this use of a double forces a mis-aligned double,

@@ -1769,11 +1769,11 @@
     return base;
   }
 
   // Check for AddP-related opcodes
   if (!derived->is_Phi()) {
-    assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, "but is: %s", derived->Name());
+    assert(derived->as_Mach()->ideal_Opcode() == Opcodes::Op_AddP, "but is: %s", derived->Name());
     Node *base = derived->in(AddPNode::Base);
     derived_base_map[derived->_idx] = base;
     return base;
   }
 

@@ -1854,16 +1854,16 @@
       // we need both alive at the same time -- which requires at least 1
       // copy.  But because Intel has only 2-address registers we end up with
       // at least 2 copies, one before the loop-phi update instruction and
       // one after.  Instead we split the input to the compare just after the
       // phi.
-      if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
+      if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Opcodes::Op_CmpI ) {
         Node *phi = n->in(1);
         if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
           Block *phi_block = _cfg.get_block_for_node(phi);
           if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
-            const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
+            const RegMask *mask = C->matcher()->idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegI)];
             Node *spill = new MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask);
             insert_proj( phi_block, 1, spill, maxlrg++ );
             n->set_req(1,spill);
             must_recompute_live = true;
           }

@@ -1957,11 +1957,11 @@
 
 #ifndef PRODUCT
 void PhaseChaitin::dump(const Node *n) const {
   uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
   tty->print("L%d",r);
-  if (r && n->Opcode() != Op_Phi) {
+  if (r && n->Opcode() != Opcodes::Op_Phi) {
     if( _node_regs ) {          // Got a post-allocation copy of allocation?
       tty->print("[");
       OptoReg::Name second = get_reg_second(n);
       if( OptoReg::is_valid(second) ) {
         if( OptoReg::is_reg(second) )

@@ -1988,12 +1988,12 @@
     else {
       uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
       tty->print("L%d",r);
       // Data MultiNode's can have projections with no real registers.
       // Don't die while dumping them.
-      int op = n->Opcode();
-      if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
+      Opcodes op = n->Opcode();
+      if( r && op != Opcodes::Op_Phi && op != Opcodes::Op_Proj && op != Opcodes::Op_SCMemProj) {
         if( _node_regs ) {
           tty->print("[");
           OptoReg::Name second = get_reg_second(n->in(k));
           if( OptoReg::is_valid(second) ) {
             if( OptoReg::is_reg(second) )
< prev index next >