--- old/src/share/vm/opto/divnode.cpp	2016-07-11 22:46:22.525461373 +0900
+++ new/src/share/vm/opto/divnode.cpp	2016-07-11 22:46:22.387461856 +0900
@@ -118,7 +118,7 @@
     if (dti && dti->_lo >= 0) {
       // we don't need to round a positive dividend
       needs_rounding = false;
-    } else if( dividend->Opcode() == Op_AndI ) {
+    } else if( dividend->Opcode() == Opcodes::Op_AndI ) {
       // An AND mask of sufficient size clears the low bits and
       // I can avoid rounding.
       const TypeInt *andconi_t = phase->type( dividend->in(2) )->isa_int();
@@ -259,7 +259,7 @@
 static Node* long_by_long_mulhi(PhaseGVN* phase, Node* dividend, jlong magic_const) {
   // If the architecture supports a 64x64 mulhi, there is
   // no need to synthesize it in ideal nodes.
-  if (Matcher::has_match_rule(Op_MulHiL)) {
+  if (Matcher::has_match_rule(Opcodes::Op_MulHiL)) {
     Node* v = phase->longcon(magic_const);
     return new MulHiLNode(dividend, v);
   }
@@ -371,7 +371,7 @@
     if (dtl && dtl->_lo > 0) {
       // we don't need to round a positive dividend
       needs_rounding = false;
-    } else if( dividend->Opcode() == Op_AndL ) {
+    } else if( dividend->Opcode() == Opcodes::Op_AndL ) {
       // An AND mask of sufficient size clears the low bits and
       // I can avoid rounding.
       const TypeLong *andconl_t = phase->type( dividend->in(2) )->isa_long();
@@ -1282,7 +1282,7 @@
 //------------------------------make------------------------------------------
 DivModINode* DivModINode::make(Node* div_or_mod) {
   Node* n = div_or_mod;
-  assert(n->Opcode() == Op_DivI || n->Opcode() == Op_ModI,
+  assert(n->Opcode() == Opcodes::Op_DivI || n->Opcode() == Opcodes::Op_ModI,
          "only div or mod input pattern accepted");
 
   DivModINode* divmod = new DivModINode(n->in(0), n->in(1), n->in(2));
@@ -1294,7 +1294,7 @@
 //------------------------------make------------------------------------------
 DivModLNode* DivModLNode::make(Node* div_or_mod) {
   Node* n = div_or_mod;
-  assert(n->Opcode() == Op_DivL || n->Opcode() == Op_ModL,
+  assert(n->Opcode() == Opcodes::Op_DivL || n->Opcode() == Opcodes::Op_ModL,
          "only div or mod input pattern accepted");
 
   DivModLNode* divmod = new DivModLNode(n->in(0), n->in(1), n->in(2));
@@ -1306,7 +1306,7 @@
 //------------------------------match------------------------------------------
 // return result(s) along with their RegMask info
 Node *DivModINode::match( const ProjNode *proj, const Matcher *match ) {
-  uint ideal_reg = proj->ideal_reg();
+  Opcodes ideal_reg = proj->ideal_reg();
   RegMask rm;
   if (proj->_con == div_proj_num) {
     rm = match->divI_proj_mask();
@@ -1321,7 +1321,7 @@
 //------------------------------match------------------------------------------
 // return result(s) along with their RegMask info
 Node *DivModLNode::match( const ProjNode *proj, const Matcher *match ) {
-  uint ideal_reg = proj->ideal_reg();
+  Opcodes ideal_reg = proj->ideal_reg();
   RegMask rm;
   if (proj->_con == div_proj_num) {
     rm = match->divL_proj_mask();