173 // Check whether o is a valid oper.
174 static bool notAnOper(const MachOper *o) {
175 if (o == NULL) return true;
176 if (((intptr_t)o & 1) != 0) return true;
177 if (*(address*)o == badAddress) return true; // kill by Node::destruct
178 return false;
179 }
180 #endif // !PRODUCT
181 };
182
183 //------------------------------MachNode---------------------------------------
184 // Base type for all machine specific nodes. All node classes generated by the
185 // ADLC inherit from this class.
186 class MachNode : public Node {
187 public:
188 MachNode() : Node((uint)0), _num_opnds(0), _opnds(NULL) {
189 init_class_id(Class_Mach);
190 }
191 // Required boilerplate
192 virtual uint size_of() const { return sizeof(MachNode); }
193 virtual int Opcode() const; // Always equal to MachNode
194 virtual uint rule() const = 0; // Machine-specific opcode
195 // Number of inputs which come before the first operand.
196 // Generally at least 1, to skip the Control input
197 virtual uint oper_input_base() const { return 1; }
198 // Position of constant base node in node's inputs. -1 if
199 // no constant base node input.
200 virtual uint mach_constant_base_node_input() const { return (uint)-1; }
201
202 // Copy inputs and operands to new node of instruction.
203 // Called from cisc_version() and short_branch_version().
204 // !!!! The method's body is defined in ad_<arch>.cpp file.
205 void fill_new_machnode(MachNode *n) const;
206
207 // Return an equivalent instruction using memory for cisc_operand position
208 virtual MachNode *cisc_version(int offset);
209 // Modify this instruction's register mask to use stack version for cisc_operand
210 virtual void use_cisc_RegMask();
211
212 // Support for short branches
213 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
272 // instruction to properly align it.
273 virtual int compute_padding(int current_offset) const { return 0; }
274
275 // Return number of relocatable values contained in this instruction
276 virtual int reloc() const { return 0; }
277
278 // Return number of words used for double constants in this instruction
279 virtual int ins_num_consts() const { return 0; }
280
281 // Hash and compare over operands. Used to do GVN on machine Nodes.
282 virtual uint hash() const;
283 virtual uint cmp( const Node &n ) const;
284
285 // Expand method for MachNode, replaces nodes representing pseudo
286 // instructions with a set of nodes which represent real machine
287 // instructions and compute the same value.
288 virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; }
289
290 // Bottom_type call; value comes from operand0
291 virtual const class Type *bottom_type() const { return _opnds[0]->type(); }
292 virtual uint ideal_reg() const { const Type *t = _opnds[0]->type(); return t == TypeInt::CC ? Op_RegFlags : t->ideal_reg(); }
293
294 // If this is a memory op, return the base pointer and fixed offset.
295 // If there are no such, return NULL. If there are multiple addresses
296 // or the address is indeterminate (rare cases) then return (Node*)-1,
297 // which serves as node bottom.
298 // If the offset is not statically determined, set it to Type::OffsetBot.
299 // This method is free to ignore stack slots if that helps.
300 #define TYPE_PTR_SENTINAL ((const TypePtr*)-1)
301 // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible
302 const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const;
303
304 // Helper for get_base_and_disp: find the base and index input nodes.
305 // Returns the MachOper as determined by memory_operand(), for use, if
306 // needed by the caller. If (MachOper *)-1 is returned, base and index
307 // are set to NodeSentinel. If (MachOper *) NULL is returned, base and
308 // index are set to NULL.
309 const MachOper* memory_inputs(Node* &base, Node* &index) const;
310
311 // Helper for memory_inputs: Which operand carries the necessary info?
312 // By default, returns NULL, which means there is no such operand.
313 // If it returns (MachOper*)-1, this means there are multiple memories.
314 virtual const MachOper* memory_operand() const { return NULL; }
315
316 // Call "get_base_and_disp" to decide which category of memory is used here.
317 virtual const class TypePtr *adr_type() const;
318
319 // Apply peephole rule(s) to this instruction
320 virtual MachNode *peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted);
321
322 // Top-level ideal Opcode matched
323 virtual int ideal_Opcode() const { return Op_Node; }
324
325 // Adds the label for the case
326 virtual void add_case_label( int switch_val, Label* blockLabel);
327
328 // Set the absolute address for methods
329 virtual void method_set( intptr_t addr );
330
331 // Should we clone rather than spill this instruction?
332 bool rematerialize() const;
333
334 // Get the pipeline info
335 static const Pipeline *pipeline_class();
336 virtual const Pipeline *pipeline() const;
337
338 // Returns true if this node is a check that can be implemented with a trap.
339 virtual bool is_TrapBasedCheckNode() const { return false; }
340
341 #ifndef PRODUCT
342 virtual const char *Name() const = 0; // Machine-specific name
343 virtual void dump_spec(outputStream *st) const; // Print per-node info
381 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
382 virtual uint size(PhaseRegAlloc *ra_) const;
383
384 #ifndef PRODUCT
385 virtual const char *Name() const { return "Breakpoint"; }
386 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
387 #endif
388 };
389
390 //------------------------------MachConstantBaseNode--------------------------
391 // Machine node that represents the base address of the constant table.
392 class MachConstantBaseNode : public MachIdealNode {
393 public:
394 static const RegMask& _out_RegMask; // We need the out_RegMask statically in MachConstantNode::in_RegMask().
395
396 public:
397 MachConstantBaseNode() : MachIdealNode() {
398 init_class_id(Class_MachConstantBase);
399 }
400 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; }
401 virtual uint ideal_reg() const { return Op_RegP; }
402 virtual uint oper_input_base() const { return 1; }
403
404 virtual bool requires_postalloc_expand() const;
405 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
406
407 virtual void emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const;
408 virtual uint size(PhaseRegAlloc* ra_) const;
409 virtual bool pinned() const { return UseRDPCForConstantTableBase; }
410
411 static const RegMask& static_out_RegMask() { return _out_RegMask; }
412 virtual const RegMask& out_RegMask() const { return static_out_RegMask(); }
413
414 #ifndef PRODUCT
415 virtual const char* Name() const { return "MachConstantBaseNode"; }
416 virtual void format(PhaseRegAlloc*, outputStream* st) const;
417 #endif
418 };
419
420 //------------------------------MachConstantNode-------------------------------
421 // Machine node that holds a constant which is stored in the constant table.
501
502 #ifndef PRODUCT
503 virtual const char *Name() const { return "Epilog"; }
504 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
505 #endif
506 };
507
508 //------------------------------MachNopNode-----------------------------------
509 // Machine function Nop Node
510 class MachNopNode : public MachIdealNode {
511 private:
512 int _count;
513 public:
514 MachNopNode( ) : _count(1) {}
515 MachNopNode( int count ) : _count(count) {}
516 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
517 virtual uint size(PhaseRegAlloc *ra_) const;
518
519 virtual const class Type *bottom_type() const { return Type::CONTROL; }
520
521 virtual int ideal_Opcode() const { return Op_Con; } // bogus; see output.cpp
522 virtual const Pipeline *pipeline() const;
523 #ifndef PRODUCT
524 virtual const char *Name() const { return "Nop"; }
525 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
526 virtual void dump_spec(outputStream *st) const { } // No per-operand info
527 #endif
528 };
529
530 //------------------------------MachSpillCopyNode------------------------------
531 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any
532 // location (stack or register).
533 class MachSpillCopyNode : public MachIdealNode {
534 public:
535 enum SpillType {
536 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails
537 PhiInput, // Inserted when coalescing of a phi node and its input fails
538 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks
539 LoopPhiInput, // Pre-split compares of loop-phis
540 Definition, // An lrg marked as spilled will be spilled to memory right after its definition,
541 // if in high pressure region or the lrg is bound
552 };
553 private:
554 const RegMask *_in; // RegMask for input
555 const RegMask *_out; // RegMask for output
556 const Type *_type;
557 const SpillType _spill_type;
558 public:
559 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) :
560 MachIdealNode(), _spill_type(spill_type), _in(&in), _out(&out), _type(n->bottom_type()) {
561 init_class_id(Class_MachSpillCopy);
562 init_flags(Flag_is_Copy);
563 add_req(NULL);
564 add_req(n);
565 }
566 virtual uint size_of() const { return sizeof(*this); }
567 void set_out_RegMask(const RegMask &out) { _out = &out; }
568 void set_in_RegMask(const RegMask &in) { _in = ∈ }
569 virtual const RegMask &out_RegMask() const { return *_out; }
570 virtual const RegMask &in_RegMask(uint) const { return *_in; }
571 virtual const class Type *bottom_type() const { return _type; }
572 virtual uint ideal_reg() const { return _type->ideal_reg(); }
573 virtual uint oper_input_base() const { return 1; }
574 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
575
576 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
577 virtual uint size(PhaseRegAlloc *ra_) const;
578
579
580 #ifndef PRODUCT
581 static const char *spill_type(SpillType st) {
582 switch (st) {
583 case TwoAddress:
584 return "TwoAddressSpillCopy";
585 case PhiInput:
586 return "PhiInputSpillCopy";
587 case DebugUse:
588 return "DebugUseSpillCopy";
589 case LoopPhiInput:
590 return "LoopPhiInputSpillCopy";
591 case Definition:
592 return "DefinitionSpillCopy";
617 }
618
619 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
620 #endif
621 };
622
623 // MachMergeNode is similar to a PhiNode in a sense it merges multiple values,
624 // however it doesn't have a control input and is more like a MergeMem.
625 // It is inserted after the register allocation is done to ensure that nodes use single
626 // definition of a multidef lrg in a block.
627 class MachMergeNode : public MachIdealNode {
628 public:
629 MachMergeNode(Node *n1) {
630 init_class_id(Class_MachMerge);
631 add_req(NULL);
632 add_req(n1);
633 }
634 virtual const RegMask &out_RegMask() const { return in(1)->out_RegMask(); }
635 virtual const RegMask &in_RegMask(uint idx) const { return in(1)->in_RegMask(idx); }
636 virtual const class Type *bottom_type() const { return in(1)->bottom_type(); }
637 virtual uint ideal_reg() const { return bottom_type()->ideal_reg(); }
638 virtual uint oper_input_base() const { return 1; }
639 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { }
640 virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
641 #ifndef PRODUCT
642 virtual const char *Name() const { return "MachMerge"; }
643 #endif
644 };
645
646 //------------------------------MachBranchNode--------------------------------
647 // Abstract machine branch Node
648 class MachBranchNode : public MachIdealNode {
649 public:
650 MachBranchNode() : MachIdealNode() {
651 init_class_id(Class_MachBranch);
652 }
653 virtual void label_set(Label* label, uint block_num) = 0;
654 virtual void save_label(Label** label, uint* block_num) = 0;
655
656 // Support for short branches
657 virtual MachNode *short_branch_version() { return NULL; }
663 // Machine-dependent null-pointer-check Node. Points a real MachNode that is
664 // also some kind of memory op. Turns the indicated MachNode into a
665 // conditional branch with good latency on the ptr-not-null path and awful
666 // latency on the pointer-is-null path.
667
668 class MachNullCheckNode : public MachBranchNode {
669 public:
670 const uint _vidx; // Index of memop being tested
671 MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachBranchNode(), _vidx(vidx) {
672 init_class_id(Class_MachNullCheck);
673 add_req(ctrl);
674 add_req(memop);
675 }
676 virtual uint size_of() const { return sizeof(*this); }
677
678 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
679 virtual void label_set(Label* label, uint block_num);
680 virtual void save_label(Label** label, uint* block_num);
681 virtual void negate() { }
682 virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; }
683 virtual uint ideal_reg() const { return NotAMachineReg; }
684 virtual const RegMask &in_RegMask(uint) const;
685 virtual const RegMask &out_RegMask() const { return RegMask::Empty; }
686 #ifndef PRODUCT
687 virtual const char *Name() const { return "NullCheck"; }
688 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
689 #endif
690 };
691
692 //------------------------------MachProjNode----------------------------------
693 // Machine-dependent Ideal projections (how is that for an oxymoron). Really
694 // just MachNodes made by the Ideal world that replicate simple projections
695 // but with machine-dependent input & output register masks. Generally
696 // produced as part of calling conventions. Normally I make MachNodes as part
697 // of the Matcher process, but the Matcher is ill suited to issues involving
698 // frame handling, so frame handling is all done in the Ideal world with
699 // occasional callbacks to the machine model for important info.
700 class MachProjNode : public ProjNode {
701 public:
702 MachProjNode( Node *multi, uint con, const RegMask &out, uint ideal_reg ) : ProjNode(multi,con), _rout(out), _ideal_reg(ideal_reg) {
703 init_class_id(Class_MachProj);
704 }
705 RegMask _rout;
706 const uint _ideal_reg;
707 enum projType {
708 unmatched_proj = 0, // Projs for Control, I/O, memory not matched
709 fat_proj = 999 // Projs killing many regs, defined by _rout
710 };
711 virtual int Opcode() const;
712 virtual const Type *bottom_type() const;
713 virtual const TypePtr *adr_type() const;
714 virtual const RegMask &in_RegMask(uint) const { return RegMask::Empty; }
715 virtual const RegMask &out_RegMask() const { return _rout; }
716 virtual uint ideal_reg() const { return _ideal_reg; }
717 // Need size_of() for virtual ProjNode::clone()
718 virtual uint size_of() const { return sizeof(MachProjNode); }
719 #ifndef PRODUCT
720 virtual void dump_spec(outputStream *st) const;
721 #endif
722 };
723
724 //------------------------------MachIfNode-------------------------------------
725 // Machine-specific versions of IfNodes
726 class MachIfNode : public MachBranchNode {
727 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
728 public:
729 float _prob; // Probability branch goes either way
730 float _fcnt; // Frequency counter
731 MachIfNode() : MachBranchNode() {
732 init_class_id(Class_MachIf);
733 }
734 // Negate conditional branches.
735 virtual void negate() = 0;
736 #ifndef PRODUCT
|
173 // Check whether o is a valid oper.
174 static bool notAnOper(const MachOper *o) {
175 if (o == NULL) return true;
176 if (((intptr_t)o & 1) != 0) return true;
177 if (*(address*)o == badAddress) return true; // kill by Node::destruct
178 return false;
179 }
180 #endif // !PRODUCT
181 };
182
183 //------------------------------MachNode---------------------------------------
184 // Base type for all machine specific nodes. All node classes generated by the
185 // ADLC inherit from this class.
186 class MachNode : public Node {
187 public:
188 MachNode() : Node((uint)0), _num_opnds(0), _opnds(NULL) {
189 init_class_id(Class_Mach);
190 }
191 // Required boilerplate
192 virtual uint size_of() const { return sizeof(MachNode); }
193 virtual Opcodes Opcode() const; // Always equal to MachNode
194 virtual uint rule() const = 0; // Machine-specific opcode
195 // Number of inputs which come before the first operand.
196 // Generally at least 1, to skip the Control input
197 virtual uint oper_input_base() const { return 1; }
198 // Position of constant base node in node's inputs. -1 if
199 // no constant base node input.
200 virtual uint mach_constant_base_node_input() const { return (uint)-1; }
201
202 // Copy inputs and operands to new node of instruction.
203 // Called from cisc_version() and short_branch_version().
204 // !!!! The method's body is defined in ad_<arch>.cpp file.
205 void fill_new_machnode(MachNode *n) const;
206
207 // Return an equivalent instruction using memory for cisc_operand position
208 virtual MachNode *cisc_version(int offset);
209 // Modify this instruction's register mask to use stack version for cisc_operand
210 virtual void use_cisc_RegMask();
211
212 // Support for short branches
213 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
272 // instruction to properly align it.
273 virtual int compute_padding(int current_offset) const { return 0; }
274
275 // Return number of relocatable values contained in this instruction
276 virtual int reloc() const { return 0; }
277
278 // Return number of words used for double constants in this instruction
279 virtual int ins_num_consts() const { return 0; }
280
281 // Hash and compare over operands. Used to do GVN on machine Nodes.
282 virtual uint hash() const;
283 virtual uint cmp( const Node &n ) const;
284
285 // Expand method for MachNode, replaces nodes representing pseudo
286 // instructions with a set of nodes which represent real machine
287 // instructions and compute the same value.
288 virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; }
289
290 // Bottom_type call; value comes from operand0
291 virtual const class Type *bottom_type() const { return _opnds[0]->type(); }
292 virtual Opcodes ideal_reg() const { const Type *t = _opnds[0]->type(); return t == TypeInt::CC ? Opcodes::Op_RegFlags : t->ideal_reg(); }
293
294 // If this is a memory op, return the base pointer and fixed offset.
295 // If there are no such, return NULL. If there are multiple addresses
296 // or the address is indeterminate (rare cases) then return (Node*)-1,
297 // which serves as node bottom.
298 // If the offset is not statically determined, set it to Type::OffsetBot.
299 // This method is free to ignore stack slots if that helps.
300 #define TYPE_PTR_SENTINAL ((const TypePtr*)-1)
301 // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible
302 const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const;
303
304 // Helper for get_base_and_disp: find the base and index input nodes.
305 // Returns the MachOper as determined by memory_operand(), for use, if
306 // needed by the caller. If (MachOper *)-1 is returned, base and index
307 // are set to NodeSentinel. If (MachOper *) NULL is returned, base and
308 // index are set to NULL.
309 const MachOper* memory_inputs(Node* &base, Node* &index) const;
310
311 // Helper for memory_inputs: Which operand carries the necessary info?
312 // By default, returns NULL, which means there is no such operand.
313 // If it returns (MachOper*)-1, this means there are multiple memories.
314 virtual const MachOper* memory_operand() const { return NULL; }
315
316 // Call "get_base_and_disp" to decide which category of memory is used here.
317 virtual const class TypePtr *adr_type() const;
318
319 // Apply peephole rule(s) to this instruction
320 virtual MachNode *peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted);
321
322 // Top-level ideal Opcode matched
323 virtual Opcodes ideal_Opcode() const { return Opcodes::Op_Node; }
324
325 // Adds the label for the case
326 virtual void add_case_label( int switch_val, Label* blockLabel);
327
328 // Set the absolute address for methods
329 virtual void method_set( intptr_t addr );
330
331 // Should we clone rather than spill this instruction?
332 bool rematerialize() const;
333
334 // Get the pipeline info
335 static const Pipeline *pipeline_class();
336 virtual const Pipeline *pipeline() const;
337
338 // Returns true if this node is a check that can be implemented with a trap.
339 virtual bool is_TrapBasedCheckNode() const { return false; }
340
341 #ifndef PRODUCT
342 virtual const char *Name() const = 0; // Machine-specific name
343 virtual void dump_spec(outputStream *st) const; // Print per-node info
381 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
382 virtual uint size(PhaseRegAlloc *ra_) const;
383
384 #ifndef PRODUCT
385 virtual const char *Name() const { return "Breakpoint"; }
386 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
387 #endif
388 };
389
390 //------------------------------MachConstantBaseNode--------------------------
391 // Machine node that represents the base address of the constant table.
392 class MachConstantBaseNode : public MachIdealNode {
393 public:
394 static const RegMask& _out_RegMask; // We need the out_RegMask statically in MachConstantNode::in_RegMask().
395
396 public:
397 MachConstantBaseNode() : MachIdealNode() {
398 init_class_id(Class_MachConstantBase);
399 }
400 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; }
401 virtual Opcodes ideal_reg() const { return Opcodes::Op_RegP; }
402 virtual uint oper_input_base() const { return 1; }
403
404 virtual bool requires_postalloc_expand() const;
405 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
406
407 virtual void emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const;
408 virtual uint size(PhaseRegAlloc* ra_) const;
409 virtual bool pinned() const { return UseRDPCForConstantTableBase; }
410
411 static const RegMask& static_out_RegMask() { return _out_RegMask; }
412 virtual const RegMask& out_RegMask() const { return static_out_RegMask(); }
413
414 #ifndef PRODUCT
415 virtual const char* Name() const { return "MachConstantBaseNode"; }
416 virtual void format(PhaseRegAlloc*, outputStream* st) const;
417 #endif
418 };
419
420 //------------------------------MachConstantNode-------------------------------
421 // Machine node that holds a constant which is stored in the constant table.
501
502 #ifndef PRODUCT
503 virtual const char *Name() const { return "Epilog"; }
504 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
505 #endif
506 };
507
508 //------------------------------MachNopNode-----------------------------------
509 // Machine function Nop Node
510 class MachNopNode : public MachIdealNode {
511 private:
512 int _count;
513 public:
514 MachNopNode( ) : _count(1) {}
515 MachNopNode( int count ) : _count(count) {}
516 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
517 virtual uint size(PhaseRegAlloc *ra_) const;
518
519 virtual const class Type *bottom_type() const { return Type::CONTROL; }
520
521 virtual Opcodes ideal_Opcode() const { return Opcodes::Op_Con; } // bogus; see output.cpp
522 virtual const Pipeline *pipeline() const;
523 #ifndef PRODUCT
524 virtual const char *Name() const { return "Nop"; }
525 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
526 virtual void dump_spec(outputStream *st) const { } // No per-operand info
527 #endif
528 };
529
530 //------------------------------MachSpillCopyNode------------------------------
531 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any
532 // location (stack or register).
533 class MachSpillCopyNode : public MachIdealNode {
534 public:
535 enum SpillType {
536 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails
537 PhiInput, // Inserted when coalescing of a phi node and its input fails
538 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks
539 LoopPhiInput, // Pre-split compares of loop-phis
540 Definition, // An lrg marked as spilled will be spilled to memory right after its definition,
541 // if in high pressure region or the lrg is bound
552 };
553 private:
554 const RegMask *_in; // RegMask for input
555 const RegMask *_out; // RegMask for output
556 const Type *_type;
557 const SpillType _spill_type;
558 public:
559 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) :
560 MachIdealNode(), _spill_type(spill_type), _in(&in), _out(&out), _type(n->bottom_type()) {
561 init_class_id(Class_MachSpillCopy);
562 init_flags(Flag_is_Copy);
563 add_req(NULL);
564 add_req(n);
565 }
566 virtual uint size_of() const { return sizeof(*this); }
567 void set_out_RegMask(const RegMask &out) { _out = &out; }
568 void set_in_RegMask(const RegMask &in) { _in = ∈ }
569 virtual const RegMask &out_RegMask() const { return *_out; }
570 virtual const RegMask &in_RegMask(uint) const { return *_in; }
571 virtual const class Type *bottom_type() const { return _type; }
572 virtual Opcodes ideal_reg() const { return _type->ideal_reg(); }
573 virtual uint oper_input_base() const { return 1; }
574 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
575
576 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
577 virtual uint size(PhaseRegAlloc *ra_) const;
578
579
580 #ifndef PRODUCT
581 static const char *spill_type(SpillType st) {
582 switch (st) {
583 case TwoAddress:
584 return "TwoAddressSpillCopy";
585 case PhiInput:
586 return "PhiInputSpillCopy";
587 case DebugUse:
588 return "DebugUseSpillCopy";
589 case LoopPhiInput:
590 return "LoopPhiInputSpillCopy";
591 case Definition:
592 return "DefinitionSpillCopy";
617 }
618
619 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
620 #endif
621 };
622
623 // MachMergeNode is similar to a PhiNode in a sense it merges multiple values,
624 // however it doesn't have a control input and is more like a MergeMem.
625 // It is inserted after the register allocation is done to ensure that nodes use single
626 // definition of a multidef lrg in a block.
627 class MachMergeNode : public MachIdealNode {
628 public:
629 MachMergeNode(Node *n1) {
630 init_class_id(Class_MachMerge);
631 add_req(NULL);
632 add_req(n1);
633 }
634 virtual const RegMask &out_RegMask() const { return in(1)->out_RegMask(); }
635 virtual const RegMask &in_RegMask(uint idx) const { return in(1)->in_RegMask(idx); }
636 virtual const class Type *bottom_type() const { return in(1)->bottom_type(); }
637 virtual Opcodes ideal_reg() const { return bottom_type()->ideal_reg(); }
638 virtual uint oper_input_base() const { return 1; }
639 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { }
640 virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
641 #ifndef PRODUCT
642 virtual const char *Name() const { return "MachMerge"; }
643 #endif
644 };
645
646 //------------------------------MachBranchNode--------------------------------
647 // Abstract machine branch Node
648 class MachBranchNode : public MachIdealNode {
649 public:
650 MachBranchNode() : MachIdealNode() {
651 init_class_id(Class_MachBranch);
652 }
653 virtual void label_set(Label* label, uint block_num) = 0;
654 virtual void save_label(Label** label, uint* block_num) = 0;
655
656 // Support for short branches
657 virtual MachNode *short_branch_version() { return NULL; }
663 // Machine-dependent null-pointer-check Node. Points a real MachNode that is
664 // also some kind of memory op. Turns the indicated MachNode into a
665 // conditional branch with good latency on the ptr-not-null path and awful
666 // latency on the pointer-is-null path.
667
668 class MachNullCheckNode : public MachBranchNode {
669 public:
670 const uint _vidx; // Index of memop being tested
671 MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachBranchNode(), _vidx(vidx) {
672 init_class_id(Class_MachNullCheck);
673 add_req(ctrl);
674 add_req(memop);
675 }
676 virtual uint size_of() const { return sizeof(*this); }
677
678 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
679 virtual void label_set(Label* label, uint block_num);
680 virtual void save_label(Label** label, uint* block_num);
681 virtual void negate() { }
682 virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; }
683 virtual Opcodes ideal_reg() const { return Opcodes::NotAMachineReg; }
684 virtual const RegMask &in_RegMask(uint) const;
685 virtual const RegMask &out_RegMask() const { return RegMask::Empty; }
686 #ifndef PRODUCT
687 virtual const char *Name() const { return "NullCheck"; }
688 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
689 #endif
690 };
691
692 //------------------------------MachProjNode----------------------------------
693 // Machine-dependent Ideal projections (how is that for an oxymoron). Really
694 // just MachNodes made by the Ideal world that replicate simple projections
695 // but with machine-dependent input & output register masks. Generally
696 // produced as part of calling conventions. Normally I make MachNodes as part
697 // of the Matcher process, but the Matcher is ill suited to issues involving
698 // frame handling, so frame handling is all done in the Ideal world with
699 // occasional callbacks to the machine model for important info.
700 class MachProjNode : public ProjNode {
701 public:
702 MachProjNode( Node *multi, uint con, const RegMask &out, Opcodes ideal_reg ) : ProjNode(multi,con), _rout(out), _ideal_reg(ideal_reg) {
703 init_class_id(Class_MachProj);
704 }
705 RegMask _rout;
706 const Opcodes _ideal_reg;
707 enum class projType : uint {
708 unmatched_proj = 0, // Projs for Control, I/O, memory not matched
709 fat_proj = 999 // Projs killing many regs, defined by _rout
710 };
711 virtual Opcodes Opcode() const;
712 virtual const Type *bottom_type() const;
713 virtual const TypePtr *adr_type() const;
714 virtual const RegMask &in_RegMask(uint) const { return RegMask::Empty; }
715 virtual const RegMask &out_RegMask() const { return _rout; }
716 virtual Opcodes ideal_reg() const { return _ideal_reg; }
717 // Need size_of() for virtual ProjNode::clone()
718 virtual uint size_of() const { return sizeof(MachProjNode); }
719 #ifndef PRODUCT
720 virtual void dump_spec(outputStream *st) const;
721 #endif
722 };
723
724 //------------------------------MachIfNode-------------------------------------
725 // Machine-specific versions of IfNodes
726 class MachIfNode : public MachBranchNode {
727 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
728 public:
729 float _prob; // Probability branch goes either way
730 float _fcnt; // Frequency counter
731 MachIfNode() : MachBranchNode() {
732 init_class_id(Class_MachIf);
733 }
734 // Negate conditional branches.
735 virtual void negate() = 0;
736 #ifndef PRODUCT
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