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src/share/vm/opto/machnode.hpp
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@@ -188,11 +188,11 @@
MachNode() : Node((uint)0), _num_opnds(0), _opnds(NULL) {
init_class_id(Class_Mach);
}
// Required boilerplate
virtual uint size_of() const { return sizeof(MachNode); }
- virtual int Opcode() const; // Always equal to MachNode
+ virtual Opcodes Opcode() const; // Always equal to MachNode
virtual uint rule() const = 0; // Machine-specific opcode
// Number of inputs which come before the first operand.
// Generally at least 1, to skip the Control input
virtual uint oper_input_base() const { return 1; }
// Position of constant base node in node's inputs. -1 if
@@ -287,11 +287,11 @@
// instructions and compute the same value.
virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; }
// Bottom_type call; value comes from operand0
virtual const class Type *bottom_type() const { return _opnds[0]->type(); }
- virtual uint ideal_reg() const { const Type *t = _opnds[0]->type(); return t == TypeInt::CC ? Op_RegFlags : t->ideal_reg(); }
+ virtual Opcodes ideal_reg() const { const Type *t = _opnds[0]->type(); return t == TypeInt::CC ? Opcodes::Op_RegFlags : t->ideal_reg(); }
// If this is a memory op, return the base pointer and fixed offset.
// If there are no such, return NULL. If there are multiple addresses
// or the address is indeterminate (rare cases) then return (Node*)-1,
// which serves as node bottom.
@@ -318,11 +318,11 @@
// Apply peephole rule(s) to this instruction
virtual MachNode *peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted);
// Top-level ideal Opcode matched
- virtual int ideal_Opcode() const { return Op_Node; }
+ virtual Opcodes ideal_Opcode() const { return Opcodes::Op_Node; }
// Adds the label for the case
virtual void add_case_label( int switch_val, Label* blockLabel);
// Set the absolute address for methods
@@ -396,11 +396,11 @@
public:
MachConstantBaseNode() : MachIdealNode() {
init_class_id(Class_MachConstantBase);
}
virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; }
- virtual uint ideal_reg() const { return Op_RegP; }
+ virtual Opcodes ideal_reg() const { return Opcodes::Op_RegP; }
virtual uint oper_input_base() const { return 1; }
virtual bool requires_postalloc_expand() const;
virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
@@ -516,11 +516,11 @@
virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
virtual uint size(PhaseRegAlloc *ra_) const;
virtual const class Type *bottom_type() const { return Type::CONTROL; }
- virtual int ideal_Opcode() const { return Op_Con; } // bogus; see output.cpp
+ virtual Opcodes ideal_Opcode() const { return Opcodes::Op_Con; } // bogus; see output.cpp
virtual const Pipeline *pipeline() const;
#ifndef PRODUCT
virtual const char *Name() const { return "Nop"; }
virtual void format( PhaseRegAlloc *, outputStream *st ) const;
virtual void dump_spec(outputStream *st) const { } // No per-operand info
@@ -567,11 +567,11 @@
void set_out_RegMask(const RegMask &out) { _out = &out; }
void set_in_RegMask(const RegMask &in) { _in = ∈ }
virtual const RegMask &out_RegMask() const { return *_out; }
virtual const RegMask &in_RegMask(uint) const { return *_in; }
virtual const class Type *bottom_type() const { return _type; }
- virtual uint ideal_reg() const { return _type->ideal_reg(); }
+ virtual Opcodes ideal_reg() const { return _type->ideal_reg(); }
virtual uint oper_input_base() const { return 1; }
uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
virtual uint size(PhaseRegAlloc *ra_) const;
@@ -632,11 +632,11 @@
add_req(n1);
}
virtual const RegMask &out_RegMask() const { return in(1)->out_RegMask(); }
virtual const RegMask &in_RegMask(uint idx) const { return in(1)->in_RegMask(idx); }
virtual const class Type *bottom_type() const { return in(1)->bottom_type(); }
- virtual uint ideal_reg() const { return bottom_type()->ideal_reg(); }
+ virtual Opcodes ideal_reg() const { return bottom_type()->ideal_reg(); }
virtual uint oper_input_base() const { return 1; }
virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { }
virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
#ifndef PRODUCT
virtual const char *Name() const { return "MachMerge"; }
@@ -678,11 +678,11 @@
virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
virtual void label_set(Label* label, uint block_num);
virtual void save_label(Label** label, uint* block_num);
virtual void negate() { }
virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; }
- virtual uint ideal_reg() const { return NotAMachineReg; }
+ virtual Opcodes ideal_reg() const { return Opcodes::NotAMachineReg; }
virtual const RegMask &in_RegMask(uint) const;
virtual const RegMask &out_RegMask() const { return RegMask::Empty; }
#ifndef PRODUCT
virtual const char *Name() const { return "NullCheck"; }
virtual void format( PhaseRegAlloc *, outputStream *st ) const;
@@ -697,25 +697,25 @@
// of the Matcher process, but the Matcher is ill suited to issues involving
// frame handling, so frame handling is all done in the Ideal world with
// occasional callbacks to the machine model for important info.
class MachProjNode : public ProjNode {
public:
- MachProjNode( Node *multi, uint con, const RegMask &out, uint ideal_reg ) : ProjNode(multi,con), _rout(out), _ideal_reg(ideal_reg) {
+ MachProjNode( Node *multi, uint con, const RegMask &out, Opcodes ideal_reg ) : ProjNode(multi,con), _rout(out), _ideal_reg(ideal_reg) {
init_class_id(Class_MachProj);
}
RegMask _rout;
- const uint _ideal_reg;
- enum projType {
+ const Opcodes _ideal_reg;
+ enum class projType : uint {
unmatched_proj = 0, // Projs for Control, I/O, memory not matched
fat_proj = 999 // Projs killing many regs, defined by _rout
};
- virtual int Opcode() const;
+ virtual Opcodes Opcode() const;
virtual const Type *bottom_type() const;
virtual const TypePtr *adr_type() const;
virtual const RegMask &in_RegMask(uint) const { return RegMask::Empty; }
virtual const RegMask &out_RegMask() const { return _rout; }
- virtual uint ideal_reg() const { return _ideal_reg; }
+ virtual Opcodes ideal_reg() const { return _ideal_reg; }
// Need size_of() for virtual ProjNode::clone()
virtual uint size_of() const { return sizeof(MachProjNode); }
#ifndef PRODUCT
virtual void dump_spec(outputStream *st) const;
#endif
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