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src/share/vm/opto/matcher.hpp

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*** 167,179 **** public: int LabelRootDepth; // Convert ideal machine register to a register mask for spill-loads static const RegMask *idealreg2regmask[]; ! RegMask *idealreg2spillmask [_last_machine_leaf]; ! RegMask *idealreg2debugmask [_last_machine_leaf]; ! RegMask *idealreg2mhdebugmask[_last_machine_leaf]; void init_spill_mask( Node *ret ); // Convert machine register number to register mask static uint mreg2regmask_max; static RegMask mreg2regmask[]; static RegMask STACK_ONLY_mask; --- 167,179 ---- public: int LabelRootDepth; // Convert ideal machine register to a register mask for spill-loads static const RegMask *idealreg2regmask[]; ! RegMask *idealreg2spillmask [static_cast<uint>(Opcodes::_last_machine_leaf)]; ! RegMask *idealreg2debugmask [static_cast<uint>(Opcodes::_last_machine_leaf)]; ! RegMask *idealreg2mhdebugmask[static_cast<uint>(Opcodes::_last_machine_leaf)]; void init_spill_mask( Node *ret ); // Convert machine register number to register mask static uint mreg2regmask_max; static RegMask mreg2regmask[]; static RegMask STACK_ONLY_mask;
*** 211,221 **** // Always Save = 'A' (same as SOE + SOC) const char *_register_save_policy; const char *_c_reg_save_policy; // Convert a machine register to a machine register type, so-as to // properly match spill code. ! const int *_register_save_type; // Maps from machine register to boolean; true if machine register can // be holding a call argument in some signature. static bool can_be_java_arg( int reg ); // Maps from machine register to boolean; true if machine register holds // a spillable argument. --- 211,221 ---- // Always Save = 'A' (same as SOE + SOC) const char *_register_save_policy; const char *_c_reg_save_policy; // Convert a machine register to a machine register type, so-as to // properly match spill code. ! const Opcodes *_register_save_type; // Maps from machine register to boolean; true if machine register can // be holding a call argument in some signature. static bool can_be_java_arg( int reg ); // Maps from machine register to boolean; true if machine register holds // a spillable argument.
*** 297,318 **** OptoRegPair *_parm_regs; // Array of machine registers per argument RegMask *_calling_convention_mask; // Array of RegMasks per argument // Does matcher have a match rule for this ideal node? ! static const bool has_match_rule(int opcode); ! static const bool _hasMatchRule[_last_opcode]; // Does matcher have a match rule for this ideal node and is the // predicate (if there is one) true? // NOTE: If this function is used more commonly in the future, ADLC // should generate this one. ! static const bool match_rule_supported(int opcode); // identify extra cases that we might want to provide match rules for // e.g. Op_ vector nodes and other intrinsics while guarding with vlen ! static const bool match_rule_supported_vector(int opcode, int vlen); // Some microarchitectures have mask registers used on vectors static const bool has_predicated_vectors(void); // Some uarchs have different sized float register resources --- 297,318 ---- OptoRegPair *_parm_regs; // Array of machine registers per argument RegMask *_calling_convention_mask; // Array of RegMasks per argument // Does matcher have a match rule for this ideal node? ! static const bool has_match_rule(Opcodes opcode); ! static const bool _hasMatchRule[static_cast<uint>(Opcodes::_last_opcode)]; // Does matcher have a match rule for this ideal node and is the // predicate (if there is one) true? // NOTE: If this function is used more commonly in the future, ADLC // should generate this one. ! static const bool match_rule_supported(Opcodes opcode); // identify extra cases that we might want to provide match rules for // e.g. Op_ vector nodes and other intrinsics while guarding with vlen ! static const bool match_rule_supported_vector(Opcodes opcode, int vlen); // Some microarchitectures have mask registers used on vectors static const bool has_predicated_vectors(void); // Some uarchs have different sized float register resources
*** 332,343 **** return (Matcher::max_vector_size(bt) >= size && Matcher::min_vector_size(bt) <= size); } // Vector ideal reg ! static const int vector_ideal_reg(int len); ! static const int vector_shift_count_ideal_reg(int len); // CPU supports misaligned vectors store/load. static const bool misaligned_vectors_ok(); // Should original key array reference be passed to AES stubs --- 332,343 ---- return (Matcher::max_vector_size(bt) >= size && Matcher::min_vector_size(bt) <= size); } // Vector ideal reg ! static const Opcodes vector_ideal_reg(int len); ! static const Opcodes vector_shift_count_ideal_reg(int len); // CPU supports misaligned vectors store/load. static const bool misaligned_vectors_ok(); // Should original key array reference be passed to AES stubs
*** 375,386 **** // Return address register. On Intel it is a stack-slot. On PowerPC // it is the Link register. On Sparc it is r31? virtual OptoReg::Name return_addr() const; RegMask _return_addr_mask; // Return value register. On Intel it is EAX. On Sparc i0/o0. ! static OptoRegPair return_value(int ideal_reg, bool is_outgoing); ! static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); RegMask _return_value_mask; // Inline Cache Register static OptoReg::Name inline_cache_reg(); static int inline_cache_reg_encode(); --- 375,386 ---- // Return address register. On Intel it is a stack-slot. On PowerPC // it is the Link register. On Sparc it is r31? virtual OptoReg::Name return_addr() const; RegMask _return_addr_mask; // Return value register. On Intel it is EAX. On Sparc i0/o0. ! static OptoRegPair return_value(Opcodes ideal_reg, bool is_outgoing); ! static OptoRegPair c_return_value(Opcodes ideal_reg, bool is_outgoing); RegMask _return_value_mask; // Inline Cache Register static OptoReg::Name inline_cache_reg(); static int inline_cache_reg_encode();
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