24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/connode.hpp"
29 #include "opto/convertnode.hpp"
30 #include "opto/memnode.hpp"
31 #include "opto/mulnode.hpp"
32 #include "opto/phaseX.hpp"
33 #include "opto/subnode.hpp"
34
35 // Portions of code courtesy of Clifford Click
36
37
38 //=============================================================================
39 //------------------------------hash-------------------------------------------
40 // Hash function over MulNodes. Needs to be commutative; i.e., I swap
41 // (commute) inputs to MulNodes willy-nilly so the hash function must return
42 // the same value in the presence of edge swapping.
43 uint MulNode::hash() const {
44 return (uintptr_t)in(1) + (uintptr_t)in(2) + Opcode();
45 }
46
47 //------------------------------Identity---------------------------------------
48 // Multiplying a one preserves the other argument
49 Node* MulNode::Identity(PhaseGVN* phase) {
50 register const Type *one = mul_id(); // The multiplicative identity
51 if( phase->type( in(1) )->higher_equal( one ) ) return in(2);
52 if( phase->type( in(2) )->higher_equal( one ) ) return in(1);
53
54 return this;
55 }
56
57 //------------------------------Ideal------------------------------------------
58 // We also canonicalize the Node, moving constants to the right input,
59 // and flatten expressions (so that 1+x+2 becomes x+3).
60 Node *MulNode::Ideal(PhaseGVN *phase, bool can_reshape) {
61 const Type *t1 = phase->type( in(1) );
62 const Type *t2 = phase->type( in(2) );
63 Node *progress = NULL; // Progress flag
64 // We are OK if right is a constant, or right is a load and
65 // left is a non-constant.
66 if( !(t2->singleton() ||
67 (in(2)->is_Load() && !(t1->singleton() || in(1)->is_Load())) ) ) {
68 if( t1->singleton() || // Left input is a constant?
69 // Otherwise, sort inputs (commutativity) to help value numbering.
70 (in(1)->_idx > in(2)->_idx) ) {
71 swap_edges(1, 2);
72 const Type *t = t1;
73 t1 = t2;
74 t2 = t;
75 progress = this; // Made progress
76 }
77 }
78
79 // If the right input is a constant, and the left input is a product of a
80 // constant, flatten the expression tree.
81 uint op = Opcode();
82 if( t2->singleton() && // Right input is a constant?
83 op != Op_MulF && // Float & double cannot reassociate
84 op != Op_MulD ) {
85 if( t2 == Type::TOP ) return NULL;
86 Node *mul1 = in(1);
87 #ifdef ASSERT
88 // Check for dead loop
89 int op1 = mul1->Opcode();
90 if( phase->eqv( mul1, this ) || phase->eqv( in(2), this ) ||
91 ( op1 == mul_opcode() || op1 == add_opcode() ) &&
92 ( phase->eqv( mul1->in(1), this ) || phase->eqv( mul1->in(2), this ) ||
93 phase->eqv( mul1->in(1), mul1 ) || phase->eqv( mul1->in(2), mul1 ) ) )
94 assert(false, "dead loop in MulNode::Ideal");
95 #endif
96
97 if( mul1->Opcode() == mul_opcode() ) { // Left input is a multiply?
98 // Mul of a constant?
99 const Type *t12 = phase->type( mul1->in(2) );
100 if( t12->singleton() && t12 != Type::TOP) { // Left input is an add of a constant?
101 // Compute new constant; check for overflow
102 const Type *tcon01 = ((MulNode*)mul1)->mul_ring(t2,t12);
103 if( tcon01->singleton() ) {
104 // The Mul of the flattened expression
105 set_req(1, mul1->in(1));
106 set_req(2, phase->makecon( tcon01 ));
107 t2 = tcon01;
108 progress = this; // Made progress
109 }
131 add2->set_req(2, phase->makecon(tcon01) );
132 progress = add2;
133 }
134 }
135 } // End of is left input an add
136 } // End of is right input a Mul
137
138 return progress;
139 }
140
141 //------------------------------Value-----------------------------------------
142 const Type* MulNode::Value(PhaseGVN* phase) const {
143 const Type *t1 = phase->type( in(1) );
144 const Type *t2 = phase->type( in(2) );
145 // Either input is TOP ==> the result is TOP
146 if( t1 == Type::TOP ) return Type::TOP;
147 if( t2 == Type::TOP ) return Type::TOP;
148
149 // Either input is ZERO ==> the result is ZERO.
150 // Not valid for floats or doubles since +0.0 * -0.0 --> +0.0
151 int op = Opcode();
152 if( op == Op_MulI || op == Op_AndI || op == Op_MulL || op == Op_AndL ) {
153 const Type *zero = add_id(); // The multiplicative zero
154 if( t1->higher_equal( zero ) ) return zero;
155 if( t2->higher_equal( zero ) ) return zero;
156 }
157
158 // Either input is BOTTOM ==> the result is the local BOTTOM
159 if( t1 == Type::BOTTOM || t2 == Type::BOTTOM )
160 return bottom_type();
161
162 #if defined(IA32)
163 // Can't trust native compilers to properly fold strict double
164 // multiplication with round-to-zero on this platform.
165 if (op == Op_MulD && phase->C->method()->is_strict()) {
166 return TypeD::DOUBLE;
167 }
168 #endif
169
170 return mul_ring(t1,t2); // Local flavor of type multiplication
171 }
172
173
174 //=============================================================================
175 //------------------------------Ideal------------------------------------------
176 // Check for power-of-2 multiply, then try the regular MulNode::Ideal
177 Node *MulINode::Ideal(PhaseGVN *phase, bool can_reshape) {
178 // Swap constant to right
179 jint con;
180 if ((con = in(1)->find_int_con(0)) != 0) {
181 swap_edges(1, 2);
182 // Finish rest of method to use info in 'con'
183 } else if ((con = in(2)->find_int_con(0)) == 0) {
184 return MulNode::Ideal(phase, can_reshape);
185 }
421 return TypeInt::make(0, r0->get_con(), widen);
422
423 if( r1->is_con() && r1->get_con() > 0 )
424 return TypeInt::make(0, r1->get_con(), widen);
425
426 if( r0 == TypeInt::BOOL || r1 == TypeInt::BOOL ) {
427 return TypeInt::BOOL;
428 }
429
430 return TypeInt::INT; // No constants to be had
431 }
432
433 //------------------------------Identity---------------------------------------
434 // Masking off the high bits of an unsigned load is not required
435 Node* AndINode::Identity(PhaseGVN* phase) {
436
437 // x & x => x
438 if (phase->eqv(in(1), in(2))) return in(1);
439
440 Node* in1 = in(1);
441 uint op = in1->Opcode();
442 const TypeInt* t2 = phase->type(in(2))->isa_int();
443 if (t2 && t2->is_con()) {
444 int con = t2->get_con();
445 // Masking off high bits which are always zero is useless.
446 const TypeInt* t1 = phase->type( in(1) )->isa_int();
447 if (t1 != NULL && t1->_lo >= 0) {
448 jint t1_support = right_n_bits(1 + log2_intptr(t1->_hi));
449 if ((t1_support & con) == t1_support)
450 return in1;
451 }
452 // Masking off the high bits of a unsigned-shift-right is not
453 // needed either.
454 if (op == Op_URShiftI) {
455 const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
456 if (t12 && t12->is_con()) { // Shift is by a constant
457 int shift = t12->get_con();
458 shift &= BitsPerJavaInteger - 1; // semantics of Java shifts
459 int mask = max_juint >> shift;
460 if ((mask & con) == mask) // If AND is useless, skip it
461 return in1;
462 }
463 }
464 }
465 return MulNode::Identity(phase);
466 }
467
468 //------------------------------Ideal------------------------------------------
469 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
470 // Special case constant AND mask
471 const TypeInt *t2 = phase->type( in(2) )->isa_int();
472 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
473 const int mask = t2->get_con();
474 Node *load = in(1);
475 uint lop = load->Opcode();
476
477 // Masking bits off of a Character? Hi bits are already zero.
478 if( lop == Op_LoadUS &&
479 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
480 return new AndINode(load,phase->intcon(mask&0xFFFF));
481
482 // Masking bits off of a Short? Loading a Character does some masking
483 if (can_reshape &&
484 load->outcnt() == 1 && load->unique_out() == this) {
485 if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
486 Node* ldus = load->as_Load()->convert_to_unsigned_load(*phase);
487 ldus = phase->transform(ldus);
488 return new AndINode(ldus, phase->intcon(mask & 0xFFFF));
489 }
490
491 // Masking sign bits off of a Byte? Do an unsigned byte load plus
492 // an and.
493 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
494 Node* ldub = load->as_Load()->convert_to_unsigned_load(*phase);
495 ldub = phase->transform(ldub);
496 return new AndINode(ldub, phase->intcon(mask));
497 }
498 }
499
500 // Masking off sign bits? Dont make them!
501 if( lop == Op_RShiftI ) {
502 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
503 if( t12 && t12->is_con() ) { // Shift is by a constant
504 int shift = t12->get_con();
505 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
506 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
507 // If the AND'ing of the 2 masks has no bits, then only original shifted
508 // bits survive. NO sign-extension bits survive the maskings.
509 if( (sign_bits_mask & mask) == 0 ) {
510 // Use zero-fill shift instead
511 Node *zshift = phase->transform(new URShiftINode(load->in(1),load->in(2)));
512 return new AndINode( zshift, in(2) );
513 }
514 }
515 }
516
517 // Check for 'negate/and-1', a pattern emitted when someone asks for
518 // 'mod 2'. Negate leaves the low order bit unchanged (think: complement
519 // plus 1) and the mask is of the low order bit. Skip the negate.
520 if( lop == Op_SubI && mask == 1 && load->in(1) &&
521 phase->type(load->in(1)) == TypeInt::ZERO )
522 return new AndINode( load->in(2), in(2) );
523
524 return MulNode::Ideal(phase, can_reshape);
525 }
526
527 //=============================================================================
528 //------------------------------mul_ring---------------------------------------
529 // Supplied function returns the product of the inputs IN THE CURRENT RING.
530 // For the logical operations the ring's MUL is really a logical AND function.
531 // This also type-checks the inputs for sanity. Guaranteed never to
532 // be passed a TOP or BOTTOM type, these are filtered out by pre-check.
533 const Type *AndLNode::mul_ring( const Type *t0, const Type *t1 ) const {
534 const TypeLong *r0 = t0->is_long(); // Handy access
535 const TypeLong *r1 = t1->is_long();
536 int widen = MAX2(r0->_widen,r1->_widen);
537
538 // If either input is a constant, might be able to trim cases
539 if( !r0->is_con() && !r1->is_con() )
540 return TypeLong::LONG; // No constants to be had
554
555 //------------------------------Identity---------------------------------------
556 // Masking off the high bits of an unsigned load is not required
557 Node* AndLNode::Identity(PhaseGVN* phase) {
558
559 // x & x => x
560 if (phase->eqv(in(1), in(2))) return in(1);
561
562 Node *usr = in(1);
563 const TypeLong *t2 = phase->type( in(2) )->isa_long();
564 if( t2 && t2->is_con() ) {
565 jlong con = t2->get_con();
566 // Masking off high bits which are always zero is useless.
567 const TypeLong* t1 = phase->type( in(1) )->isa_long();
568 if (t1 != NULL && t1->_lo >= 0) {
569 int bit_count = log2_long(t1->_hi) + 1;
570 jlong t1_support = jlong(max_julong >> (BitsPerJavaLong - bit_count));
571 if ((t1_support & con) == t1_support)
572 return usr;
573 }
574 uint lop = usr->Opcode();
575 // Masking off the high bits of a unsigned-shift-right is not
576 // needed either.
577 if( lop == Op_URShiftL ) {
578 const TypeInt *t12 = phase->type( usr->in(2) )->isa_int();
579 if( t12 && t12->is_con() ) { // Shift is by a constant
580 int shift = t12->get_con();
581 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
582 jlong mask = max_julong >> shift;
583 if( (mask&con) == mask ) // If AND is useless, skip it
584 return usr;
585 }
586 }
587 }
588 return MulNode::Identity(phase);
589 }
590
591 //------------------------------Ideal------------------------------------------
592 Node *AndLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
593 // Special case constant AND mask
594 const TypeLong *t2 = phase->type( in(2) )->isa_long();
595 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
596 const jlong mask = t2->get_con();
597
598 Node* in1 = in(1);
599 uint op = in1->Opcode();
600
601 // Are we masking a long that was converted from an int with a mask
602 // that fits in 32-bits? Commute them and use an AndINode. Don't
603 // convert masks which would cause a sign extension of the integer
604 // value. This check includes UI2L masks (0x00000000FFFFFFFF) which
605 // would be optimized away later in Identity.
606 if (op == Op_ConvI2L && (mask & UCONST64(0xFFFFFFFF80000000)) == 0) {
607 Node* andi = new AndINode(in1->in(1), phase->intcon(mask));
608 andi = phase->transform(andi);
609 return new ConvI2LNode(andi);
610 }
611
612 // Masking off sign bits? Dont make them!
613 if (op == Op_RShiftL) {
614 const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
615 if( t12 && t12->is_con() ) { // Shift is by a constant
616 int shift = t12->get_con();
617 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
618 const jlong sign_bits_mask = ~(((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - shift)) -1);
619 // If the AND'ing of the 2 masks has no bits, then only original shifted
620 // bits survive. NO sign-extension bits survive the maskings.
621 if( (sign_bits_mask & mask) == 0 ) {
622 // Use zero-fill shift instead
623 Node *zshift = phase->transform(new URShiftLNode(in1->in(1), in1->in(2)));
624 return new AndLNode(zshift, in(2));
625 }
626 }
627 }
628
629 return MulNode::Ideal(phase, can_reshape);
630 }
631
632 //=============================================================================
633 //------------------------------Identity---------------------------------------
634 Node* LShiftINode::Identity(PhaseGVN* phase) {
635 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
636 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) ? in(1) : this;
637 }
638
639 //------------------------------Ideal------------------------------------------
640 // If the right input is a constant, and the left input is an add of a
641 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
642 Node *LShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
643 const Type *t = phase->type( in(2) );
644 if( t == Type::TOP ) return NULL; // Right input is dead
645 const TypeInt *t2 = t->isa_int();
646 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
647 const int con = t2->get_con() & ( BitsPerInt - 1 ); // masked shift count
648
649 if ( con == 0 ) return NULL; // let Identity() handle 0 shift count
650
651 // Left input is an add of a constant?
652 Node *add1 = in(1);
653 int add1_op = add1->Opcode();
654 if( add1_op == Op_AddI ) { // Left input is an add?
655 assert( add1 != add1->in(1), "dead loop in LShiftINode::Ideal" );
656 const TypeInt *t12 = phase->type(add1->in(2))->isa_int();
657 if( t12 && t12->is_con() ){ // Left input is an add of a con?
658 // Transform is legal, but check for profit. Avoid breaking 'i2s'
659 // and 'i2b' patterns which typically fold into 'StoreC/StoreB'.
660 if( con < 16 ) {
661 // Compute X << con0
662 Node *lsh = phase->transform( new LShiftINode( add1->in(1), in(2) ) );
663 // Compute X<<con0 + (con1<<con0)
664 return new AddINode( lsh, phase->intcon(t12->get_con() << con));
665 }
666 }
667 }
668
669 // Check for "(x>>c0)<<c0" which just masks off low bits
670 if( (add1_op == Op_RShiftI || add1_op == Op_URShiftI ) &&
671 add1->in(2) == in(2) )
672 // Convert to "(x & -(1<<c0))"
673 return new AndINode(add1->in(1),phase->intcon( -(1<<con)));
674
675 // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
676 if( add1_op == Op_AndI ) {
677 Node *add2 = add1->in(1);
678 int add2_op = add2->Opcode();
679 if( (add2_op == Op_RShiftI || add2_op == Op_URShiftI ) &&
680 add2->in(2) == in(2) ) {
681 // Convert to "(x & (Y<<c0))"
682 Node *y_sh = phase->transform( new LShiftINode( add1->in(2), in(2) ) );
683 return new AndINode( add2->in(1), y_sh );
684 }
685 }
686
687 // Check for ((x & ((1<<(32-c0))-1)) << c0) which ANDs off high bits
688 // before shifting them away.
689 const jint bits_mask = right_n_bits(BitsPerJavaInteger-con);
690 if( add1_op == Op_AndI &&
691 phase->type(add1->in(2)) == TypeInt::make( bits_mask ) )
692 return new LShiftINode( add1->in(1), in(2) );
693
694 return NULL;
695 }
696
697 //------------------------------Value------------------------------------------
698 // A LShiftINode shifts its input2 left by input1 amount.
699 const Type* LShiftINode::Value(PhaseGVN* phase) const {
700 const Type *t1 = phase->type( in(1) );
701 const Type *t2 = phase->type( in(2) );
702 // Either input is TOP ==> the result is TOP
703 if( t1 == Type::TOP ) return Type::TOP;
704 if( t2 == Type::TOP ) return Type::TOP;
705
706 // Left input is ZERO ==> the result is ZERO.
707 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
708 // Shift by zero does nothing
709 if( t2 == TypeInt::ZERO ) return t1;
710
745 //------------------------------Identity---------------------------------------
746 Node* LShiftLNode::Identity(PhaseGVN* phase) {
747 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
748 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
749 }
750
751 //------------------------------Ideal------------------------------------------
752 // If the right input is a constant, and the left input is an add of a
753 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
754 Node *LShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
755 const Type *t = phase->type( in(2) );
756 if( t == Type::TOP ) return NULL; // Right input is dead
757 const TypeInt *t2 = t->isa_int();
758 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
759 const int con = t2->get_con() & ( BitsPerLong - 1 ); // masked shift count
760
761 if ( con == 0 ) return NULL; // let Identity() handle 0 shift count
762
763 // Left input is an add of a constant?
764 Node *add1 = in(1);
765 int add1_op = add1->Opcode();
766 if( add1_op == Op_AddL ) { // Left input is an add?
767 // Avoid dead data cycles from dead loops
768 assert( add1 != add1->in(1), "dead loop in LShiftLNode::Ideal" );
769 const TypeLong *t12 = phase->type(add1->in(2))->isa_long();
770 if( t12 && t12->is_con() ){ // Left input is an add of a con?
771 // Compute X << con0
772 Node *lsh = phase->transform( new LShiftLNode( add1->in(1), in(2) ) );
773 // Compute X<<con0 + (con1<<con0)
774 return new AddLNode( lsh, phase->longcon(t12->get_con() << con));
775 }
776 }
777
778 // Check for "(x>>c0)<<c0" which just masks off low bits
779 if( (add1_op == Op_RShiftL || add1_op == Op_URShiftL ) &&
780 add1->in(2) == in(2) )
781 // Convert to "(x & -(1<<c0))"
782 return new AndLNode(add1->in(1),phase->longcon( -(CONST64(1)<<con)));
783
784 // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
785 if( add1_op == Op_AndL ) {
786 Node *add2 = add1->in(1);
787 int add2_op = add2->Opcode();
788 if( (add2_op == Op_RShiftL || add2_op == Op_URShiftL ) &&
789 add2->in(2) == in(2) ) {
790 // Convert to "(x & (Y<<c0))"
791 Node *y_sh = phase->transform( new LShiftLNode( add1->in(2), in(2) ) );
792 return new AndLNode( add2->in(1), y_sh );
793 }
794 }
795
796 // Check for ((x & ((CONST64(1)<<(64-c0))-1)) << c0) which ANDs off high bits
797 // before shifting them away.
798 const jlong bits_mask = jlong(max_julong >> con);
799 if( add1_op == Op_AndL &&
800 phase->type(add1->in(2)) == TypeLong::make( bits_mask ) )
801 return new LShiftLNode( add1->in(1), in(2) );
802
803 return NULL;
804 }
805
806 //------------------------------Value------------------------------------------
807 // A LShiftLNode shifts its input2 left by input1 amount.
808 const Type* LShiftLNode::Value(PhaseGVN* phase) const {
809 const Type *t1 = phase->type( in(1) );
810 const Type *t2 = phase->type( in(2) );
811 // Either input is TOP ==> the result is TOP
812 if( t1 == Type::TOP ) return Type::TOP;
813 if( t2 == Type::TOP ) return Type::TOP;
814
815 // Left input is ZERO ==> the result is ZERO.
816 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
817 // Shift by zero does nothing
818 if( t2 == TypeInt::ZERO ) return t1;
819
842 // No overflow. The range shifts up cleanly.
843 return TypeLong::make((jlong)lo << (jint)shift,
844 (jlong)hi << (jint)shift,
845 MAX2(r1->_widen,r2->_widen));
846 }
847 return TypeLong::LONG;
848 }
849
850 return TypeLong::make( (jlong)r1->get_con() << (jint)shift );
851 }
852
853 //=============================================================================
854 //------------------------------Identity---------------------------------------
855 Node* RShiftINode::Identity(PhaseGVN* phase) {
856 const TypeInt *t2 = phase->type(in(2))->isa_int();
857 if( !t2 ) return this;
858 if ( t2->is_con() && ( t2->get_con() & ( BitsPerInt - 1 ) ) == 0 )
859 return in(1);
860
861 // Check for useless sign-masking
862 if( in(1)->Opcode() == Op_LShiftI &&
863 in(1)->req() == 3 &&
864 in(1)->in(2) == in(2) &&
865 t2->is_con() ) {
866 uint shift = t2->get_con();
867 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
868 // Compute masks for which this shifting doesn't change
869 int lo = (-1 << (BitsPerJavaInteger - shift-1)); // FFFF8000
870 int hi = ~lo; // 00007FFF
871 const TypeInt *t11 = phase->type(in(1)->in(1))->isa_int();
872 if( !t11 ) return this;
873 // Does actual value fit inside of mask?
874 if( lo <= t11->_lo && t11->_hi <= hi )
875 return in(1)->in(1); // Then shifting is a nop
876 }
877
878 return this;
879 }
880
881 //------------------------------Ideal------------------------------------------
882 Node *RShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
883 // Inputs may be TOP if they are dead.
884 const TypeInt *t1 = phase->type( in(1) )->isa_int();
885 if( !t1 ) return NULL; // Left input is an integer
886 const TypeInt *t2 = phase->type( in(2) )->isa_int();
887 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
888 const TypeInt *t3; // type of in(1).in(2)
889 int shift = t2->get_con();
890 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
891
892 if ( shift == 0 ) return NULL; // let Identity() handle 0 shift count
893
894 // Check for (x & 0xFF000000) >> 24, whose mask can be made smaller.
895 // Such expressions arise normally from shift chains like (byte)(x >> 24).
896 const Node *mask = in(1);
897 if( mask->Opcode() == Op_AndI &&
898 (t3 = phase->type(mask->in(2))->isa_int()) &&
899 t3->is_con() ) {
900 Node *x = mask->in(1);
901 jint maskbits = t3->get_con();
902 // Convert to "(x >> shift) & (mask >> shift)"
903 Node *shr_nomask = phase->transform( new RShiftINode(mask->in(1), in(2)) );
904 return new AndINode(shr_nomask, phase->intcon( maskbits >> shift));
905 }
906
907 // Check for "(short[i] <<16)>>16" which simply sign-extends
908 const Node *shl = in(1);
909 if( shl->Opcode() != Op_LShiftI ) return NULL;
910
911 if( shift == 16 &&
912 (t3 = phase->type(shl->in(2))->isa_int()) &&
913 t3->is_con(16) ) {
914 Node *ld = shl->in(1);
915 if( ld->Opcode() == Op_LoadS ) {
916 // Sign extension is just useless here. Return a RShiftI of zero instead
917 // returning 'ld' directly. We cannot return an old Node directly as
918 // that is the job of 'Identity' calls and Identity calls only work on
919 // direct inputs ('ld' is an extra Node removed from 'this'). The
920 // combined optimization requires Identity only return direct inputs.
921 set_req(1, ld);
922 set_req(2, phase->intcon(0));
923 return this;
924 }
925 else if( can_reshape &&
926 ld->Opcode() == Op_LoadUS &&
927 ld->outcnt() == 1 && ld->unique_out() == shl)
928 // Replace zero-extension-load with sign-extension-load
929 return ld->as_Load()->convert_to_signed_load(*phase);
930 }
931
932 // Check for "(byte[i] <<24)>>24" which simply sign-extends
933 if( shift == 24 &&
934 (t3 = phase->type(shl->in(2))->isa_int()) &&
935 t3->is_con(24) ) {
936 Node *ld = shl->in(1);
937 if( ld->Opcode() == Op_LoadB ) {
938 // Sign extension is just useless here
939 set_req(1, ld);
940 set_req(2, phase->intcon(0));
941 return this;
942 }
943 }
944
945 return NULL;
946 }
947
948 //------------------------------Value------------------------------------------
949 // A RShiftINode shifts its input2 right by input1 amount.
950 const Type* RShiftINode::Value(PhaseGVN* phase) const {
951 const Type *t1 = phase->type( in(1) );
952 const Type *t2 = phase->type( in(2) );
953 // Either input is TOP ==> the result is TOP
954 if( t1 == Type::TOP ) return Type::TOP;
955 if( t2 == Type::TOP ) return Type::TOP;
956
957 // Left input is ZERO ==> the result is ZERO.
1051 if (r1->_lo >= 0) assert(tl == TypeLong::ZERO, ">>63 of + is 0");
1052 if (r1->_hi < 0) assert(tl == TypeLong::MINUS_1, ">>63 of - is -1");
1053 }
1054 #endif
1055 return tl;
1056 }
1057
1058 return TypeLong::LONG; // Give up
1059 }
1060
1061 //=============================================================================
1062 //------------------------------Identity---------------------------------------
1063 Node* URShiftINode::Identity(PhaseGVN* phase) {
1064 const TypeInt *ti = phase->type( in(2) )->isa_int();
1065 if ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) return in(1);
1066
1067 // Check for "((x << LogBytesPerWord) + (wordSize-1)) >> LogBytesPerWord" which is just "x".
1068 // Happens during new-array length computation.
1069 // Safe if 'x' is in the range [0..(max_int>>LogBytesPerWord)]
1070 Node *add = in(1);
1071 if( add->Opcode() == Op_AddI ) {
1072 const TypeInt *t2 = phase->type(add->in(2))->isa_int();
1073 if( t2 && t2->is_con(wordSize - 1) &&
1074 add->in(1)->Opcode() == Op_LShiftI ) {
1075 // Check that shift_counts are LogBytesPerWord
1076 Node *lshift_count = add->in(1)->in(2);
1077 const TypeInt *t_lshift_count = phase->type(lshift_count)->isa_int();
1078 if( t_lshift_count && t_lshift_count->is_con(LogBytesPerWord) &&
1079 t_lshift_count == phase->type(in(2)) ) {
1080 Node *x = add->in(1)->in(1);
1081 const TypeInt *t_x = phase->type(x)->isa_int();
1082 if( t_x != NULL && 0 <= t_x->_lo && t_x->_hi <= (max_jint>>LogBytesPerWord) ) {
1083 return x;
1084 }
1085 }
1086 }
1087 }
1088
1089 return (phase->type(in(2))->higher_equal(TypeInt::ZERO)) ? in(1) : this;
1090 }
1091
1092 //------------------------------Ideal------------------------------------------
1093 Node *URShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
1094 const TypeInt *t2 = phase->type( in(2) )->isa_int();
1095 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
1096 const int con = t2->get_con() & 31; // Shift count is always masked
1097 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count
1098 // We'll be wanting the right-shift amount as a mask of that many bits
1099 const int mask = right_n_bits(BitsPerJavaInteger - con);
1100
1101 int in1_op = in(1)->Opcode();
1102
1103 // Check for ((x>>>a)>>>b) and replace with (x>>>(a+b)) when a+b < 32
1104 if( in1_op == Op_URShiftI ) {
1105 const TypeInt *t12 = phase->type( in(1)->in(2) )->isa_int();
1106 if( t12 && t12->is_con() ) { // Right input is a constant
1107 assert( in(1) != in(1)->in(1), "dead loop in URShiftINode::Ideal" );
1108 const int con2 = t12->get_con() & 31; // Shift count is always masked
1109 const int con3 = con+con2;
1110 if( con3 < 32 ) // Only merge shifts if total is < 32
1111 return new URShiftINode( in(1)->in(1), phase->intcon(con3) );
1112 }
1113 }
1114
1115 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z
1116 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
1117 // If Q is "X << z" the rounding is useless. Look for patterns like
1118 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask.
1119 Node *add = in(1);
1120 if( in1_op == Op_AddI ) {
1121 Node *lshl = add->in(1);
1122 if( lshl->Opcode() == Op_LShiftI &&
1123 phase->type(lshl->in(2)) == t2 ) {
1124 Node *y_z = phase->transform( new URShiftINode(add->in(2),in(2)) );
1125 Node *sum = phase->transform( new AddINode( lshl->in(1), y_z ) );
1126 return new AndINode( sum, phase->intcon(mask) );
1127 }
1128 }
1129
1130 // Check for (x & mask) >>> z. Replace with (x >>> z) & (mask >>> z)
1131 // This shortens the mask. Also, if we are extracting a high byte and
1132 // storing it to a buffer, the mask will be removed completely.
1133 Node *andi = in(1);
1134 if( in1_op == Op_AndI ) {
1135 const TypeInt *t3 = phase->type( andi->in(2) )->isa_int();
1136 if( t3 && t3->is_con() ) { // Right input is a constant
1137 jint mask2 = t3->get_con();
1138 mask2 >>= con; // *signed* shift downward (high-order zeroes do not help)
1139 Node *newshr = phase->transform( new URShiftINode(andi->in(1), in(2)) );
1140 return new AndINode(newshr, phase->intcon(mask2));
1141 // The negative values are easier to materialize than positive ones.
1142 // A typical case from address arithmetic is ((x & ~15) >> 4).
1143 // It's better to change that to ((x >> 4) & ~0) versus
1144 // ((x >> 4) & 0x0FFFFFFF). The difference is greatest in LP64.
1145 }
1146 }
1147
1148 // Check for "(X << z ) >>> z" which simply zero-extends
1149 Node *shl = in(1);
1150 if( in1_op == Op_LShiftI &&
1151 phase->type(shl->in(2)) == t2 )
1152 return new AndINode( shl->in(1), phase->intcon(mask) );
1153
1154 return NULL;
1155 }
1156
1157 //------------------------------Value------------------------------------------
1158 // A URShiftINode shifts its input2 right by input1 amount.
1159 const Type* URShiftINode::Value(PhaseGVN* phase) const {
1160 // (This is a near clone of RShiftINode::Value.)
1161 const Type *t1 = phase->type( in(1) );
1162 const Type *t2 = phase->type( in(2) );
1163 // Either input is TOP ==> the result is TOP
1164 if( t1 == Type::TOP ) return Type::TOP;
1165 if( t2 == Type::TOP ) return Type::TOP;
1166
1167 // Left input is ZERO ==> the result is ZERO.
1168 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
1169 // Shift by zero does nothing
1170 if( t2 == TypeInt::ZERO ) return t1;
1233 Node* URShiftLNode::Identity(PhaseGVN* phase) {
1234 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
1235 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
1236 }
1237
1238 //------------------------------Ideal------------------------------------------
1239 Node *URShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
1240 const TypeInt *t2 = phase->type( in(2) )->isa_int();
1241 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
1242 const int con = t2->get_con() & ( BitsPerLong - 1 ); // Shift count is always masked
1243 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count
1244 // note: mask computation below does not work for 0 shift count
1245 // We'll be wanting the right-shift amount as a mask of that many bits
1246 const jlong mask = jlong(max_julong >> con);
1247
1248 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z
1249 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
1250 // If Q is "X << z" the rounding is useless. Look for patterns like
1251 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask.
1252 Node *add = in(1);
1253 if( add->Opcode() == Op_AddL ) {
1254 Node *lshl = add->in(1);
1255 if( lshl->Opcode() == Op_LShiftL &&
1256 phase->type(lshl->in(2)) == t2 ) {
1257 Node *y_z = phase->transform( new URShiftLNode(add->in(2),in(2)) );
1258 Node *sum = phase->transform( new AddLNode( lshl->in(1), y_z ) );
1259 return new AndLNode( sum, phase->longcon(mask) );
1260 }
1261 }
1262
1263 // Check for (x & mask) >>> z. Replace with (x >>> z) & (mask >>> z)
1264 // This shortens the mask. Also, if we are extracting a high byte and
1265 // storing it to a buffer, the mask will be removed completely.
1266 Node *andi = in(1);
1267 if( andi->Opcode() == Op_AndL ) {
1268 const TypeLong *t3 = phase->type( andi->in(2) )->isa_long();
1269 if( t3 && t3->is_con() ) { // Right input is a constant
1270 jlong mask2 = t3->get_con();
1271 mask2 >>= con; // *signed* shift downward (high-order zeroes do not help)
1272 Node *newshr = phase->transform( new URShiftLNode(andi->in(1), in(2)) );
1273 return new AndLNode(newshr, phase->longcon(mask2));
1274 }
1275 }
1276
1277 // Check for "(X << z ) >>> z" which simply zero-extends
1278 Node *shl = in(1);
1279 if( shl->Opcode() == Op_LShiftL &&
1280 phase->type(shl->in(2)) == t2 )
1281 return new AndLNode( shl->in(1), phase->longcon(mask) );
1282
1283 return NULL;
1284 }
1285
1286 //------------------------------Value------------------------------------------
1287 // A URShiftINode shifts its input2 right by input1 amount.
1288 const Type* URShiftLNode::Value(PhaseGVN* phase) const {
1289 // (This is a near clone of RShiftLNode::Value.)
1290 const Type *t1 = phase->type( in(1) );
1291 const Type *t2 = phase->type( in(2) );
1292 // Either input is TOP ==> the result is TOP
1293 if( t1 == Type::TOP ) return Type::TOP;
1294 if( t2 == Type::TOP ) return Type::TOP;
1295
1296 // Left input is ZERO ==> the result is ZERO.
1297 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
1298 // Shift by zero does nothing
1299 if( t2 == TypeInt::ZERO ) return t1;
|
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/connode.hpp"
29 #include "opto/convertnode.hpp"
30 #include "opto/memnode.hpp"
31 #include "opto/mulnode.hpp"
32 #include "opto/phaseX.hpp"
33 #include "opto/subnode.hpp"
34
35 // Portions of code courtesy of Clifford Click
36
37
38 //=============================================================================
39 //------------------------------hash-------------------------------------------
40 // Hash function over MulNodes. Needs to be commutative; i.e., I swap
41 // (commute) inputs to MulNodes willy-nilly so the hash function must return
42 // the same value in the presence of edge swapping.
43 uint MulNode::hash() const {
44 return (uintptr_t)in(1) + (uintptr_t)in(2) + static_cast<uint>(Opcode());
45 }
46
47 //------------------------------Identity---------------------------------------
48 // Multiplying a one preserves the other argument
49 Node* MulNode::Identity(PhaseGVN* phase) {
50 register const Type *one = mul_id(); // The multiplicative identity
51 if( phase->type( in(1) )->higher_equal( one ) ) return in(2);
52 if( phase->type( in(2) )->higher_equal( one ) ) return in(1);
53
54 return this;
55 }
56
57 //------------------------------Ideal------------------------------------------
58 // We also canonicalize the Node, moving constants to the right input,
59 // and flatten expressions (so that 1+x+2 becomes x+3).
60 Node *MulNode::Ideal(PhaseGVN *phase, bool can_reshape) {
61 const Type *t1 = phase->type( in(1) );
62 const Type *t2 = phase->type( in(2) );
63 Node *progress = NULL; // Progress flag
64 // We are OK if right is a constant, or right is a load and
65 // left is a non-constant.
66 if( !(t2->singleton() ||
67 (in(2)->is_Load() && !(t1->singleton() || in(1)->is_Load())) ) ) {
68 if( t1->singleton() || // Left input is a constant?
69 // Otherwise, sort inputs (commutativity) to help value numbering.
70 (in(1)->_idx > in(2)->_idx) ) {
71 swap_edges(1, 2);
72 const Type *t = t1;
73 t1 = t2;
74 t2 = t;
75 progress = this; // Made progress
76 }
77 }
78
79 // If the right input is a constant, and the left input is a product of a
80 // constant, flatten the expression tree.
81 Opcodes op = Opcode();
82 if( t2->singleton() && // Right input is a constant?
83 op != Opcodes::Op_MulF && // Float & double cannot reassociate
84 op != Opcodes::Op_MulD ) {
85 if( t2 == Type::TOP ) return NULL;
86 Node *mul1 = in(1);
87 #ifdef ASSERT
88 // Check for dead loop
89 Opcodes op1 = mul1->Opcode();
90 if( phase->eqv( mul1, this ) || phase->eqv( in(2), this ) ||
91 ( op1 == mul_opcode() || op1 == add_opcode() ) &&
92 ( phase->eqv( mul1->in(1), this ) || phase->eqv( mul1->in(2), this ) ||
93 phase->eqv( mul1->in(1), mul1 ) || phase->eqv( mul1->in(2), mul1 ) ) )
94 assert(false, "dead loop in MulNode::Ideal");
95 #endif
96
97 if( mul1->Opcode() == mul_opcode() ) { // Left input is a multiply?
98 // Mul of a constant?
99 const Type *t12 = phase->type( mul1->in(2) );
100 if( t12->singleton() && t12 != Type::TOP) { // Left input is an add of a constant?
101 // Compute new constant; check for overflow
102 const Type *tcon01 = ((MulNode*)mul1)->mul_ring(t2,t12);
103 if( tcon01->singleton() ) {
104 // The Mul of the flattened expression
105 set_req(1, mul1->in(1));
106 set_req(2, phase->makecon( tcon01 ));
107 t2 = tcon01;
108 progress = this; // Made progress
109 }
131 add2->set_req(2, phase->makecon(tcon01) );
132 progress = add2;
133 }
134 }
135 } // End of is left input an add
136 } // End of is right input a Mul
137
138 return progress;
139 }
140
141 //------------------------------Value-----------------------------------------
142 const Type* MulNode::Value(PhaseGVN* phase) const {
143 const Type *t1 = phase->type( in(1) );
144 const Type *t2 = phase->type( in(2) );
145 // Either input is TOP ==> the result is TOP
146 if( t1 == Type::TOP ) return Type::TOP;
147 if( t2 == Type::TOP ) return Type::TOP;
148
149 // Either input is ZERO ==> the result is ZERO.
150 // Not valid for floats or doubles since +0.0 * -0.0 --> +0.0
151 Opcodes op = Opcode();
152 if( op == Opcodes::Op_MulI || op == Opcodes::Op_AndI || op == Opcodes::Op_MulL || op == Opcodes::Op_AndL ) {
153 const Type *zero = add_id(); // The multiplicative zero
154 if( t1->higher_equal( zero ) ) return zero;
155 if( t2->higher_equal( zero ) ) return zero;
156 }
157
158 // Either input is BOTTOM ==> the result is the local BOTTOM
159 if( t1 == Type::BOTTOM || t2 == Type::BOTTOM )
160 return bottom_type();
161
162 #if defined(IA32)
163 // Can't trust native compilers to properly fold strict double
164 // multiplication with round-to-zero on this platform.
165 if (op == Opcodes::Op_MulD && phase->C->method()->is_strict()) {
166 return TypeD::DOUBLE;
167 }
168 #endif
169
170 return mul_ring(t1,t2); // Local flavor of type multiplication
171 }
172
173
174 //=============================================================================
175 //------------------------------Ideal------------------------------------------
176 // Check for power-of-2 multiply, then try the regular MulNode::Ideal
177 Node *MulINode::Ideal(PhaseGVN *phase, bool can_reshape) {
178 // Swap constant to right
179 jint con;
180 if ((con = in(1)->find_int_con(0)) != 0) {
181 swap_edges(1, 2);
182 // Finish rest of method to use info in 'con'
183 } else if ((con = in(2)->find_int_con(0)) == 0) {
184 return MulNode::Ideal(phase, can_reshape);
185 }
421 return TypeInt::make(0, r0->get_con(), widen);
422
423 if( r1->is_con() && r1->get_con() > 0 )
424 return TypeInt::make(0, r1->get_con(), widen);
425
426 if( r0 == TypeInt::BOOL || r1 == TypeInt::BOOL ) {
427 return TypeInt::BOOL;
428 }
429
430 return TypeInt::INT; // No constants to be had
431 }
432
433 //------------------------------Identity---------------------------------------
434 // Masking off the high bits of an unsigned load is not required
435 Node* AndINode::Identity(PhaseGVN* phase) {
436
437 // x & x => x
438 if (phase->eqv(in(1), in(2))) return in(1);
439
440 Node* in1 = in(1);
441 Opcodes op = in1->Opcode();
442 const TypeInt* t2 = phase->type(in(2))->isa_int();
443 if (t2 && t2->is_con()) {
444 int con = t2->get_con();
445 // Masking off high bits which are always zero is useless.
446 const TypeInt* t1 = phase->type( in(1) )->isa_int();
447 if (t1 != NULL && t1->_lo >= 0) {
448 jint t1_support = right_n_bits(1 + log2_intptr(t1->_hi));
449 if ((t1_support & con) == t1_support)
450 return in1;
451 }
452 // Masking off the high bits of a unsigned-shift-right is not
453 // needed either.
454 if (op == Opcodes::Op_URShiftI) {
455 const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
456 if (t12 && t12->is_con()) { // Shift is by a constant
457 int shift = t12->get_con();
458 shift &= BitsPerJavaInteger - 1; // semantics of Java shifts
459 int mask = max_juint >> shift;
460 if ((mask & con) == mask) // If AND is useless, skip it
461 return in1;
462 }
463 }
464 }
465 return MulNode::Identity(phase);
466 }
467
468 //------------------------------Ideal------------------------------------------
469 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
470 // Special case constant AND mask
471 const TypeInt *t2 = phase->type( in(2) )->isa_int();
472 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
473 const int mask = t2->get_con();
474 Node *load = in(1);
475 Opcodes lop = load->Opcode();
476
477 // Masking bits off of a Character? Hi bits are already zero.
478 if( lop == Opcodes::Op_LoadUS &&
479 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
480 return new AndINode(load,phase->intcon(mask&0xFFFF));
481
482 // Masking bits off of a Short? Loading a Character does some masking
483 if (can_reshape &&
484 load->outcnt() == 1 && load->unique_out() == this) {
485 if (lop == Opcodes::Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
486 Node* ldus = load->as_Load()->convert_to_unsigned_load(*phase);
487 ldus = phase->transform(ldus);
488 return new AndINode(ldus, phase->intcon(mask & 0xFFFF));
489 }
490
491 // Masking sign bits off of a Byte? Do an unsigned byte load plus
492 // an and.
493 if (lop == Opcodes::Op_LoadB && (mask & 0xFFFFFF00) == 0) {
494 Node* ldub = load->as_Load()->convert_to_unsigned_load(*phase);
495 ldub = phase->transform(ldub);
496 return new AndINode(ldub, phase->intcon(mask));
497 }
498 }
499
500 // Masking off sign bits? Dont make them!
501 if( lop == Opcodes::Op_RShiftI ) {
502 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
503 if( t12 && t12->is_con() ) { // Shift is by a constant
504 int shift = t12->get_con();
505 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
506 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
507 // If the AND'ing of the 2 masks has no bits, then only original shifted
508 // bits survive. NO sign-extension bits survive the maskings.
509 if( (sign_bits_mask & mask) == 0 ) {
510 // Use zero-fill shift instead
511 Node *zshift = phase->transform(new URShiftINode(load->in(1),load->in(2)));
512 return new AndINode( zshift, in(2) );
513 }
514 }
515 }
516
517 // Check for 'negate/and-1', a pattern emitted when someone asks for
518 // 'mod 2'. Negate leaves the low order bit unchanged (think: complement
519 // plus 1) and the mask is of the low order bit. Skip the negate.
520 if( lop == Opcodes::Op_SubI && mask == 1 && load->in(1) &&
521 phase->type(load->in(1)) == TypeInt::ZERO )
522 return new AndINode( load->in(2), in(2) );
523
524 return MulNode::Ideal(phase, can_reshape);
525 }
526
527 //=============================================================================
528 //------------------------------mul_ring---------------------------------------
529 // Supplied function returns the product of the inputs IN THE CURRENT RING.
530 // For the logical operations the ring's MUL is really a logical AND function.
531 // This also type-checks the inputs for sanity. Guaranteed never to
532 // be passed a TOP or BOTTOM type, these are filtered out by pre-check.
533 const Type *AndLNode::mul_ring( const Type *t0, const Type *t1 ) const {
534 const TypeLong *r0 = t0->is_long(); // Handy access
535 const TypeLong *r1 = t1->is_long();
536 int widen = MAX2(r0->_widen,r1->_widen);
537
538 // If either input is a constant, might be able to trim cases
539 if( !r0->is_con() && !r1->is_con() )
540 return TypeLong::LONG; // No constants to be had
554
555 //------------------------------Identity---------------------------------------
556 // Masking off the high bits of an unsigned load is not required
557 Node* AndLNode::Identity(PhaseGVN* phase) {
558
559 // x & x => x
560 if (phase->eqv(in(1), in(2))) return in(1);
561
562 Node *usr = in(1);
563 const TypeLong *t2 = phase->type( in(2) )->isa_long();
564 if( t2 && t2->is_con() ) {
565 jlong con = t2->get_con();
566 // Masking off high bits which are always zero is useless.
567 const TypeLong* t1 = phase->type( in(1) )->isa_long();
568 if (t1 != NULL && t1->_lo >= 0) {
569 int bit_count = log2_long(t1->_hi) + 1;
570 jlong t1_support = jlong(max_julong >> (BitsPerJavaLong - bit_count));
571 if ((t1_support & con) == t1_support)
572 return usr;
573 }
574 Opcodes lop = usr->Opcode();
575 // Masking off the high bits of a unsigned-shift-right is not
576 // needed either.
577 if( lop == Opcodes::Op_URShiftL ) {
578 const TypeInt *t12 = phase->type( usr->in(2) )->isa_int();
579 if( t12 && t12->is_con() ) { // Shift is by a constant
580 int shift = t12->get_con();
581 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
582 jlong mask = max_julong >> shift;
583 if( (mask&con) == mask ) // If AND is useless, skip it
584 return usr;
585 }
586 }
587 }
588 return MulNode::Identity(phase);
589 }
590
591 //------------------------------Ideal------------------------------------------
592 Node *AndLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
593 // Special case constant AND mask
594 const TypeLong *t2 = phase->type( in(2) )->isa_long();
595 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
596 const jlong mask = t2->get_con();
597
598 Node* in1 = in(1);
599 Opcodes op = in1->Opcode();
600
601 // Are we masking a long that was converted from an int with a mask
602 // that fits in 32-bits? Commute them and use an AndINode. Don't
603 // convert masks which would cause a sign extension of the integer
604 // value. This check includes UI2L masks (0x00000000FFFFFFFF) which
605 // would be optimized away later in Identity.
606 if (op == Opcodes::Op_ConvI2L && (mask & UCONST64(0xFFFFFFFF80000000)) == 0) {
607 Node* andi = new AndINode(in1->in(1), phase->intcon(mask));
608 andi = phase->transform(andi);
609 return new ConvI2LNode(andi);
610 }
611
612 // Masking off sign bits? Dont make them!
613 if (op == Opcodes::Op_RShiftL) {
614 const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
615 if( t12 && t12->is_con() ) { // Shift is by a constant
616 int shift = t12->get_con();
617 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
618 const jlong sign_bits_mask = ~(((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - shift)) -1);
619 // If the AND'ing of the 2 masks has no bits, then only original shifted
620 // bits survive. NO sign-extension bits survive the maskings.
621 if( (sign_bits_mask & mask) == 0 ) {
622 // Use zero-fill shift instead
623 Node *zshift = phase->transform(new URShiftLNode(in1->in(1), in1->in(2)));
624 return new AndLNode(zshift, in(2));
625 }
626 }
627 }
628
629 return MulNode::Ideal(phase, can_reshape);
630 }
631
632 //=============================================================================
633 //------------------------------Identity---------------------------------------
634 Node* LShiftINode::Identity(PhaseGVN* phase) {
635 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
636 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) ? in(1) : this;
637 }
638
639 //------------------------------Ideal------------------------------------------
640 // If the right input is a constant, and the left input is an add of a
641 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
642 Node *LShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
643 const Type *t = phase->type( in(2) );
644 if( t == Type::TOP ) return NULL; // Right input is dead
645 const TypeInt *t2 = t->isa_int();
646 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
647 const int con = t2->get_con() & ( BitsPerInt - 1 ); // masked shift count
648
649 if ( con == 0 ) return NULL; // let Identity() handle 0 shift count
650
651 // Left input is an add of a constant?
652 Node *add1 = in(1);
653 Opcodes add1_op = add1->Opcode();
654 if( add1_op == Opcodes::Op_AddI ) { // Left input is an add?
655 assert( add1 != add1->in(1), "dead loop in LShiftINode::Ideal" );
656 const TypeInt *t12 = phase->type(add1->in(2))->isa_int();
657 if( t12 && t12->is_con() ){ // Left input is an add of a con?
658 // Transform is legal, but check for profit. Avoid breaking 'i2s'
659 // and 'i2b' patterns which typically fold into 'StoreC/StoreB'.
660 if( con < 16 ) {
661 // Compute X << con0
662 Node *lsh = phase->transform( new LShiftINode( add1->in(1), in(2) ) );
663 // Compute X<<con0 + (con1<<con0)
664 return new AddINode( lsh, phase->intcon(t12->get_con() << con));
665 }
666 }
667 }
668
669 // Check for "(x>>c0)<<c0" which just masks off low bits
670 if( (add1_op == Opcodes::Op_RShiftI || add1_op == Opcodes::Op_URShiftI ) &&
671 add1->in(2) == in(2) )
672 // Convert to "(x & -(1<<c0))"
673 return new AndINode(add1->in(1),phase->intcon( -(1<<con)));
674
675 // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
676 if( add1_op == Opcodes::Op_AndI ) {
677 Node *add2 = add1->in(1);
678 Opcodes add2_op = add2->Opcode();
679 if( (add2_op == Opcodes::Op_RShiftI || add2_op == Opcodes::Op_URShiftI ) &&
680 add2->in(2) == in(2) ) {
681 // Convert to "(x & (Y<<c0))"
682 Node *y_sh = phase->transform( new LShiftINode( add1->in(2), in(2) ) );
683 return new AndINode( add2->in(1), y_sh );
684 }
685 }
686
687 // Check for ((x & ((1<<(32-c0))-1)) << c0) which ANDs off high bits
688 // before shifting them away.
689 const jint bits_mask = right_n_bits(BitsPerJavaInteger-con);
690 if( add1_op == Opcodes::Op_AndI &&
691 phase->type(add1->in(2)) == TypeInt::make( bits_mask ) )
692 return new LShiftINode( add1->in(1), in(2) );
693
694 return NULL;
695 }
696
697 //------------------------------Value------------------------------------------
698 // A LShiftINode shifts its input2 left by input1 amount.
699 const Type* LShiftINode::Value(PhaseGVN* phase) const {
700 const Type *t1 = phase->type( in(1) );
701 const Type *t2 = phase->type( in(2) );
702 // Either input is TOP ==> the result is TOP
703 if( t1 == Type::TOP ) return Type::TOP;
704 if( t2 == Type::TOP ) return Type::TOP;
705
706 // Left input is ZERO ==> the result is ZERO.
707 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
708 // Shift by zero does nothing
709 if( t2 == TypeInt::ZERO ) return t1;
710
745 //------------------------------Identity---------------------------------------
746 Node* LShiftLNode::Identity(PhaseGVN* phase) {
747 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
748 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
749 }
750
751 //------------------------------Ideal------------------------------------------
752 // If the right input is a constant, and the left input is an add of a
753 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
754 Node *LShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
755 const Type *t = phase->type( in(2) );
756 if( t == Type::TOP ) return NULL; // Right input is dead
757 const TypeInt *t2 = t->isa_int();
758 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
759 const int con = t2->get_con() & ( BitsPerLong - 1 ); // masked shift count
760
761 if ( con == 0 ) return NULL; // let Identity() handle 0 shift count
762
763 // Left input is an add of a constant?
764 Node *add1 = in(1);
765 Opcodes add1_op = add1->Opcode();
766 if( add1_op == Opcodes::Op_AddL ) { // Left input is an add?
767 // Avoid dead data cycles from dead loops
768 assert( add1 != add1->in(1), "dead loop in LShiftLNode::Ideal" );
769 const TypeLong *t12 = phase->type(add1->in(2))->isa_long();
770 if( t12 && t12->is_con() ){ // Left input is an add of a con?
771 // Compute X << con0
772 Node *lsh = phase->transform( new LShiftLNode( add1->in(1), in(2) ) );
773 // Compute X<<con0 + (con1<<con0)
774 return new AddLNode( lsh, phase->longcon(t12->get_con() << con));
775 }
776 }
777
778 // Check for "(x>>c0)<<c0" which just masks off low bits
779 if( (add1_op == Opcodes::Op_RShiftL || add1_op == Opcodes::Op_URShiftL ) &&
780 add1->in(2) == in(2) )
781 // Convert to "(x & -(1<<c0))"
782 return new AndLNode(add1->in(1),phase->longcon( -(CONST64(1)<<con)));
783
784 // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
785 if( add1_op == Opcodes::Op_AndL ) {
786 Node *add2 = add1->in(1);
787 Opcodes add2_op = add2->Opcode();
788 if( (add2_op == Opcodes::Op_RShiftL || add2_op == Opcodes::Op_URShiftL ) &&
789 add2->in(2) == in(2) ) {
790 // Convert to "(x & (Y<<c0))"
791 Node *y_sh = phase->transform( new LShiftLNode( add1->in(2), in(2) ) );
792 return new AndLNode( add2->in(1), y_sh );
793 }
794 }
795
796 // Check for ((x & ((CONST64(1)<<(64-c0))-1)) << c0) which ANDs off high bits
797 // before shifting them away.
798 const jlong bits_mask = jlong(max_julong >> con);
799 if( add1_op == Opcodes::Op_AndL &&
800 phase->type(add1->in(2)) == TypeLong::make( bits_mask ) )
801 return new LShiftLNode( add1->in(1), in(2) );
802
803 return NULL;
804 }
805
806 //------------------------------Value------------------------------------------
807 // A LShiftLNode shifts its input2 left by input1 amount.
808 const Type* LShiftLNode::Value(PhaseGVN* phase) const {
809 const Type *t1 = phase->type( in(1) );
810 const Type *t2 = phase->type( in(2) );
811 // Either input is TOP ==> the result is TOP
812 if( t1 == Type::TOP ) return Type::TOP;
813 if( t2 == Type::TOP ) return Type::TOP;
814
815 // Left input is ZERO ==> the result is ZERO.
816 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
817 // Shift by zero does nothing
818 if( t2 == TypeInt::ZERO ) return t1;
819
842 // No overflow. The range shifts up cleanly.
843 return TypeLong::make((jlong)lo << (jint)shift,
844 (jlong)hi << (jint)shift,
845 MAX2(r1->_widen,r2->_widen));
846 }
847 return TypeLong::LONG;
848 }
849
850 return TypeLong::make( (jlong)r1->get_con() << (jint)shift );
851 }
852
853 //=============================================================================
854 //------------------------------Identity---------------------------------------
855 Node* RShiftINode::Identity(PhaseGVN* phase) {
856 const TypeInt *t2 = phase->type(in(2))->isa_int();
857 if( !t2 ) return this;
858 if ( t2->is_con() && ( t2->get_con() & ( BitsPerInt - 1 ) ) == 0 )
859 return in(1);
860
861 // Check for useless sign-masking
862 if( in(1)->Opcode() == Opcodes::Op_LShiftI &&
863 in(1)->req() == 3 &&
864 in(1)->in(2) == in(2) &&
865 t2->is_con() ) {
866 uint shift = t2->get_con();
867 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
868 // Compute masks for which this shifting doesn't change
869 int lo = (-1 << (BitsPerJavaInteger - shift-1)); // FFFF8000
870 int hi = ~lo; // 00007FFF
871 const TypeInt *t11 = phase->type(in(1)->in(1))->isa_int();
872 if( !t11 ) return this;
873 // Does actual value fit inside of mask?
874 if( lo <= t11->_lo && t11->_hi <= hi )
875 return in(1)->in(1); // Then shifting is a nop
876 }
877
878 return this;
879 }
880
881 //------------------------------Ideal------------------------------------------
882 Node *RShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
883 // Inputs may be TOP if they are dead.
884 const TypeInt *t1 = phase->type( in(1) )->isa_int();
885 if( !t1 ) return NULL; // Left input is an integer
886 const TypeInt *t2 = phase->type( in(2) )->isa_int();
887 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
888 const TypeInt *t3; // type of in(1).in(2)
889 int shift = t2->get_con();
890 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
891
892 if ( shift == 0 ) return NULL; // let Identity() handle 0 shift count
893
894 // Check for (x & 0xFF000000) >> 24, whose mask can be made smaller.
895 // Such expressions arise normally from shift chains like (byte)(x >> 24).
896 const Node *mask = in(1);
897 if( mask->Opcode() == Opcodes::Op_AndI &&
898 (t3 = phase->type(mask->in(2))->isa_int()) &&
899 t3->is_con() ) {
900 Node *x = mask->in(1);
901 jint maskbits = t3->get_con();
902 // Convert to "(x >> shift) & (mask >> shift)"
903 Node *shr_nomask = phase->transform( new RShiftINode(mask->in(1), in(2)) );
904 return new AndINode(shr_nomask, phase->intcon( maskbits >> shift));
905 }
906
907 // Check for "(short[i] <<16)>>16" which simply sign-extends
908 const Node *shl = in(1);
909 if( shl->Opcode() != Opcodes::Op_LShiftI ) return NULL;
910
911 if( shift == 16 &&
912 (t3 = phase->type(shl->in(2))->isa_int()) &&
913 t3->is_con(16) ) {
914 Node *ld = shl->in(1);
915 if( ld->Opcode() == Opcodes::Op_LoadS ) {
916 // Sign extension is just useless here. Return a RShiftI of zero instead
917 // returning 'ld' directly. We cannot return an old Node directly as
918 // that is the job of 'Identity' calls and Identity calls only work on
919 // direct inputs ('ld' is an extra Node removed from 'this'). The
920 // combined optimization requires Identity only return direct inputs.
921 set_req(1, ld);
922 set_req(2, phase->intcon(0));
923 return this;
924 }
925 else if( can_reshape &&
926 ld->Opcode() == Opcodes::Op_LoadUS &&
927 ld->outcnt() == 1 && ld->unique_out() == shl)
928 // Replace zero-extension-load with sign-extension-load
929 return ld->as_Load()->convert_to_signed_load(*phase);
930 }
931
932 // Check for "(byte[i] <<24)>>24" which simply sign-extends
933 if( shift == 24 &&
934 (t3 = phase->type(shl->in(2))->isa_int()) &&
935 t3->is_con(24) ) {
936 Node *ld = shl->in(1);
937 if( ld->Opcode() == Opcodes::Op_LoadB ) {
938 // Sign extension is just useless here
939 set_req(1, ld);
940 set_req(2, phase->intcon(0));
941 return this;
942 }
943 }
944
945 return NULL;
946 }
947
948 //------------------------------Value------------------------------------------
949 // A RShiftINode shifts its input2 right by input1 amount.
950 const Type* RShiftINode::Value(PhaseGVN* phase) const {
951 const Type *t1 = phase->type( in(1) );
952 const Type *t2 = phase->type( in(2) );
953 // Either input is TOP ==> the result is TOP
954 if( t1 == Type::TOP ) return Type::TOP;
955 if( t2 == Type::TOP ) return Type::TOP;
956
957 // Left input is ZERO ==> the result is ZERO.
1051 if (r1->_lo >= 0) assert(tl == TypeLong::ZERO, ">>63 of + is 0");
1052 if (r1->_hi < 0) assert(tl == TypeLong::MINUS_1, ">>63 of - is -1");
1053 }
1054 #endif
1055 return tl;
1056 }
1057
1058 return TypeLong::LONG; // Give up
1059 }
1060
1061 //=============================================================================
1062 //------------------------------Identity---------------------------------------
1063 Node* URShiftINode::Identity(PhaseGVN* phase) {
1064 const TypeInt *ti = phase->type( in(2) )->isa_int();
1065 if ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) return in(1);
1066
1067 // Check for "((x << LogBytesPerWord) + (wordSize-1)) >> LogBytesPerWord" which is just "x".
1068 // Happens during new-array length computation.
1069 // Safe if 'x' is in the range [0..(max_int>>LogBytesPerWord)]
1070 Node *add = in(1);
1071 if( add->Opcode() == Opcodes::Op_AddI ) {
1072 const TypeInt *t2 = phase->type(add->in(2))->isa_int();
1073 if( t2 && t2->is_con(wordSize - 1) &&
1074 add->in(1)->Opcode() == Opcodes::Op_LShiftI ) {
1075 // Check that shift_counts are LogBytesPerWord
1076 Node *lshift_count = add->in(1)->in(2);
1077 const TypeInt *t_lshift_count = phase->type(lshift_count)->isa_int();
1078 if( t_lshift_count && t_lshift_count->is_con(LogBytesPerWord) &&
1079 t_lshift_count == phase->type(in(2)) ) {
1080 Node *x = add->in(1)->in(1);
1081 const TypeInt *t_x = phase->type(x)->isa_int();
1082 if( t_x != NULL && 0 <= t_x->_lo && t_x->_hi <= (max_jint>>LogBytesPerWord) ) {
1083 return x;
1084 }
1085 }
1086 }
1087 }
1088
1089 return (phase->type(in(2))->higher_equal(TypeInt::ZERO)) ? in(1) : this;
1090 }
1091
1092 //------------------------------Ideal------------------------------------------
1093 Node *URShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
1094 const TypeInt *t2 = phase->type( in(2) )->isa_int();
1095 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
1096 const int con = t2->get_con() & 31; // Shift count is always masked
1097 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count
1098 // We'll be wanting the right-shift amount as a mask of that many bits
1099 const int mask = right_n_bits(BitsPerJavaInteger - con);
1100
1101 Opcodes in1_op = in(1)->Opcode();
1102
1103 // Check for ((x>>>a)>>>b) and replace with (x>>>(a+b)) when a+b < 32
1104 if( in1_op == Opcodes::Op_URShiftI ) {
1105 const TypeInt *t12 = phase->type( in(1)->in(2) )->isa_int();
1106 if( t12 && t12->is_con() ) { // Right input is a constant
1107 assert( in(1) != in(1)->in(1), "dead loop in URShiftINode::Ideal" );
1108 const int con2 = t12->get_con() & 31; // Shift count is always masked
1109 const int con3 = con+con2;
1110 if( con3 < 32 ) // Only merge shifts if total is < 32
1111 return new URShiftINode( in(1)->in(1), phase->intcon(con3) );
1112 }
1113 }
1114
1115 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z
1116 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
1117 // If Q is "X << z" the rounding is useless. Look for patterns like
1118 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask.
1119 Node *add = in(1);
1120 if( in1_op == Opcodes::Op_AddI ) {
1121 Node *lshl = add->in(1);
1122 if( lshl->Opcode() == Opcodes::Op_LShiftI &&
1123 phase->type(lshl->in(2)) == t2 ) {
1124 Node *y_z = phase->transform( new URShiftINode(add->in(2),in(2)) );
1125 Node *sum = phase->transform( new AddINode( lshl->in(1), y_z ) );
1126 return new AndINode( sum, phase->intcon(mask) );
1127 }
1128 }
1129
1130 // Check for (x & mask) >>> z. Replace with (x >>> z) & (mask >>> z)
1131 // This shortens the mask. Also, if we are extracting a high byte and
1132 // storing it to a buffer, the mask will be removed completely.
1133 Node *andi = in(1);
1134 if( in1_op == Opcodes::Op_AndI ) {
1135 const TypeInt *t3 = phase->type( andi->in(2) )->isa_int();
1136 if( t3 && t3->is_con() ) { // Right input is a constant
1137 jint mask2 = t3->get_con();
1138 mask2 >>= con; // *signed* shift downward (high-order zeroes do not help)
1139 Node *newshr = phase->transform( new URShiftINode(andi->in(1), in(2)) );
1140 return new AndINode(newshr, phase->intcon(mask2));
1141 // The negative values are easier to materialize than positive ones.
1142 // A typical case from address arithmetic is ((x & ~15) >> 4).
1143 // It's better to change that to ((x >> 4) & ~0) versus
1144 // ((x >> 4) & 0x0FFFFFFF). The difference is greatest in LP64.
1145 }
1146 }
1147
1148 // Check for "(X << z ) >>> z" which simply zero-extends
1149 Node *shl = in(1);
1150 if( in1_op == Opcodes::Op_LShiftI &&
1151 phase->type(shl->in(2)) == t2 )
1152 return new AndINode( shl->in(1), phase->intcon(mask) );
1153
1154 return NULL;
1155 }
1156
1157 //------------------------------Value------------------------------------------
1158 // A URShiftINode shifts its input2 right by input1 amount.
1159 const Type* URShiftINode::Value(PhaseGVN* phase) const {
1160 // (This is a near clone of RShiftINode::Value.)
1161 const Type *t1 = phase->type( in(1) );
1162 const Type *t2 = phase->type( in(2) );
1163 // Either input is TOP ==> the result is TOP
1164 if( t1 == Type::TOP ) return Type::TOP;
1165 if( t2 == Type::TOP ) return Type::TOP;
1166
1167 // Left input is ZERO ==> the result is ZERO.
1168 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
1169 // Shift by zero does nothing
1170 if( t2 == TypeInt::ZERO ) return t1;
1233 Node* URShiftLNode::Identity(PhaseGVN* phase) {
1234 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
1235 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
1236 }
1237
1238 //------------------------------Ideal------------------------------------------
1239 Node *URShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
1240 const TypeInt *t2 = phase->type( in(2) )->isa_int();
1241 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
1242 const int con = t2->get_con() & ( BitsPerLong - 1 ); // Shift count is always masked
1243 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count
1244 // note: mask computation below does not work for 0 shift count
1245 // We'll be wanting the right-shift amount as a mask of that many bits
1246 const jlong mask = jlong(max_julong >> con);
1247
1248 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z
1249 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
1250 // If Q is "X << z" the rounding is useless. Look for patterns like
1251 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask.
1252 Node *add = in(1);
1253 if( add->Opcode() == Opcodes::Op_AddL ) {
1254 Node *lshl = add->in(1);
1255 if( lshl->Opcode() == Opcodes::Op_LShiftL &&
1256 phase->type(lshl->in(2)) == t2 ) {
1257 Node *y_z = phase->transform( new URShiftLNode(add->in(2),in(2)) );
1258 Node *sum = phase->transform( new AddLNode( lshl->in(1), y_z ) );
1259 return new AndLNode( sum, phase->longcon(mask) );
1260 }
1261 }
1262
1263 // Check for (x & mask) >>> z. Replace with (x >>> z) & (mask >>> z)
1264 // This shortens the mask. Also, if we are extracting a high byte and
1265 // storing it to a buffer, the mask will be removed completely.
1266 Node *andi = in(1);
1267 if( andi->Opcode() == Opcodes::Op_AndL ) {
1268 const TypeLong *t3 = phase->type( andi->in(2) )->isa_long();
1269 if( t3 && t3->is_con() ) { // Right input is a constant
1270 jlong mask2 = t3->get_con();
1271 mask2 >>= con; // *signed* shift downward (high-order zeroes do not help)
1272 Node *newshr = phase->transform( new URShiftLNode(andi->in(1), in(2)) );
1273 return new AndLNode(newshr, phase->longcon(mask2));
1274 }
1275 }
1276
1277 // Check for "(X << z ) >>> z" which simply zero-extends
1278 Node *shl = in(1);
1279 if( shl->Opcode() == Opcodes::Op_LShiftL &&
1280 phase->type(shl->in(2)) == t2 )
1281 return new AndLNode( shl->in(1), phase->longcon(mask) );
1282
1283 return NULL;
1284 }
1285
1286 //------------------------------Value------------------------------------------
1287 // A URShiftINode shifts its input2 right by input1 amount.
1288 const Type* URShiftLNode::Value(PhaseGVN* phase) const {
1289 // (This is a near clone of RShiftLNode::Value.)
1290 const Type *t1 = phase->type( in(1) );
1291 const Type *t2 = phase->type( in(2) );
1292 // Either input is TOP ==> the result is TOP
1293 if( t1 == Type::TOP ) return Type::TOP;
1294 if( t2 == Type::TOP ) return Type::TOP;
1295
1296 // Left input is ZERO ==> the result is ZERO.
1297 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
1298 // Shift by zero does nothing
1299 if( t2 == TypeInt::ZERO ) return t1;
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