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src/share/vm/opto/regmask.cpp

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*** 113,140 **** # undef BODY 0 ); //============================================================================= ! bool RegMask::is_vector(uint ireg) { ! return (ireg == Op_VecS || ireg == Op_VecD || ! ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ); } ! int RegMask::num_registers(uint ireg) { switch(ireg) { ! case Op_VecZ: return 16; ! case Op_VecY: return 8; ! case Op_VecX: return 4; ! case Op_VecD: ! case Op_RegD: ! case Op_RegL: #ifdef _LP64 ! case Op_RegP: #endif return 2; } // Op_VecS and the rest ideal registers. return 1; --- 113,140 ---- # undef BODY 0 ); //============================================================================= ! bool RegMask::is_vector(Opcodes ireg) { ! return (ireg == Opcodes::Op_VecS || ireg == Opcodes::Op_VecD || ! ireg == Opcodes::Op_VecX || ireg == Opcodes::Op_VecY || ireg == Opcodes::Op_VecZ ); } ! int RegMask::num_registers(Opcodes ireg) { switch(ireg) { ! case Opcodes::Op_VecZ: return 16; ! case Opcodes::Op_VecY: return 8; ! case Opcodes::Op_VecX: return 4; ! case Opcodes::Op_VecD: ! case Opcodes::Op_RegD: ! case Opcodes::Op_RegL: #ifdef _LP64 ! case Opcodes::Op_RegP: #endif return 2; } // Op_VecS and the rest ideal registers. return 1;
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