src/share/vm/opto/regmask.cpp

@@ -113,28 +113,28 @@
 # undef BODY
   0
 );
 
 //=============================================================================
-bool RegMask::is_vector(uint ireg) {
-  return (ireg == Op_VecS || ireg == Op_VecD ||
-          ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ );
+bool RegMask::is_vector(Opcodes ireg) {
+  return (ireg == Opcodes::Op_VecS || ireg == Opcodes::Op_VecD ||
+          ireg == Opcodes::Op_VecX || ireg == Opcodes::Op_VecY || ireg == Opcodes::Op_VecZ );
 }
 
-int RegMask::num_registers(uint ireg) {
+int RegMask::num_registers(Opcodes ireg) {
     switch(ireg) {
-      case Op_VecZ:
+      case Opcodes::Op_VecZ:
         return 16;
-      case Op_VecY:
+      case Opcodes::Op_VecY:
         return 8;
-      case Op_VecX:
+      case Opcodes::Op_VecX:
         return 4;
-      case Op_VecD:
-      case Op_RegD:
-      case Op_RegL:
+      case Opcodes::Op_VecD:
+      case Opcodes::Op_RegD:
+      case Opcodes::Op_RegL:
 #ifdef _LP64
-      case Op_RegP:
+      case Opcodes::Op_RegP:
 #endif
         return 2;
     }
     // Op_VecS and the rest ideal registers.
     return 1;