1 /*
   2  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
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  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  24 
  25 #ifndef SHARE_VM_OPTO_REGMASK_HPP
  26 #define SHARE_VM_OPTO_REGMASK_HPP
  27 
  28 #include "code/vmreg.hpp"
  29 #include "opto/opcodes.hpp"
  30 #include "opto/optoreg.hpp"
  31 
  32 // Some fun naming (textual) substitutions:
  33 //
  34 // RegMask::get_low_elem() ==> RegMask::find_first_elem()
  35 // RegMask::Special        ==> RegMask::Empty
  36 // RegMask::_flags         ==> RegMask::is_AllStack()
  37 // RegMask::operator<<=()  ==> RegMask::Insert()
  38 // RegMask::operator>>=()  ==> RegMask::Remove()
  39 // RegMask::Union()        ==> RegMask::OR
  40 // RegMask::Inter()        ==> RegMask::AND
  41 //
  42 // OptoRegister::RegName   ==> OptoReg::Name
  43 //
  44 // OptoReg::stack0()       ==> _last_Mach_Reg  or ZERO in core version
  45 //
  46 // numregs in chaitin      ==> proper degree in chaitin
  47 
  48 //-------------Non-zero bit search methods used by RegMask---------------------
  49 // Find lowest 1, or return 32 if empty
  50 int find_lowest_bit( uint32_t mask );
  51 // Find highest 1, or return 32 if empty
  52 int find_hihghest_bit( uint32_t mask );
  53 
  54 //------------------------------RegMask----------------------------------------
  55 // The ADL file describes how to print the machine-specific registers, as well
  56 // as any notion of register classes.  We provide a register mask, which is
  57 // just a collection of Register numbers.
  58 
  59 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
  60 // RM_SIZE is the size of a register mask in words.
  61 // FORALL_BODY replicates a BODY macro once per word in the register mask.
  62 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
  63 // However, it means the ADLC can redefine the unroll macro and all loops
  64 // over register masks will be unrolled by the correct amount.
  65 
  66 class RegMask VALUE_OBJ_CLASS_SPEC {
  67   union {
  68     double _dummy_force_double_alignment[RM_SIZE>>1];
  69     // Array of Register Mask bits.  This array is large enough to cover
  70     // all the machine registers and all parameters that need to be passed
  71     // on the stack (stack registers) up to some interesting limit.  Methods
  72     // that need more parameters will NOT be compiled.  On Intel, the limit
  73     // is something like 90+ parameters.
  74     int _A[RM_SIZE];
  75   };
  76 
  77   enum {
  78     _WordBits    = BitsPerInt,
  79     _LogWordBits = LogBitsPerInt,
  80     _RM_SIZE     = RM_SIZE   // local constant, imported, then hidden by #undef
  81   };
  82 
  83 public:
  84   enum { CHUNK_SIZE = RM_SIZE*_WordBits };
  85 
  86   // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
  87   // Also, consider the maximum alignment size for a normally allocated
  88   // value.  Since we allocate register pairs but not register quads (at
  89   // present), this alignment is SlotsPerLong (== 2).  A normally
  90   // aligned allocated register is either a single register, or a pair
  91   // of adjacent registers, the lower-numbered being even.
  92   // See also is_aligned_Pairs() below, and the padding added before
  93   // Matcher::_new_SP to keep allocated pairs aligned properly.
  94   // If we ever go to quad-word allocations, SlotsPerQuad will become
  95   // the controlling alignment constraint.  Note that this alignment
  96   // requirement is internal to the allocator, and independent of any
  97   // particular platform.
  98   enum { SlotsPerLong = 2,
  99          SlotsPerVecS = 1,
 100          SlotsPerVecD = 2,
 101          SlotsPerVecX = 4,
 102          SlotsPerVecY = 8,
 103          SlotsPerVecZ = 16 };
 104 
 105   // A constructor only used by the ADLC output.  All mask fields are filled
 106   // in directly.  Calls to this look something like RM(1,2,3,4);
 107   RegMask(
 108 #   define BODY(I) int a##I,
 109     FORALL_BODY
 110 #   undef BODY
 111     int dummy = 0 ) {
 112 #   define BODY(I) _A[I] = a##I;
 113     FORALL_BODY
 114 #   undef BODY
 115   }
 116 
 117   // Handy copying constructor
 118   RegMask( RegMask *rm ) {
 119 #   define BODY(I) _A[I] = rm->_A[I];
 120     FORALL_BODY
 121 #   undef BODY
 122   }
 123 
 124   // Construct an empty mask
 125   RegMask( ) { Clear(); }
 126 
 127   // Construct a mask with a single bit
 128   RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); }
 129 
 130   // Check for register being in mask
 131   int Member( OptoReg::Name reg ) const {
 132     assert( reg < CHUNK_SIZE, "" );
 133     return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1)));
 134   }
 135 
 136   // The last bit in the register mask indicates that the mask should repeat
 137   // indefinitely with ONE bits.  Returns TRUE if mask is infinite or
 138   // unbounded in size.  Returns FALSE if mask is finite size.
 139   int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); }
 140 
 141   // Work around an -xO3 optimization problme in WS6U1. The old way:
 142   //   void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); }
 143   // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack()
 144   // follows an Insert() loop, like the one found in init_spill_mask(). Using
 145   // Insert() instead works because the index into _A in computed instead of
 146   // constant.  See bug 4665841.
 147   void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); }
 148 
 149   // Test for being a not-empty mask.
 150   int is_NotEmpty( ) const {
 151     int tmp = 0;
 152 #   define BODY(I) tmp |= _A[I];
 153     FORALL_BODY
 154 #   undef BODY
 155     return tmp;
 156   }
 157 
 158   // Find lowest-numbered register from mask, or BAD if mask is empty.
 159   OptoReg::Name find_first_elem() const {
 160     int base, bits;
 161 #   define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else
 162     FORALL_BODY
 163 #   undef BODY
 164       { base = OptoReg::Bad; bits = 1<<0; }
 165     return OptoReg::Name(base + find_lowest_bit(bits));
 166   }
 167   // Get highest-numbered register from mask, or BAD if mask is empty.
 168   OptoReg::Name find_last_elem() const {
 169     int base, bits;
 170 #   define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else
 171     FORALL_BODY
 172 #   undef BODY
 173       { base = OptoReg::Bad; bits = 1<<0; }
 174     return OptoReg::Name(base + find_hihghest_bit(bits));
 175   }
 176 
 177   // Find the lowest-numbered register pair in the mask.  Return the
 178   // HIGHEST register number in the pair, or BAD if no pairs.
 179   // Assert that the mask contains only bit pairs.
 180   OptoReg::Name find_first_pair() const;
 181 
 182   // Clear out partial bits; leave only aligned adjacent bit pairs.
 183   void clear_to_pairs();
 184   // Smear out partial bits; leave only aligned adjacent bit pairs.
 185   void smear_to_pairs();
 186   // Verify that the mask contains only aligned adjacent bit pairs
 187   void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); }
 188   // Test that the mask contains only aligned adjacent bit pairs
 189   bool is_aligned_pairs() const;
 190 
 191   // mask is a pair of misaligned registers
 192   bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); }
 193   // Test for single register
 194   int is_bound1() const;
 195   // Test for a single adjacent pair
 196   int is_bound_pair() const;
 197   // Test for a single adjacent set of ideal register's size.
 198   int is_bound(Opcodes ireg) const {
 199     if (is_vector(ireg)) {
 200       if (is_bound_set(num_registers(ireg)))
 201         return true;
 202     } else if (is_bound1() || is_bound_pair()) {
 203       return true;
 204     }
 205     return false;
 206   }
 207 
 208   // Find the lowest-numbered register set in the mask.  Return the
 209   // HIGHEST register number in the set, or BAD if no sets.
 210   // Assert that the mask contains only bit sets.
 211   OptoReg::Name find_first_set(const int size) const;
 212 
 213   // Clear out partial bits; leave only aligned adjacent bit sets of size.
 214   void clear_to_sets(const int size);
 215   // Smear out partial bits to aligned adjacent bit sets.
 216   void smear_to_sets(const int size);
 217   // Verify that the mask contains only aligned adjacent bit sets
 218   void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); }
 219   // Test that the mask contains only aligned adjacent bit sets
 220   bool is_aligned_sets(const int size) const;
 221 
 222   // mask is a set of misaligned registers
 223   bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);}
 224 
 225   // Test for a single adjacent set
 226   int is_bound_set(const int size) const;
 227 
 228   static bool is_vector(Opcodes ireg);
 229   static int num_registers(Opcodes ireg);
 230 
 231   // Fast overlap test.  Non-zero if any registers in common.
 232   int overlap( const RegMask &rm ) const {
 233     return
 234 #   define BODY(I) (_A[I] & rm._A[I]) |
 235     FORALL_BODY
 236 #   undef BODY
 237     0 ;
 238   }
 239 
 240   // Special test for register pressure based splitting
 241   // UP means register only, Register plus stack, or stack only is DOWN
 242   bool is_UP() const;
 243 
 244   // Clear a register mask
 245   void Clear( ) {
 246 #   define BODY(I) _A[I] = 0;
 247     FORALL_BODY
 248 #   undef BODY
 249   }
 250 
 251   // Fill a register mask with 1's
 252   void Set_All( ) {
 253 #   define BODY(I) _A[I] = -1;
 254     FORALL_BODY
 255 #   undef BODY
 256   }
 257 
 258   // Insert register into mask
 259   void Insert( OptoReg::Name reg ) {
 260     assert( reg < CHUNK_SIZE, "" );
 261     _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1)));
 262   }
 263 
 264   // Remove register from mask
 265   void Remove( OptoReg::Name reg ) {
 266     assert( reg < CHUNK_SIZE, "" );
 267     _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1)));
 268   }
 269 
 270   // OR 'rm' into 'this'
 271   void OR( const RegMask &rm ) {
 272 #   define BODY(I) this->_A[I] |= rm._A[I];
 273     FORALL_BODY
 274 #   undef BODY
 275   }
 276 
 277   // AND 'rm' into 'this'
 278   void AND( const RegMask &rm ) {
 279 #   define BODY(I) this->_A[I] &= rm._A[I];
 280     FORALL_BODY
 281 #   undef BODY
 282   }
 283 
 284   // Subtract 'rm' from 'this'
 285   void SUBTRACT( const RegMask &rm ) {
 286 #   define BODY(I) _A[I] &= ~rm._A[I];
 287     FORALL_BODY
 288 #   undef BODY
 289   }
 290 
 291   // Compute size of register mask: number of bits
 292   uint Size() const;
 293 
 294 #ifndef PRODUCT
 295   void print() const { dump(); }
 296   void dump(outputStream *st = tty) const; // Print a mask
 297 #endif
 298 
 299   static const RegMask Empty;   // Common empty mask
 300 
 301   static bool can_represent(OptoReg::Name reg) {
 302     // NOTE: -1 in computation reflects the usage of the last
 303     //       bit of the regmask as an infinite stack flag and
 304     //       -7 is to keep mask aligned for largest value (VecZ).
 305     return (int)reg < (int)(CHUNK_SIZE-1);
 306   }
 307   static bool can_represent_arg(OptoReg::Name reg) {
 308     // NOTE: -SlotsPerVecZ in computation reflects the need
 309     //       to keep mask aligned for largest value (VecZ).
 310     return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecZ);
 311   }
 312 };
 313 
 314 // Do not use this constant directly in client code!
 315 #undef RM_SIZE
 316 
 317 #endif // SHARE_VM_OPTO_REGMASK_HPP