1 /*
   2  * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_VERSION_X86_HPP
  26 #define CPU_X86_VM_VERSION_X86_HPP
  27 
  28 #include "memory/universe.hpp"
  29 #include "runtime/abstract_vm_version.hpp"
  30 #include "runtime/globals_extension.hpp"
  31 
  32 class VM_Version : public Abstract_VM_Version {
  33   friend class VMStructs;
  34   friend class JVMCIVMStructs;
  35 
  36  public:
  37   // cpuid result register layouts.  These are all unions of a uint32_t
  38   // (in case anyone wants access to the register as a whole) and a bitfield.
  39 
  40   union StdCpuid1Eax {
  41     uint32_t value;
  42     struct {
  43       uint32_t stepping   : 4,
  44                model      : 4,
  45                family     : 4,
  46                proc_type  : 2,
  47                           : 2,
  48                ext_model  : 4,
  49                ext_family : 8,
  50                           : 4;
  51     } bits;
  52   };
  53 
  54   union StdCpuid1Ebx { // example, unused
  55     uint32_t value;
  56     struct {
  57       uint32_t brand_id         : 8,
  58                clflush_size     : 8,
  59                threads_per_cpu  : 8,
  60                apic_id          : 8;
  61     } bits;
  62   };
  63 
  64   union StdCpuid1Ecx {
  65     uint32_t value;
  66     struct {
  67       uint32_t sse3     : 1,
  68                clmul    : 1,
  69                         : 1,
  70                monitor  : 1,
  71                         : 1,
  72                vmx      : 1,
  73                         : 1,
  74                est      : 1,
  75                         : 1,
  76                ssse3    : 1,
  77                cid      : 1,
  78                         : 1,
  79                fma      : 1,
  80                cmpxchg16: 1,
  81                         : 4,
  82                dca      : 1,
  83                sse4_1   : 1,
  84                sse4_2   : 1,
  85                         : 2,
  86                popcnt   : 1,
  87                         : 1,
  88                aes      : 1,
  89                         : 1,
  90                osxsave  : 1,
  91                avx      : 1,
  92                         : 2,
  93                hv       : 1;
  94     } bits;
  95   };
  96 
  97   union StdCpuid1Edx {
  98     uint32_t value;
  99     struct {
 100       uint32_t          : 4,
 101                tsc      : 1,
 102                         : 3,
 103                cmpxchg8 : 1,
 104                         : 6,
 105                cmov     : 1,
 106                         : 3,
 107                clflush  : 1,
 108                         : 3,
 109                mmx      : 1,
 110                fxsr     : 1,
 111                sse      : 1,
 112                sse2     : 1,
 113                         : 1,
 114                ht       : 1,
 115                         : 3;
 116     } bits;
 117   };
 118 
 119   union DcpCpuid4Eax {
 120     uint32_t value;
 121     struct {
 122       uint32_t cache_type    : 5,
 123                              : 21,
 124                cores_per_cpu : 6;
 125     } bits;
 126   };
 127 
 128   union DcpCpuid4Ebx {
 129     uint32_t value;
 130     struct {
 131       uint32_t L1_line_size  : 12,
 132                partitions    : 10,
 133                associativity : 10;
 134     } bits;
 135   };
 136 
 137   union TplCpuidBEbx {
 138     uint32_t value;
 139     struct {
 140       uint32_t logical_cpus : 16,
 141                             : 16;
 142     } bits;
 143   };
 144 
 145   union ExtCpuid1Ecx {
 146     uint32_t value;
 147     struct {
 148       uint32_t LahfSahf     : 1,
 149                CmpLegacy    : 1,
 150                             : 3,
 151                lzcnt_intel  : 1,
 152                lzcnt        : 1,
 153                sse4a        : 1,
 154                misalignsse  : 1,
 155                prefetchw    : 1,
 156                             : 22;
 157     } bits;
 158   };
 159 
 160   union ExtCpuid1Edx {
 161     uint32_t value;
 162     struct {
 163       uint32_t           : 22,
 164                mmx_amd   : 1,
 165                mmx       : 1,
 166                fxsr      : 1,
 167                          : 4,
 168                long_mode : 1,
 169                tdnow2    : 1,
 170                tdnow     : 1;
 171     } bits;
 172   };
 173 
 174   union ExtCpuid5Ex {
 175     uint32_t value;
 176     struct {
 177       uint32_t L1_line_size : 8,
 178                L1_tag_lines : 8,
 179                L1_assoc     : 8,
 180                L1_size      : 8;
 181     } bits;
 182   };
 183 
 184   union ExtCpuid7Edx {
 185     uint32_t value;
 186     struct {
 187       uint32_t               : 8,
 188               tsc_invariance : 1,
 189                              : 23;
 190     } bits;
 191   };
 192 
 193   union ExtCpuid8Ecx {
 194     uint32_t value;
 195     struct {
 196       uint32_t cores_per_cpu : 8,
 197                              : 24;
 198     } bits;
 199   };
 200 
 201   union SefCpuid7Eax {
 202     uint32_t value;
 203   };
 204 
 205   union SefCpuid7Ebx {
 206     uint32_t value;
 207     struct {
 208       uint32_t fsgsbase : 1,
 209                         : 2,
 210                    bmi1 : 1,
 211                         : 1,
 212                    avx2 : 1,
 213                         : 2,
 214                    bmi2 : 1,
 215                    erms : 1,
 216                         : 1,
 217                     rtm : 1,
 218                         : 4,
 219                 avx512f : 1,
 220                avx512dq : 1,
 221                         : 1,
 222                     adx : 1,
 223                         : 3,
 224              clflushopt : 1,
 225                    clwb : 1,
 226                         : 1,
 227                avx512pf : 1,
 228                avx512er : 1,
 229                avx512cd : 1,
 230                     sha : 1,
 231                avx512bw : 1,
 232                avx512vl : 1;
 233     } bits;
 234   };
 235 
 236   union SefCpuid7Ecx {
 237     uint32_t value;
 238     struct {
 239       uint32_t prefetchwt1 : 1,
 240                avx512_vbmi : 1,
 241                       umip : 1,
 242                        pku : 1,
 243                      ospke : 1,
 244                            : 1,
 245               avx512_vbmi2 : 1,
 246                            : 1,
 247                       gfni : 1,
 248                       vaes : 1,
 249          avx512_vpclmulqdq : 1,
 250                avx512_vnni : 1,
 251              avx512_bitalg : 1,
 252                            : 1,
 253           avx512_vpopcntdq : 1,
 254                            : 17;
 255     } bits;
 256   };
 257 
 258   union SefCpuid7Edx {
 259     uint32_t value;
 260     struct {
 261       uint32_t             : 2,
 262              avx512_4vnniw : 1,
 263              avx512_4fmaps : 1,
 264                            : 28;
 265     } bits;
 266   };
 267 
 268   union ExtCpuid1EEbx {
 269     uint32_t value;
 270     struct {
 271       uint32_t                  : 8,
 272                threads_per_core : 8,
 273                                 : 16;
 274     } bits;
 275   };
 276 
 277   union XemXcr0Eax {
 278     uint32_t value;
 279     struct {
 280       uint32_t x87     : 1,
 281                sse     : 1,
 282                ymm     : 1,
 283                bndregs : 1,
 284                bndcsr  : 1,
 285                opmask  : 1,
 286                zmm512  : 1,
 287                zmm32   : 1,
 288                        : 24;
 289     } bits;
 290   };
 291 
 292 protected:
 293   static int _cpu;
 294   static int _model;
 295   static int _stepping;
 296 
 297   static bool _has_intel_jcc_erratum;
 298 
 299   static address   _cpuinfo_segv_addr; // address of instruction which causes SEGV
 300   static address   _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
 301 
 302   enum Feature_Flag {
 303     CPU_CX8      = (1 << 0), // next bits are from cpuid 1 (EDX)
 304     CPU_CMOV     = (1 << 1),
 305     CPU_FXSR     = (1 << 2),
 306     CPU_HT       = (1 << 3),
 307     CPU_MMX      = (1 << 4),
 308     CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
 309                                    // may not necessarily support other 3dnow instructions
 310     CPU_SSE      = (1 << 6),
 311     CPU_SSE2     = (1 << 7),
 312     CPU_SSE3     = (1 << 8),  // SSE3 comes from cpuid 1 (ECX)
 313     CPU_SSSE3    = (1 << 9),
 314     CPU_SSE4A    = (1 << 10),
 315     CPU_SSE4_1   = (1 << 11),
 316     CPU_SSE4_2   = (1 << 12),
 317     CPU_POPCNT   = (1 << 13),
 318     CPU_LZCNT    = (1 << 14),
 319     CPU_TSC      = (1 << 15),
 320     CPU_TSCINV   = (1 << 16),
 321     CPU_AVX      = (1 << 17),
 322     CPU_AVX2     = (1 << 18),
 323     CPU_AES      = (1 << 19),
 324     CPU_ERMS     = (1 << 20), // enhanced 'rep movsb/stosb' instructions
 325     CPU_CLMUL    = (1 << 21), // carryless multiply for CRC
 326     CPU_BMI1     = (1 << 22),
 327     CPU_BMI2     = (1 << 23),
 328     CPU_RTM      = (1 << 24), // Restricted Transactional Memory instructions
 329     CPU_ADX      = (1 << 25),
 330     CPU_AVX512F  = (1 << 26), // AVX 512bit foundation instructions
 331     CPU_AVX512DQ = (1 << 27),
 332     CPU_AVX512PF = (1 << 28),
 333     CPU_AVX512ER = (1 << 29),
 334     CPU_AVX512CD = (1 << 30)
 335     // Keeping sign bit 31 unassigned.
 336   };
 337 
 338 #define CPU_AVX512BW          ((uint64_t)UCONST64(   0x100000000)) // enums are limited to 31 bit
 339 #define CPU_AVX512VL          ((uint64_t)UCONST64(   0x200000000)) // EVEX instructions with smaller vector length
 340 #define CPU_SHA               ((uint64_t)UCONST64(   0x400000000)) // SHA instructions
 341 #define CPU_FMA               ((uint64_t)UCONST64(   0x800000000)) // FMA instructions
 342 #define CPU_VZEROUPPER        ((uint64_t)UCONST64(  0x1000000000)) // Vzeroupper instruction
 343 #define CPU_AVX512_VPOPCNTDQ  ((uint64_t)UCONST64(  0x2000000000)) // Vector popcount
 344 #define CPU_AVX512_VPCLMULQDQ ((uint64_t)UCONST64(  0x4000000000)) // Vector carryless multiplication
 345 #define CPU_AVX512_VAES       ((uint64_t)UCONST64(  0x8000000000)) // Vector AES instructions
 346 #define CPU_AVX512_VNNI       ((uint64_t)UCONST64( 0x10000000000)) // Vector Neural Network Instructions
 347 #define CPU_FLUSH             ((uint64_t)UCONST64( 0x20000000000)) // flush instruction
 348 #define CPU_FLUSHOPT          ((uint64_t)UCONST64( 0x40000000000)) // flushopt instruction
 349 #define CPU_CLWB              ((uint64_t)UCONST64( 0x80000000000)) // clwb instruction
 350 #define CPU_AVX512_VBMI2      ((uint64_t)UCONST64(0x100000000000)) // VBMI2 shift left double instructions
 351 #define CPU_AVX512_VBMI       ((uint64_t)UCONST64(0x200000000000)) // Vector BMI instructions
 352 #define CPU_HV_PRESENT        ((uint64_t)UCONST64(0x400000000000)) // for hypervisor detection
 353 
 354 // NB! When adding new CPU feature detection consider updating vmStructs_x86.hpp, vmStructs_jvmci.hpp, and VM_Version::get_processor_features().
 355 
 356 enum Extended_Family {
 357     // AMD
 358     CPU_FAMILY_AMD_11H       = 0x11,
 359     // ZX
 360     CPU_FAMILY_ZX_CORE_F6    = 6,
 361     CPU_FAMILY_ZX_CORE_F7    = 7,
 362     // Intel
 363     CPU_FAMILY_INTEL_CORE    = 6,
 364     CPU_MODEL_NEHALEM        = 0x1e,
 365     CPU_MODEL_NEHALEM_EP     = 0x1a,
 366     CPU_MODEL_NEHALEM_EX     = 0x2e,
 367     CPU_MODEL_WESTMERE       = 0x25,
 368     CPU_MODEL_WESTMERE_EP    = 0x2c,
 369     CPU_MODEL_WESTMERE_EX    = 0x2f,
 370     CPU_MODEL_SANDYBRIDGE    = 0x2a,
 371     CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
 372     CPU_MODEL_IVYBRIDGE_EP   = 0x3a,
 373     CPU_MODEL_HASWELL_E3     = 0x3c,
 374     CPU_MODEL_HASWELL_E7     = 0x3f,
 375     CPU_MODEL_BROADWELL      = 0x3d,
 376     CPU_MODEL_SKYLAKE        = 0x55
 377   };
 378 
 379   // cpuid information block.  All info derived from executing cpuid with
 380   // various function numbers is stored here.  Intel and AMD info is
 381   // merged in this block: accessor methods disentangle it.
 382   //
 383   // The info block is laid out in subblocks of 4 dwords corresponding to
 384   // eax, ebx, ecx and edx, whether or not they contain anything useful.
 385   struct CpuidInfo {
 386     // cpuid function 0
 387     uint32_t std_max_function;
 388     uint32_t std_vendor_name_0;
 389     uint32_t std_vendor_name_1;
 390     uint32_t std_vendor_name_2;
 391 
 392     // cpuid function 1
 393     StdCpuid1Eax std_cpuid1_eax;
 394     StdCpuid1Ebx std_cpuid1_ebx;
 395     StdCpuid1Ecx std_cpuid1_ecx;
 396     StdCpuid1Edx std_cpuid1_edx;
 397 
 398     // cpuid function 4 (deterministic cache parameters)
 399     DcpCpuid4Eax dcp_cpuid4_eax;
 400     DcpCpuid4Ebx dcp_cpuid4_ebx;
 401     uint32_t     dcp_cpuid4_ecx; // unused currently
 402     uint32_t     dcp_cpuid4_edx; // unused currently
 403 
 404     // cpuid function 7 (structured extended features)
 405     SefCpuid7Eax sef_cpuid7_eax;
 406     SefCpuid7Ebx sef_cpuid7_ebx;
 407     SefCpuid7Ecx sef_cpuid7_ecx;
 408     SefCpuid7Edx sef_cpuid7_edx;
 409 
 410     // cpuid function 0xB (processor topology)
 411     // ecx = 0
 412     uint32_t     tpl_cpuidB0_eax;
 413     TplCpuidBEbx tpl_cpuidB0_ebx;
 414     uint32_t     tpl_cpuidB0_ecx; // unused currently
 415     uint32_t     tpl_cpuidB0_edx; // unused currently
 416 
 417     // ecx = 1
 418     uint32_t     tpl_cpuidB1_eax;
 419     TplCpuidBEbx tpl_cpuidB1_ebx;
 420     uint32_t     tpl_cpuidB1_ecx; // unused currently
 421     uint32_t     tpl_cpuidB1_edx; // unused currently
 422 
 423     // ecx = 2
 424     uint32_t     tpl_cpuidB2_eax;
 425     TplCpuidBEbx tpl_cpuidB2_ebx;
 426     uint32_t     tpl_cpuidB2_ecx; // unused currently
 427     uint32_t     tpl_cpuidB2_edx; // unused currently
 428 
 429     // cpuid function 0x80000000 // example, unused
 430     uint32_t ext_max_function;
 431     uint32_t ext_vendor_name_0;
 432     uint32_t ext_vendor_name_1;
 433     uint32_t ext_vendor_name_2;
 434 
 435     // cpuid function 0x80000001
 436     uint32_t     ext_cpuid1_eax; // reserved
 437     uint32_t     ext_cpuid1_ebx; // reserved
 438     ExtCpuid1Ecx ext_cpuid1_ecx;
 439     ExtCpuid1Edx ext_cpuid1_edx;
 440 
 441     // cpuid functions 0x80000002 thru 0x80000004: example, unused
 442     uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
 443     uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
 444     uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
 445 
 446     // cpuid function 0x80000005 // AMD L1, Intel reserved
 447     uint32_t     ext_cpuid5_eax; // unused currently
 448     uint32_t     ext_cpuid5_ebx; // reserved
 449     ExtCpuid5Ex  ext_cpuid5_ecx; // L1 data cache info (AMD)
 450     ExtCpuid5Ex  ext_cpuid5_edx; // L1 instruction cache info (AMD)
 451 
 452     // cpuid function 0x80000007
 453     uint32_t     ext_cpuid7_eax; // reserved
 454     uint32_t     ext_cpuid7_ebx; // reserved
 455     uint32_t     ext_cpuid7_ecx; // reserved
 456     ExtCpuid7Edx ext_cpuid7_edx; // tscinv
 457 
 458     // cpuid function 0x80000008
 459     uint32_t     ext_cpuid8_eax; // unused currently
 460     uint32_t     ext_cpuid8_ebx; // reserved
 461     ExtCpuid8Ecx ext_cpuid8_ecx;
 462     uint32_t     ext_cpuid8_edx; // reserved
 463 
 464     // cpuid function 0x8000001E // AMD 17h
 465     uint32_t      ext_cpuid1E_eax;
 466     ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)
 467     uint32_t      ext_cpuid1E_ecx;
 468     uint32_t      ext_cpuid1E_edx; // unused currently
 469 
 470     // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
 471     XemXcr0Eax   xem_xcr0_eax;
 472     uint32_t     xem_xcr0_edx; // reserved
 473 
 474     // Space to save ymm registers after signal handle
 475     int          ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
 476 
 477     // Space to save zmm registers after signal handle
 478     int          zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
 479   };
 480 
 481   // The actual cpuid info block
 482   static CpuidInfo _cpuid_info;
 483 
 484   // Extractors and predicates
 485   static uint32_t extended_cpu_family() {
 486     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
 487     result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
 488     return result;
 489   }
 490 
 491   static uint32_t extended_cpu_model() {
 492     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
 493     result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
 494     return result;
 495   }
 496 
 497   static uint32_t cpu_stepping() {
 498     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
 499     return result;
 500   }
 501 
 502   static uint logical_processor_count() {
 503     uint result = threads_per_core();
 504     return result;
 505   }
 506 
 507   static bool compute_has_intel_jcc_erratum();
 508 
 509   static uint64_t feature_flags() {
 510     uint64_t result = 0;
 511     if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
 512       result |= CPU_CX8;
 513     if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
 514       result |= CPU_CMOV;
 515     if (_cpuid_info.std_cpuid1_edx.bits.clflush != 0)
 516       result |= CPU_FLUSH;
 517 #ifdef _LP64
 518     // clflush should always be available on x86_64
 519     // if not we are in real trouble because we rely on it
 520     // to flush the code cache.
 521     assert ((result & CPU_FLUSH) != 0, "clflush should be available");
 522 #endif
 523     if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() &&
 524         _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
 525       result |= CPU_FXSR;
 526     // HT flag is set for multi-core processors also.
 527     if (threads_per_core() > 1)
 528       result |= CPU_HT;
 529     if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() &&
 530         _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
 531       result |= CPU_MMX;
 532     if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
 533       result |= CPU_SSE;
 534     if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
 535       result |= CPU_SSE2;
 536     if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
 537       result |= CPU_SSE3;
 538     if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
 539       result |= CPU_SSSE3;
 540     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
 541       result |= CPU_SSE4_1;
 542     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
 543       result |= CPU_SSE4_2;
 544     if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
 545       result |= CPU_POPCNT;
 546     if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
 547         _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
 548         _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
 549         _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
 550       result |= CPU_AVX;
 551       result |= CPU_VZEROUPPER;
 552       if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
 553         result |= CPU_AVX2;
 554       if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
 555           _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
 556           _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
 557           _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
 558         result |= CPU_AVX512F;
 559         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
 560           result |= CPU_AVX512CD;
 561         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
 562           result |= CPU_AVX512DQ;
 563         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
 564           result |= CPU_AVX512PF;
 565         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
 566           result |= CPU_AVX512ER;
 567         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
 568           result |= CPU_AVX512BW;
 569         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
 570           result |= CPU_AVX512VL;
 571         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0)
 572           result |= CPU_AVX512_VPOPCNTDQ;
 573         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpclmulqdq != 0)
 574           result |= CPU_AVX512_VPCLMULQDQ;
 575         if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0)
 576           result |= CPU_AVX512_VAES;
 577         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0)
 578           result |= CPU_AVX512_VNNI;
 579         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi != 0)
 580           result |= CPU_AVX512_VBMI;
 581         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi2 != 0)
 582           result |= CPU_AVX512_VBMI2;
 583       }
 584     }
 585     if (_cpuid_info.std_cpuid1_ecx.bits.hv != 0)
 586       result |= CPU_HV_PRESENT;
 587     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 588       result |= CPU_BMI1;
 589     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 590       result |= CPU_TSC;
 591     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 592       result |= CPU_TSCINV;
 593     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 594       result |= CPU_AES;
 595     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 596       result |= CPU_ERMS;
 597     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 598       result |= CPU_CLMUL;
 599     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 600       result |= CPU_RTM;
 601     if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 602        result |= CPU_ADX;
 603     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 604       result |= CPU_BMI2;
 605     if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
 606       result |= CPU_SHA;
 607     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
 608       result |= CPU_FMA;
 609     if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
 610       result |= CPU_FLUSHOPT;
 611 
 612     // AMD|Hygon features.
 613     if (is_amd_family()) {
 614       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 615           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 616         result |= CPU_3DNOW_PREFETCH;
 617       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 618         result |= CPU_LZCNT;
 619       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 620         result |= CPU_SSE4A;
 621     }
 622     // Intel features.
 623     if (is_intel()) {
 624       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 625         result |= CPU_LZCNT;
 626       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 627       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 628         result |= CPU_3DNOW_PREFETCH;
 629       }
 630       if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) {
 631         result |= CPU_CLWB;
 632       }
 633     }
 634 
 635     // ZX features.
 636     if (is_zx()) {
 637       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 638         result |= CPU_LZCNT;
 639       // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 640       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 641         result |= CPU_3DNOW_PREFETCH;
 642       }
 643     }
 644 
 645     return result;
 646   }
 647 
 648   static bool os_supports_avx_vectors() {
 649     bool retVal = false;
 650     int nreg = 2 LP64_ONLY(+2);
 651     if (supports_evex()) {
 652       // Verify that OS save/restore all bits of EVEX registers
 653       // during signal processing.
 654       retVal = true;
 655       for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 656         if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 657           retVal = false;
 658           break;
 659         }
 660       }
 661     } else if (supports_avx()) {
 662       // Verify that OS save/restore all bits of AVX registers
 663       // during signal processing.
 664       retVal = true;
 665       for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
 666         if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
 667           retVal = false;
 668           break;
 669         }
 670       }
 671       // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen
 672       if (retVal == false) {
 673         // Verify that OS save/restore all bits of EVEX registers
 674         // during signal processing.
 675         retVal = true;
 676         for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 677           if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 678             retVal = false;
 679             break;
 680           }
 681         }
 682       }
 683     }
 684     return retVal;
 685   }
 686 
 687   static void get_processor_features();
 688 
 689 public:
 690   // Offsets for cpuid asm stub
 691   static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
 692   static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
 693   static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
 694   static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
 695   static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
 696   static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
 697   static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
 698   static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
 699   static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); }
 700   static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
 701   static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
 702   static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
 703   static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
 704   static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
 705   static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
 706 
 707   // The value used to check ymm register after signal handle
 708   static int ymm_test_value()    { return 0xCAFEBABE; }
 709 
 710   static void get_cpu_info_wrapper();
 711   static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
 712   static bool  is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
 713   static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
 714   static address  cpuinfo_cont_addr()           { return _cpuinfo_cont_addr; }
 715 
 716   static void clean_cpuFeatures()   { _features = 0; }
 717   static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); }
 718   static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); }
 719 
 720 
 721   // Initialization
 722   static void initialize();
 723 
 724   // Override Abstract_VM_Version implementation
 725   static void print_platform_virtualization_info(outputStream*);
 726 
 727   // Override Abstract_VM_Version implementation
 728   static bool use_biased_locking();
 729 
 730   // Asserts
 731   static void assert_is_initialized() {
 732     assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
 733   }
 734 
 735   //
 736   // Processor family:
 737   //       3   -  386
 738   //       4   -  486
 739   //       5   -  Pentium
 740   //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
 741   //              Pentium M, Core Solo, Core Duo, Core2 Duo
 742   //    family 6 model:   9,        13,       14,        15
 743   //    0x0f   -  Pentium 4, Opteron
 744   //
 745   // Note: The cpu family should be used to select between
 746   //       instruction sequences which are valid on all Intel
 747   //       processors.  Use the feature test functions below to
 748   //       determine whether a particular instruction is supported.
 749   //
 750   static int  cpu_family()        { return _cpu;}
 751   static bool is_P6()             { return cpu_family() >= 6; }
 752   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
 753   static bool is_hygon()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
 754   static bool is_amd_family()     { return is_amd() || is_hygon(); }
 755   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
 756   static bool is_zx()             { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS  '
 757   static bool is_atom_family()    { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
 758   static bool is_knights_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
 759 
 760   static bool supports_processor_topology() {
 761     return (_cpuid_info.std_max_function >= 0xB) &&
 762            // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
 763            // Some cpus have max cpuid >= 0xB but do not support processor topology.
 764            (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
 765   }
 766 
 767   static uint cores_per_cpu()  {
 768     uint result = 1;
 769     if (is_intel()) {
 770       bool supports_topology = supports_processor_topology();
 771       if (supports_topology) {
 772         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 773                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 774       }
 775       if (!supports_topology || result == 0) {
 776         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 777       }
 778     } else if (is_amd_family()) {
 779       result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
 780     } else if (is_zx()) {
 781       bool supports_topology = supports_processor_topology();
 782       if (supports_topology) {
 783         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 784                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 785       }
 786       if (!supports_topology || result == 0) {
 787         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 788       }
 789     }
 790     return result;
 791   }
 792 
 793   static uint threads_per_core()  {
 794     uint result = 1;
 795     if (is_intel() && supports_processor_topology()) {
 796       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 797     } else if (is_zx() && supports_processor_topology()) {
 798       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 799     } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
 800       if (cpu_family() >= 0x17) {
 801         result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1;
 802       } else {
 803         result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
 804                  cores_per_cpu();
 805       }
 806     }
 807     return (result == 0 ? 1 : result);
 808   }
 809 
 810   static intx L1_line_size()  {
 811     intx result = 0;
 812     if (is_intel()) {
 813       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 814     } else if (is_amd_family()) {
 815       result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
 816     } else if (is_zx()) {
 817       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 818     }
 819     if (result < 32) // not defined ?
 820       result = 32;   // 32 bytes by default on x86 and other x64
 821     return result;
 822   }
 823 
 824   static intx prefetch_data_size()  {
 825     return L1_line_size();
 826   }
 827 
 828   //
 829   // Feature identification
 830   //
 831   static bool supports_cpuid()    { return _features  != 0; }
 832   static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
 833   static bool supports_cmov()     { return (_features & CPU_CMOV) != 0; }
 834   static bool supports_fxsr()     { return (_features & CPU_FXSR) != 0; }
 835   static bool supports_ht()       { return (_features & CPU_HT) != 0; }
 836   static bool supports_mmx()      { return (_features & CPU_MMX) != 0; }
 837   static bool supports_sse()      { return (_features & CPU_SSE) != 0; }
 838   static bool supports_sse2()     { return (_features & CPU_SSE2) != 0; }
 839   static bool supports_sse3()     { return (_features & CPU_SSE3) != 0; }
 840   static bool supports_ssse3()    { return (_features & CPU_SSSE3)!= 0; }
 841   static bool supports_sse4_1()   { return (_features & CPU_SSE4_1) != 0; }
 842   static bool supports_sse4_2()   { return (_features & CPU_SSE4_2) != 0; }
 843   static bool supports_popcnt()   { return (_features & CPU_POPCNT) != 0; }
 844   static bool supports_avx()      { return (_features & CPU_AVX) != 0; }
 845   static bool supports_avx2()     { return (_features & CPU_AVX2) != 0; }
 846   static bool supports_tsc()      { return (_features & CPU_TSC)    != 0; }
 847   static bool supports_aes()      { return (_features & CPU_AES) != 0; }
 848   static bool supports_erms()     { return (_features & CPU_ERMS) != 0; }
 849   static bool supports_clmul()    { return (_features & CPU_CLMUL) != 0; }
 850   static bool supports_rtm()      { return (_features & CPU_RTM) != 0; }
 851   static bool supports_bmi1()     { return (_features & CPU_BMI1) != 0; }
 852   static bool supports_bmi2()     { return (_features & CPU_BMI2) != 0; }
 853   static bool supports_adx()      { return (_features & CPU_ADX) != 0; }
 854   static bool supports_evex()     { return (_features & CPU_AVX512F) != 0; }
 855   static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
 856   static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
 857   static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
 858   static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
 859   static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
 860   static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
 861   static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
 862   static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
 863   static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
 864                                                 supports_avx512bw() && supports_avx512dq()); }
 865   static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
 866   static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
 867   static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
 868   static bool supports_avxonly()    { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
 869   static bool supports_sha()        { return (_features & CPU_SHA) != 0; }
 870   static bool supports_fma()        { return (_features & CPU_FMA) != 0 && supports_avx(); }
 871   static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; }
 872   static bool supports_avx512_vpopcntdq()  { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; }
 873   static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; }
 874   static bool supports_avx512_vaes()       { return (_features & CPU_AVX512_VAES) != 0; }
 875   static bool supports_avx512_vnni()       { return (_features & CPU_AVX512_VNNI) != 0; }
 876   static bool supports_avx512_vbmi()       { return (_features & CPU_AVX512_VBMI) != 0; }
 877   static bool supports_avx512_vbmi2()      { return (_features & CPU_AVX512_VBMI2) != 0; }
 878   static bool supports_hv()                { return (_features & CPU_HV_PRESENT) != 0; }
 879 
 880   // Intel features
 881   static bool is_intel_family_core() { return is_intel() &&
 882                                        extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
 883 
 884   static bool is_intel_skylake() { return is_intel_family_core() &&
 885                                           extended_cpu_model() == CPU_MODEL_SKYLAKE; }
 886 
 887   static bool is_intel_tsc_synched_at_init()  {
 888     if (is_intel_family_core()) {
 889       uint32_t ext_model = extended_cpu_model();
 890       if (ext_model == CPU_MODEL_NEHALEM_EP     ||
 891           ext_model == CPU_MODEL_WESTMERE_EP    ||
 892           ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
 893           ext_model == CPU_MODEL_IVYBRIDGE_EP) {
 894         // <= 2-socket invariant tsc support. EX versions are usually used
 895         // in > 2-socket systems and likely don't synchronize tscs at
 896         // initialization.
 897         // Code that uses tsc values must be prepared for them to arbitrarily
 898         // jump forward or backward.
 899         return true;
 900       }
 901     }
 902     return false;
 903   }
 904 
 905   // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
 906   // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
 907   // mitigation causes regressions when jumps or fused conditional branches cross or end at
 908   // 32 byte boundaries.
 909   static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
 910 
 911   // AMD features
 912   static bool supports_3dnow_prefetch()    { return (_features & CPU_3DNOW_PREFETCH) != 0; }
 913   static bool supports_lzcnt()    { return (_features & CPU_LZCNT) != 0; }
 914   static bool supports_sse4a()    { return (_features & CPU_SSE4A) != 0; }
 915 
 916   static bool is_amd_Barcelona()  { return is_amd() &&
 917                                            extended_cpu_family() == CPU_FAMILY_AMD_11H; }
 918 
 919   // Intel and AMD newer cores support fast timestamps well
 920   static bool supports_tscinv_bit() {
 921     return (_features & CPU_TSCINV) != 0;
 922   }
 923   static bool supports_tscinv() {
 924     return supports_tscinv_bit() &&
 925       ((is_amd_family() && !is_amd_Barcelona()) ||
 926         is_intel_tsc_synched_at_init());
 927   }
 928 
 929   // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
 930   static bool has_fast_idiv()     { return is_intel() && cpu_family() == 6 &&
 931                                            supports_sse3() && _model != 0x1C; }
 932 
 933   static bool supports_compare_and_exchange() { return true; }
 934 
 935   static intx allocate_prefetch_distance(bool use_watermark_prefetch) {
 936     // Hardware prefetching (distance/size in bytes):
 937     // Pentium 3 -  64 /  32
 938     // Pentium 4 - 256 / 128
 939     // Athlon    -  64 /  32 ????
 940     // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
 941     // Core      - 128 /  64
 942     //
 943     // Software prefetching (distance in bytes / instruction with best score):
 944     // Pentium 3 - 128 / prefetchnta
 945     // Pentium 4 - 512 / prefetchnta
 946     // Athlon    - 128 / prefetchnta
 947     // Opteron   - 256 / prefetchnta
 948     // Core      - 256 / prefetchnta
 949     // It will be used only when AllocatePrefetchStyle > 0
 950 
 951     if (is_amd_family()) { // AMD | Hygon
 952       if (supports_sse2()) {
 953         return 256; // Opteron
 954       } else {
 955         return 128; // Athlon
 956       }
 957     } else { // Intel
 958       if (supports_sse3() && cpu_family() == 6) {
 959         if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
 960           return 192;
 961         } else if (use_watermark_prefetch) { // watermark prefetching on Core
 962 #ifdef _LP64
 963           return 384;
 964 #else
 965           return 320;
 966 #endif
 967         }
 968       }
 969       if (supports_sse2()) {
 970         if (cpu_family() == 6) {
 971           return 256; // Pentium M, Core, Core2
 972         } else {
 973           return 512; // Pentium 4
 974         }
 975       } else {
 976         return 128; // Pentium 3 (and all other old CPUs)
 977       }
 978     }
 979   }
 980 
 981   // SSE2 and later processors implement a 'pause' instruction
 982   // that can be used for efficient implementation of
 983   // the intrinsic for java.lang.Thread.onSpinWait()
 984   static bool supports_on_spin_wait() { return supports_sse2(); }
 985 
 986   // x86_64 supports fast class initialization checks for static methods.
 987   static bool supports_fast_class_init_checks() {
 988     return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
 989   }
 990 
 991   // there are several insns to force cache line sync to memory which
 992   // we can use to ensure mapped non-volatile memory is up to date with
 993   // pending in-cache changes.
 994   //
 995   // 64 bit cpus always support clflush which writes back and evicts
 996   // on 32 bit cpus support is recorded via a feature flag
 997   //
 998   // clflushopt is optional and acts like clflush except it does
 999   // not synchronize with other memory ops. it needs a preceding
1000   // and trailing StoreStore fence
1001   //
1002   // clwb is an optional, intel-specific instruction optional which
1003   // writes back without evicting the line. it also does not
1004   // synchronize with other memory ops. so, it also needs a preceding
1005   // and trailing StoreStore fence.
1006 
1007 #ifdef _LP64
1008   static bool supports_clflush() {
1009     // clflush should always be available on x86_64
1010     // if not we are in real trouble because we rely on it
1011     // to flush the code cache.
1012     // Unfortunately, Assembler::clflush is currently called as part
1013     // of generation of the code cache flush routine. This happens
1014     // under Universe::init before the processor features are set
1015     // up. Assembler::flush calls this routine to check that clflush
1016     // is allowed. So, we give the caller a free pass if Universe init
1017     // is still in progress.
1018     assert ((!Universe::is_fully_initialized() || (_features & CPU_FLUSH) != 0), "clflush should be available");
1019     return true;
1020   }
1021   static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); }
1022   static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); }
1023 #else
1024   static bool supports_clflush() { return  ((_features & CPU_FLUSH) != 0); }
1025   static bool supports_clflushopt() { return false; }
1026   static bool supports_clwb() { return false; }
1027 #endif // _LP64
1028 
1029   // support functions for virtualization detection
1030  private:
1031   static void check_virt_cpuid(uint32_t *regs);
1032   static void check_virtualizations();
1033 
1034 #ifdef _WINDOWS
1035   static bool is_in_VM();
1036 #endif
1037 
1038 };
1039 
1040 #endif // CPU_X86_VM_VERSION_X86_HPP