1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VERSION_X86_HPP
27
28 #include "memory/universe.hpp"
29 #include "runtime/abstract_vm_version.hpp"
30 #include "runtime/globals_extension.hpp"
31
32 class VM_Version : public Abstract_VM_Version {
33 friend class VMStructs;
34 friend class JVMCIVMStructs;
35
36 public:
37 // cpuid result register layouts. These are all unions of a uint32_t
38 // (in case anyone wants access to the register as a whole) and a bitfield.
39
40 union StdCpuid1Eax {
41 uint32_t value;
42 struct {
43 uint32_t stepping : 4,
44 model : 4,
45 family : 4,
46 proc_type : 2,
47 : 2,
48 ext_model : 4,
49 ext_family : 8,
50 : 4;
51 } bits;
52 };
53
54 union StdCpuid1Ebx { // example, unused
55 uint32_t value;
56 struct {
57 uint32_t brand_id : 8,
58 clflush_size : 8,
59 threads_per_cpu : 8,
60 apic_id : 8;
61 } bits;
62 };
63
64 union StdCpuid1Ecx {
65 uint32_t value;
66 struct {
67 uint32_t sse3 : 1,
68 clmul : 1,
69 : 1,
70 monitor : 1,
71 : 1,
72 vmx : 1,
73 : 1,
74 est : 1,
75 : 1,
76 ssse3 : 1,
77 cid : 1,
78 : 1,
79 fma : 1,
80 cmpxchg16: 1,
81 : 4,
82 dca : 1,
83 sse4_1 : 1,
84 sse4_2 : 1,
85 : 2,
86 popcnt : 1,
87 : 1,
88 aes : 1,
89 : 1,
90 osxsave : 1,
91 avx : 1,
92 : 3;
93 } bits;
94 };
95
96 union StdCpuid1Edx {
97 uint32_t value;
98 struct {
99 uint32_t : 4,
100 tsc : 1,
101 : 3,
102 cmpxchg8 : 1,
103 : 6,
104 cmov : 1,
105 : 3,
106 clflush : 1,
107 : 3,
108 mmx : 1,
109 fxsr : 1,
110 sse : 1,
111 sse2 : 1,
112 : 1,
113 ht : 1,
114 : 3;
115 } bits;
116 };
117
118 union DcpCpuid4Eax {
119 uint32_t value;
120 struct {
121 uint32_t cache_type : 5,
122 : 21,
123 cores_per_cpu : 6;
124 } bits;
125 };
126
127 union DcpCpuid4Ebx {
128 uint32_t value;
129 struct {
130 uint32_t L1_line_size : 12,
131 partitions : 10,
132 associativity : 10;
133 } bits;
134 };
135
136 union TplCpuidBEbx {
137 uint32_t value;
138 struct {
139 uint32_t logical_cpus : 16,
140 : 16;
141 } bits;
142 };
143
144 union ExtCpuid1Ecx {
145 uint32_t value;
146 struct {
147 uint32_t LahfSahf : 1,
148 CmpLegacy : 1,
149 : 3,
150 lzcnt_intel : 1,
151 lzcnt : 1,
152 sse4a : 1,
153 misalignsse : 1,
154 prefetchw : 1,
155 : 22;
156 } bits;
157 };
158
159 union ExtCpuid1Edx {
160 uint32_t value;
161 struct {
162 uint32_t : 22,
163 mmx_amd : 1,
164 mmx : 1,
165 fxsr : 1,
166 : 4,
167 long_mode : 1,
168 tdnow2 : 1,
169 tdnow : 1;
170 } bits;
171 };
172
173 union ExtCpuid5Ex {
174 uint32_t value;
175 struct {
176 uint32_t L1_line_size : 8,
177 L1_tag_lines : 8,
178 L1_assoc : 8,
179 L1_size : 8;
180 } bits;
181 };
182
183 union ExtCpuid7Edx {
184 uint32_t value;
185 struct {
186 uint32_t : 8,
187 tsc_invariance : 1,
188 : 23;
189 } bits;
190 };
191
192 union ExtCpuid8Ecx {
193 uint32_t value;
194 struct {
195 uint32_t cores_per_cpu : 8,
196 : 24;
197 } bits;
198 };
199
200 union SefCpuid7Eax {
201 uint32_t value;
202 };
203
204 union SefCpuid7Ebx {
205 uint32_t value;
206 struct {
207 uint32_t fsgsbase : 1,
208 : 2,
209 bmi1 : 1,
210 : 1,
211 avx2 : 1,
212 : 2,
213 bmi2 : 1,
214 erms : 1,
215 : 1,
216 rtm : 1,
217 : 4,
218 avx512f : 1,
219 avx512dq : 1,
220 : 1,
221 adx : 1,
222 : 3,
223 clflushopt : 1,
224 clwb : 1,
225 : 1,
226 avx512pf : 1,
227 avx512er : 1,
228 avx512cd : 1,
229 sha : 1,
230 avx512bw : 1,
231 avx512vl : 1;
232 } bits;
233 };
234
235 union SefCpuid7Ecx {
236 uint32_t value;
237 struct {
238 uint32_t prefetchwt1 : 1,
239 avx512_vbmi : 1,
240 umip : 1,
241 pku : 1,
242 ospke : 1,
243 : 1,
244 avx512_vbmi2 : 1,
245 : 1,
246 gfni : 1,
247 vaes : 1,
248 avx512_vpclmulqdq : 1,
249 avx512_vnni : 1,
250 avx512_bitalg : 1,
251 : 1,
252 avx512_vpopcntdq : 1,
253 : 17;
254 } bits;
255 };
256
257 union SefCpuid7Edx {
258 uint32_t value;
259 struct {
260 uint32_t : 2,
261 avx512_4vnniw : 1,
262 avx512_4fmaps : 1,
263 : 28;
264 } bits;
265 };
266
267 union ExtCpuid1EEbx {
268 uint32_t value;
269 struct {
270 uint32_t : 8,
271 threads_per_core : 8,
272 : 16;
273 } bits;
274 };
275
276 union XemXcr0Eax {
277 uint32_t value;
278 struct {
279 uint32_t x87 : 1,
280 sse : 1,
281 ymm : 1,
282 bndregs : 1,
283 bndcsr : 1,
284 opmask : 1,
285 zmm512 : 1,
286 zmm32 : 1,
287 : 24;
288 } bits;
289 };
290
291 protected:
292 static int _cpu;
293 static int _model;
294 static int _stepping;
295
296 static bool _has_intel_jcc_erratum;
297
298 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
299 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
300
301 enum Feature_Flag {
302 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
303 CPU_CMOV = (1 << 1),
304 CPU_FXSR = (1 << 2),
305 CPU_HT = (1 << 3),
306 CPU_MMX = (1 << 4),
307 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
308 // may not necessarily support other 3dnow instructions
309 CPU_SSE = (1 << 6),
310 CPU_SSE2 = (1 << 7),
311 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
312 CPU_SSSE3 = (1 << 9),
313 CPU_SSE4A = (1 << 10),
314 CPU_SSE4_1 = (1 << 11),
315 CPU_SSE4_2 = (1 << 12),
316 CPU_POPCNT = (1 << 13),
317 CPU_LZCNT = (1 << 14),
318 CPU_TSC = (1 << 15),
319 CPU_TSCINV = (1 << 16),
320 CPU_AVX = (1 << 17),
321 CPU_AVX2 = (1 << 18),
322 CPU_AES = (1 << 19),
323 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
324 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
325 CPU_BMI1 = (1 << 22),
326 CPU_BMI2 = (1 << 23),
327 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
328 CPU_ADX = (1 << 25),
329 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
330 CPU_AVX512DQ = (1 << 27),
331 CPU_AVX512PF = (1 << 28),
332 CPU_AVX512ER = (1 << 29),
333 CPU_AVX512CD = (1 << 30)
334 // Keeping sign bit 31 unassigned.
335 };
336
337 #define CPU_AVX512BW ((uint64_t)UCONST64( 0x100000000)) // enums are limited to 31 bit
338 #define CPU_AVX512VL ((uint64_t)UCONST64( 0x200000000)) // EVEX instructions with smaller vector length
339 #define CPU_SHA ((uint64_t)UCONST64( 0x400000000)) // SHA instructions
340 #define CPU_FMA ((uint64_t)UCONST64( 0x800000000)) // FMA instructions
341 #define CPU_VZEROUPPER ((uint64_t)UCONST64( 0x1000000000)) // Vzeroupper instruction
342 #define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64( 0x2000000000)) // Vector popcount
343 #define CPU_AVX512_VPCLMULQDQ ((uint64_t)UCONST64( 0x4000000000)) // Vector carryless multiplication
344 #define CPU_AVX512_VAES ((uint64_t)UCONST64( 0x8000000000)) // Vector AES instructions
345 #define CPU_AVX512_VNNI ((uint64_t)UCONST64( 0x10000000000)) // Vector Neural Network Instructions
346 #define CPU_FLUSH ((uint64_t)UCONST64( 0x20000000000)) // flush instruction
347 #define CPU_FLUSHOPT ((uint64_t)UCONST64( 0x40000000000)) // flushopt instruction
348 #define CPU_CLWB ((uint64_t)UCONST64( 0x80000000000)) // clwb instruction
349 #define CPU_AVX512_VBMI2 ((uint64_t)UCONST64(0x100000000000)) // VBMI2 shift left double instructions
350 #define CPU_AVX512_VBMI ((uint64_t)UCONST64(0x200000000000)) // Vector BMI instructions
351
352 // NB! When adding new CPU feature detection consider updating vmStructs_x86.hpp, vmStructs_jvmci.hpp, and VM_Version::get_processor_features().
353
354 enum Extended_Family {
355 // AMD
356 CPU_FAMILY_AMD_11H = 0x11,
357 // ZX
358 CPU_FAMILY_ZX_CORE_F6 = 6,
359 CPU_FAMILY_ZX_CORE_F7 = 7,
360 // Intel
361 CPU_FAMILY_INTEL_CORE = 6,
362 CPU_MODEL_NEHALEM = 0x1e,
363 CPU_MODEL_NEHALEM_EP = 0x1a,
364 CPU_MODEL_NEHALEM_EX = 0x2e,
365 CPU_MODEL_WESTMERE = 0x25,
366 CPU_MODEL_WESTMERE_EP = 0x2c,
367 CPU_MODEL_WESTMERE_EX = 0x2f,
368 CPU_MODEL_SANDYBRIDGE = 0x2a,
369 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
370 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
371 CPU_MODEL_HASWELL_E3 = 0x3c,
372 CPU_MODEL_HASWELL_E7 = 0x3f,
373 CPU_MODEL_BROADWELL = 0x3d,
374 CPU_MODEL_SKYLAKE = 0x55
375 };
376
377 // cpuid information block. All info derived from executing cpuid with
378 // various function numbers is stored here. Intel and AMD info is
379 // merged in this block: accessor methods disentangle it.
380 //
381 // The info block is laid out in subblocks of 4 dwords corresponding to
382 // eax, ebx, ecx and edx, whether or not they contain anything useful.
383 struct CpuidInfo {
384 // cpuid function 0
385 uint32_t std_max_function;
386 uint32_t std_vendor_name_0;
387 uint32_t std_vendor_name_1;
388 uint32_t std_vendor_name_2;
389
390 // cpuid function 1
391 StdCpuid1Eax std_cpuid1_eax;
392 StdCpuid1Ebx std_cpuid1_ebx;
393 StdCpuid1Ecx std_cpuid1_ecx;
394 StdCpuid1Edx std_cpuid1_edx;
395
396 // cpuid function 4 (deterministic cache parameters)
397 DcpCpuid4Eax dcp_cpuid4_eax;
398 DcpCpuid4Ebx dcp_cpuid4_ebx;
399 uint32_t dcp_cpuid4_ecx; // unused currently
400 uint32_t dcp_cpuid4_edx; // unused currently
401
402 // cpuid function 7 (structured extended features)
403 SefCpuid7Eax sef_cpuid7_eax;
404 SefCpuid7Ebx sef_cpuid7_ebx;
405 SefCpuid7Ecx sef_cpuid7_ecx;
406 SefCpuid7Edx sef_cpuid7_edx;
407
408 // cpuid function 0xB (processor topology)
409 // ecx = 0
410 uint32_t tpl_cpuidB0_eax;
411 TplCpuidBEbx tpl_cpuidB0_ebx;
412 uint32_t tpl_cpuidB0_ecx; // unused currently
413 uint32_t tpl_cpuidB0_edx; // unused currently
414
415 // ecx = 1
416 uint32_t tpl_cpuidB1_eax;
417 TplCpuidBEbx tpl_cpuidB1_ebx;
418 uint32_t tpl_cpuidB1_ecx; // unused currently
419 uint32_t tpl_cpuidB1_edx; // unused currently
420
421 // ecx = 2
422 uint32_t tpl_cpuidB2_eax;
423 TplCpuidBEbx tpl_cpuidB2_ebx;
424 uint32_t tpl_cpuidB2_ecx; // unused currently
425 uint32_t tpl_cpuidB2_edx; // unused currently
426
427 // cpuid function 0x80000000 // example, unused
428 uint32_t ext_max_function;
429 uint32_t ext_vendor_name_0;
430 uint32_t ext_vendor_name_1;
431 uint32_t ext_vendor_name_2;
432
433 // cpuid function 0x80000001
434 uint32_t ext_cpuid1_eax; // reserved
435 uint32_t ext_cpuid1_ebx; // reserved
436 ExtCpuid1Ecx ext_cpuid1_ecx;
437 ExtCpuid1Edx ext_cpuid1_edx;
438
439 // cpuid functions 0x80000002 thru 0x80000004: example, unused
440 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
441 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
442 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
443
444 // cpuid function 0x80000005 // AMD L1, Intel reserved
445 uint32_t ext_cpuid5_eax; // unused currently
446 uint32_t ext_cpuid5_ebx; // reserved
447 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
448 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
449
450 // cpuid function 0x80000007
451 uint32_t ext_cpuid7_eax; // reserved
452 uint32_t ext_cpuid7_ebx; // reserved
453 uint32_t ext_cpuid7_ecx; // reserved
454 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
455
456 // cpuid function 0x80000008
457 uint32_t ext_cpuid8_eax; // unused currently
458 uint32_t ext_cpuid8_ebx; // reserved
459 ExtCpuid8Ecx ext_cpuid8_ecx;
460 uint32_t ext_cpuid8_edx; // reserved
461
462 // cpuid function 0x8000001E // AMD 17h
463 uint32_t ext_cpuid1E_eax;
464 ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)
465 uint32_t ext_cpuid1E_ecx;
466 uint32_t ext_cpuid1E_edx; // unused currently
467
468 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
469 XemXcr0Eax xem_xcr0_eax;
470 uint32_t xem_xcr0_edx; // reserved
471
472 // Space to save ymm registers after signal handle
473 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
474
475 // Space to save zmm registers after signal handle
476 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
477 };
478
479 // The actual cpuid info block
480 static CpuidInfo _cpuid_info;
481
482 // Extractors and predicates
483 static uint32_t extended_cpu_family() {
484 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
485 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
486 return result;
487 }
488
489 static uint32_t extended_cpu_model() {
490 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
491 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
492 return result;
493 }
494
495 static uint32_t cpu_stepping() {
496 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
497 return result;
498 }
499
500 static uint logical_processor_count() {
501 uint result = threads_per_core();
502 return result;
503 }
504
505 static bool compute_has_intel_jcc_erratum();
506
507 static uint64_t feature_flags() {
508 uint64_t result = 0;
509 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
510 result |= CPU_CX8;
511 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
512 result |= CPU_CMOV;
513 if (_cpuid_info.std_cpuid1_edx.bits.clflush != 0)
514 result |= CPU_FLUSH;
515 #ifdef _LP64
516 // clflush should always be available on x86_64
517 // if not we are in real trouble because we rely on it
518 // to flush the code cache.
519 assert ((result & CPU_FLUSH) != 0, "clflush should be available");
520 #endif
521 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() &&
522 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
523 result |= CPU_FXSR;
524 // HT flag is set for multi-core processors also.
525 if (threads_per_core() > 1)
526 result |= CPU_HT;
527 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() &&
528 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
529 result |= CPU_MMX;
530 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
531 result |= CPU_SSE;
532 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
533 result |= CPU_SSE2;
534 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
535 result |= CPU_SSE3;
536 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
537 result |= CPU_SSSE3;
538 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
539 result |= CPU_SSE4_1;
540 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
541 result |= CPU_SSE4_2;
542 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
543 result |= CPU_POPCNT;
544 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
545 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
546 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
547 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
548 result |= CPU_AVX;
549 result |= CPU_VZEROUPPER;
550 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
551 result |= CPU_AVX2;
552 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
553 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
554 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
555 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
556 result |= CPU_AVX512F;
557 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
558 result |= CPU_AVX512CD;
559 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
560 result |= CPU_AVX512DQ;
561 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
562 result |= CPU_AVX512PF;
563 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
564 result |= CPU_AVX512ER;
565 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
566 result |= CPU_AVX512BW;
567 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
568 result |= CPU_AVX512VL;
569 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0)
570 result |= CPU_AVX512_VPOPCNTDQ;
571 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpclmulqdq != 0)
572 result |= CPU_AVX512_VPCLMULQDQ;
573 if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0)
574 result |= CPU_AVX512_VAES;
575 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0)
576 result |= CPU_AVX512_VNNI;
577 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi != 0)
578 result |= CPU_AVX512_VBMI;
579 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi2 != 0)
580 result |= CPU_AVX512_VBMI2;
581 }
582 }
583 if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
584 result |= CPU_BMI1;
585 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
586 result |= CPU_TSC;
587 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
588 result |= CPU_TSCINV;
589 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
590 result |= CPU_AES;
591 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
592 result |= CPU_ERMS;
593 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
594 result |= CPU_CLMUL;
595 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
596 result |= CPU_RTM;
597 if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
598 result |= CPU_ADX;
599 if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
600 result |= CPU_BMI2;
601 if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
602 result |= CPU_SHA;
603 if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
604 result |= CPU_FMA;
605 if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
606 result |= CPU_FLUSHOPT;
607
608 // AMD|Hygon features.
609 if (is_amd_family()) {
610 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
611 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
612 result |= CPU_3DNOW_PREFETCH;
613 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
614 result |= CPU_LZCNT;
615 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
616 result |= CPU_SSE4A;
617 }
618 // Intel features.
619 if (is_intel()) {
620 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
621 result |= CPU_LZCNT;
622 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
623 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
624 result |= CPU_3DNOW_PREFETCH;
625 }
626 if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) {
627 result |= CPU_CLWB;
628 }
629 }
630
631 // ZX features.
632 if (is_zx()) {
633 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
634 result |= CPU_LZCNT;
635 // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
636 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
637 result |= CPU_3DNOW_PREFETCH;
638 }
639 }
640
641 return result;
642 }
643
644 static bool os_supports_avx_vectors() {
645 bool retVal = false;
646 int nreg = 2 LP64_ONLY(+2);
647 if (supports_evex()) {
648 // Verify that OS save/restore all bits of EVEX registers
649 // during signal processing.
650 retVal = true;
651 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
652 if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
653 retVal = false;
654 break;
655 }
656 }
657 } else if (supports_avx()) {
658 // Verify that OS save/restore all bits of AVX registers
659 // during signal processing.
660 retVal = true;
661 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
662 if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
663 retVal = false;
664 break;
665 }
666 }
667 // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen
668 if (retVal == false) {
669 // Verify that OS save/restore all bits of EVEX registers
670 // during signal processing.
671 retVal = true;
672 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
673 if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
674 retVal = false;
675 break;
676 }
677 }
678 }
679 }
680 return retVal;
681 }
682
683 static void get_processor_features();
684
685 public:
686 // Offsets for cpuid asm stub
687 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
688 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
689 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
690 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
691 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
692 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
693 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
694 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
695 static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); }
696 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
697 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
698 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
699 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
700 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
701 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
702
703 // The value used to check ymm register after signal handle
704 static int ymm_test_value() { return 0xCAFEBABE; }
705
706 static void get_cpu_info_wrapper();
707 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
708 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
709 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
710 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
711
712 static void clean_cpuFeatures() { _features = 0; }
713 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); }
714 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); }
715
716
717 // Initialization
718 static void initialize();
719
720 // Override Abstract_VM_Version implementation
721 static void print_platform_virtualization_info(outputStream*);
722
723 // Override Abstract_VM_Version implementation
724 static bool use_biased_locking();
725
726 // Asserts
727 static void assert_is_initialized() {
728 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
729 }
730
731 //
732 // Processor family:
733 // 3 - 386
734 // 4 - 486
735 // 5 - Pentium
736 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
737 // Pentium M, Core Solo, Core Duo, Core2 Duo
738 // family 6 model: 9, 13, 14, 15
739 // 0x0f - Pentium 4, Opteron
740 //
741 // Note: The cpu family should be used to select between
742 // instruction sequences which are valid on all Intel
743 // processors. Use the feature test functions below to
744 // determine whether a particular instruction is supported.
745 //
746 static int cpu_family() { return _cpu;}
747 static bool is_P6() { return cpu_family() >= 6; }
748 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
749 static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
750 static bool is_amd_family() { return is_amd() || is_hygon(); }
751 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
752 static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
753 static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
754 static bool is_knights_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
755
756 static bool supports_processor_topology() {
757 return (_cpuid_info.std_max_function >= 0xB) &&
758 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
759 // Some cpus have max cpuid >= 0xB but do not support processor topology.
760 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
761 }
762
763 static uint cores_per_cpu() {
764 uint result = 1;
765 if (is_intel()) {
766 bool supports_topology = supports_processor_topology();
767 if (supports_topology) {
768 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
769 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
770 }
771 if (!supports_topology || result == 0) {
772 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
773 }
774 } else if (is_amd_family()) {
775 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
776 } else if (is_zx()) {
777 bool supports_topology = supports_processor_topology();
778 if (supports_topology) {
779 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
780 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
781 }
782 if (!supports_topology || result == 0) {
783 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
784 }
785 }
786 return result;
787 }
788
789 static uint threads_per_core() {
790 uint result = 1;
791 if (is_intel() && supports_processor_topology()) {
792 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
793 } else if (is_zx() && supports_processor_topology()) {
794 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
795 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
796 if (cpu_family() >= 0x17) {
797 result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1;
798 } else {
799 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
800 cores_per_cpu();
801 }
802 }
803 return (result == 0 ? 1 : result);
804 }
805
806 static intx L1_line_size() {
807 intx result = 0;
808 if (is_intel()) {
809 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
810 } else if (is_amd_family()) {
811 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
812 } else if (is_zx()) {
813 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
814 }
815 if (result < 32) // not defined ?
816 result = 32; // 32 bytes by default on x86 and other x64
817 return result;
818 }
819
820 static intx prefetch_data_size() {
821 return L1_line_size();
822 }
823
824 //
825 // Feature identification
826 //
827 static bool supports_cpuid() { return _features != 0; }
828 static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
829 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; }
830 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; }
831 static bool supports_ht() { return (_features & CPU_HT) != 0; }
832 static bool supports_mmx() { return (_features & CPU_MMX) != 0; }
833 static bool supports_sse() { return (_features & CPU_SSE) != 0; }
834 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; }
835 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; }
836 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; }
837 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; }
838 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; }
839 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; }
840 static bool supports_avx() { return (_features & CPU_AVX) != 0; }
841 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; }
842 static bool supports_tsc() { return (_features & CPU_TSC) != 0; }
843 static bool supports_aes() { return (_features & CPU_AES) != 0; }
844 static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
845 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
846 static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
847 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
848 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
849 static bool supports_adx() { return (_features & CPU_ADX) != 0; }
850 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
851 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
852 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
853 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
854 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
855 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
856 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
857 static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
858 static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
859 static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
860 supports_avx512bw() && supports_avx512dq()); }
861 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
862 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
863 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
864 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
865 static bool supports_sha() { return (_features & CPU_SHA) != 0; }
866 static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); }
867 static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; }
868 static bool supports_avx512_vpopcntdq() { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; }
869 static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; }
870 static bool supports_avx512_vaes() { return (_features & CPU_AVX512_VAES) != 0; }
871 static bool supports_avx512_vnni() { return (_features & CPU_AVX512_VNNI) != 0; }
872 static bool supports_avx512_vbmi() { return (_features & CPU_AVX512_VBMI) != 0; }
873 static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; }
874
875 // Intel features
876 static bool is_intel_family_core() { return is_intel() &&
877 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
878
879 static bool is_intel_skylake() { return is_intel_family_core() &&
880 extended_cpu_model() == CPU_MODEL_SKYLAKE; }
881
882 static bool is_intel_tsc_synched_at_init() {
883 if (is_intel_family_core()) {
884 uint32_t ext_model = extended_cpu_model();
885 if (ext_model == CPU_MODEL_NEHALEM_EP ||
886 ext_model == CPU_MODEL_WESTMERE_EP ||
887 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
888 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
889 // <= 2-socket invariant tsc support. EX versions are usually used
890 // in > 2-socket systems and likely don't synchronize tscs at
891 // initialization.
892 // Code that uses tsc values must be prepared for them to arbitrarily
893 // jump forward or backward.
894 return true;
895 }
896 }
897 return false;
898 }
899
900 // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
901 // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
902 // mitigation causes regressions when jumps or fused conditional branches cross or end at
903 // 32 byte boundaries.
904 static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
905
906 // AMD features
907 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; }
908 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; }
909 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; }
910
911 static bool is_amd_Barcelona() { return is_amd() &&
912 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
913
914 // Intel and AMD newer cores support fast timestamps well
915 static bool supports_tscinv_bit() {
916 return (_features & CPU_TSCINV) != 0;
917 }
918 static bool supports_tscinv() {
919 return supports_tscinv_bit() &&
920 ((is_amd_family() && !is_amd_Barcelona()) ||
921 is_intel_tsc_synched_at_init());
922 }
923
924 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
925 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
926 supports_sse3() && _model != 0x1C; }
927
928 static bool supports_compare_and_exchange() { return true; }
929
930 static intx allocate_prefetch_distance(bool use_watermark_prefetch) {
931 // Hardware prefetching (distance/size in bytes):
932 // Pentium 3 - 64 / 32
933 // Pentium 4 - 256 / 128
934 // Athlon - 64 / 32 ????
935 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
936 // Core - 128 / 64
937 //
938 // Software prefetching (distance in bytes / instruction with best score):
939 // Pentium 3 - 128 / prefetchnta
940 // Pentium 4 - 512 / prefetchnta
941 // Athlon - 128 / prefetchnta
942 // Opteron - 256 / prefetchnta
943 // Core - 256 / prefetchnta
944 // It will be used only when AllocatePrefetchStyle > 0
945
946 if (is_amd_family()) { // AMD | Hygon
947 if (supports_sse2()) {
948 return 256; // Opteron
949 } else {
950 return 128; // Athlon
951 }
952 } else { // Intel
953 if (supports_sse3() && cpu_family() == 6) {
954 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
955 return 192;
956 } else if (use_watermark_prefetch) { // watermark prefetching on Core
957 #ifdef _LP64
958 return 384;
959 #else
960 return 320;
961 #endif
962 }
963 }
964 if (supports_sse2()) {
965 if (cpu_family() == 6) {
966 return 256; // Pentium M, Core, Core2
967 } else {
968 return 512; // Pentium 4
969 }
970 } else {
971 return 128; // Pentium 3 (and all other old CPUs)
972 }
973 }
974 }
975
976 // SSE2 and later processors implement a 'pause' instruction
977 // that can be used for efficient implementation of
978 // the intrinsic for java.lang.Thread.onSpinWait()
979 static bool supports_on_spin_wait() { return supports_sse2(); }
980
981 // x86_64 supports fast class initialization checks for static methods.
982 static bool supports_fast_class_init_checks() {
983 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
984 }
985
986 // there are several insns to force cache line sync to memory which
987 // we can use to ensure mapped non-volatile memory is up to date with
988 // pending in-cache changes.
989 //
990 // 64 bit cpus always support clflush which writes back and evicts
991 // on 32 bit cpus support is recorded via a feature flag
992 //
993 // clflushopt is optional and acts like clflush except it does
994 // not synchronize with other memory ops. it needs a preceding
995 // and trailing StoreStore fence
996 //
997 // clwb is an optional, intel-specific instruction optional which
998 // writes back without evicting the line. it also does not
999 // synchronize with other memory ops. so, it also needs a preceding
1000 // and trailing StoreStore fence.
1001
1002 #ifdef _LP64
1003 static bool supports_clflush() {
1004 // clflush should always be available on x86_64
1005 // if not we are in real trouble because we rely on it
1006 // to flush the code cache.
1007 // Unfortunately, Assembler::clflush is currently called as part
1008 // of generation of the code cache flush routine. This happens
1009 // under Universe::init before the processor features are set
1010 // up. Assembler::flush calls this routine to check that clflush
1011 // is allowed. So, we give the caller a free pass if Universe init
1012 // is still in progress.
1013 assert ((!Universe::is_fully_initialized() || (_features & CPU_FLUSH) != 0), "clflush should be available");
1014 return true;
1015 }
1016 static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); }
1017 static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); }
1018 #else
1019 static bool supports_clflush() { return ((_features & CPU_FLUSH) != 0); }
1020 static bool supports_clflushopt() { return false; }
1021 static bool supports_clwb() { return false; }
1022 #endif // _LP64
1023
1024 // support functions for virtualization detection
1025 private:
1026 static void check_virt_cpuid(uint32_t idx, uint32_t *regs);
1027 static void check_virtualizations();
1028 };
1029
1030 #endif // CPU_X86_VM_VERSION_X86_HPP