1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef SHARE_VM_OPTO_REGMASK_HPP
26 #define SHARE_VM_OPTO_REGMASK_HPP
27
28 #include "code/vmreg.hpp"
29 #include "opto/optoreg.hpp"
30 #ifdef TARGET_ARCH_MODEL_x86_32
31 # include "adfiles/adGlobals_x86_32.hpp"
32 #endif
33 #ifdef TARGET_ARCH_MODEL_x86_64
34 # include "adfiles/adGlobals_x86_64.hpp"
35 #endif
36 #ifdef TARGET_ARCH_MODEL_sparc
37 # include "adfiles/adGlobals_sparc.hpp"
38 #endif
39 #ifdef TARGET_ARCH_MODEL_zero
40 # include "adfiles/adGlobals_zero.hpp"
41 #endif
42 #ifdef TARGET_ARCH_MODEL_arm
43 # include "adfiles/adGlobals_arm.hpp"
44 #endif
45 #ifdef TARGET_ARCH_MODEL_ppc_32
46 # include "adfiles/adGlobals_ppc_32.hpp"
47 #endif
48 #ifdef TARGET_ARCH_MODEL_ppc_64
49 # include "adfiles/adGlobals_ppc_64.hpp"
50 #endif
51
52 // Some fun naming (textual) substitutions:
53 //
54 // RegMask::get_low_elem() ==> RegMask::find_first_elem()
55 // RegMask::Special ==> RegMask::Empty
56 // RegMask::_flags ==> RegMask::is_AllStack()
57 // RegMask::operator<<=() ==> RegMask::Insert()
58 // RegMask::operator>>=() ==> RegMask::Remove()
59 // RegMask::Union() ==> RegMask::OR
60 // RegMask::Inter() ==> RegMask::AND
61 //
62 // OptoRegister::RegName ==> OptoReg::Name
63 //
64 // OptoReg::stack0() ==> _last_Mach_Reg or ZERO in core version
65 //
66 // numregs in chaitin ==> proper degree in chaitin
67
68 //-------------Non-zero bit search methods used by RegMask---------------------
69 // Find lowest 1, or return 32 if empty
70 int find_lowest_bit( uint32_t mask );
71 // Find highest 1, or return 32 if empty
72 int find_hihghest_bit( uint32_t mask );
73
74 //------------------------------RegMask----------------------------------------
75 // The ADL file describes how to print the machine-specific registers, as well
76 // as any notion of register classes. We provide a register mask, which is
77 // just a collection of Register numbers.
78
79 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
80 // RM_SIZE is the size of a register mask in words.
81 // FORALL_BODY replicates a BODY macro once per word in the register mask.
82 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
83 // However, it means the ADLC can redefine the unroll macro and all loops
84 // over register masks will be unrolled by the correct amount.
85
86 class RegMask VALUE_OBJ_CLASS_SPEC {
87 union {
88 double _dummy_force_double_alignment[RM_SIZE>>1];
89 // Array of Register Mask bits. This array is large enough to cover
90 // all the machine registers and all parameters that need to be passed
91 // on the stack (stack registers) up to some interesting limit. Methods
92 // that need more parameters will NOT be compiled. On Intel, the limit
93 // is something like 90+ parameters.
94 int _A[RM_SIZE];
95 };
96
97 enum {
98 _WordBits = BitsPerInt,
99 _LogWordBits = LogBitsPerInt,
100 _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef
101 };
102
103 public:
104 enum { CHUNK_SIZE = RM_SIZE*_WordBits };
105
106 // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
107 // Also, consider the maximum alignment size for a normally allocated
108 // value. Since we allocate register pairs but not register quads (at
109 // present), this alignment is SlotsPerLong (== 2). A normally
110 // aligned allocated register is either a single register, or a pair
111 // of adjacent registers, the lower-numbered being even.
112 // See also is_aligned_Pairs() below, and the padding added before
113 // Matcher::_new_SP to keep allocated pairs aligned properly.
114 // If we ever go to quad-word allocations, SlotsPerQuad will become
115 // the controlling alignment constraint. Note that this alignment
116 // requirement is internal to the allocator, and independent of any
117 // particular platform.
118 enum { SlotsPerLong = 2,
119 SlotsPerVecS = 1,
120 SlotsPerVecD = 2,
121 SlotsPerVecX = 4,
122 SlotsPerVecY = 8 };
123
124 // A constructor only used by the ADLC output. All mask fields are filled
125 // in directly. Calls to this look something like RM(1,2,3,4);
126 RegMask(
127 # define BODY(I) int a##I,
128 FORALL_BODY
129 # undef BODY
130 int dummy = 0 ) {
131 # define BODY(I) _A[I] = a##I;
132 FORALL_BODY
133 # undef BODY
134 }
135
136 // Handy copying constructor
137 RegMask( RegMask *rm ) {
138 # define BODY(I) _A[I] = rm->_A[I];
139 FORALL_BODY
140 # undef BODY
141 }
142
143 // Construct an empty mask
144 RegMask( ) { Clear(); }
145
146 // Construct a mask with a single bit
147 RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); }
148
149 // Check for register being in mask
150 int Member( OptoReg::Name reg ) const {
151 assert( reg < CHUNK_SIZE, "" );
152 return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1)));
153 }
154
155 // The last bit in the register mask indicates that the mask should repeat
156 // indefinitely with ONE bits. Returns TRUE if mask is infinite or
157 // unbounded in size. Returns FALSE if mask is finite size.
158 int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); }
159
160 // Work around an -xO3 optimization problme in WS6U1. The old way:
161 // void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); }
162 // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack()
163 // follows an Insert() loop, like the one found in init_spill_mask(). Using
164 // Insert() instead works because the index into _A in computed instead of
165 // constant. See bug 4665841.
166 void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); }
167
168 // Test for being a not-empty mask.
169 int is_NotEmpty( ) const {
170 int tmp = 0;
171 # define BODY(I) tmp |= _A[I];
172 FORALL_BODY
173 # undef BODY
174 return tmp;
175 }
176
177 // Find lowest-numbered register from mask, or BAD if mask is empty.
178 OptoReg::Name find_first_elem() const {
179 int base, bits;
180 # define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else
181 FORALL_BODY
182 # undef BODY
183 { base = OptoReg::Bad; bits = 1<<0; }
184 return OptoReg::Name(base + find_lowest_bit(bits));
185 }
186 // Get highest-numbered register from mask, or BAD if mask is empty.
187 OptoReg::Name find_last_elem() const {
188 int base, bits;
189 # define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else
190 FORALL_BODY
191 # undef BODY
192 { base = OptoReg::Bad; bits = 1<<0; }
193 return OptoReg::Name(base + find_hihghest_bit(bits));
194 }
195
196 // Find the lowest-numbered register pair in the mask. Return the
197 // HIGHEST register number in the pair, or BAD if no pairs.
198 // Assert that the mask contains only bit pairs.
199 OptoReg::Name find_first_pair() const;
200
201 // Clear out partial bits; leave only aligned adjacent bit pairs.
202 void clear_to_pairs();
203 // Smear out partial bits; leave only aligned adjacent bit pairs.
204 void smear_to_pairs();
205 // Verify that the mask contains only aligned adjacent bit pairs
206 void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); }
207 // Test that the mask contains only aligned adjacent bit pairs
208 bool is_aligned_pairs() const;
209
210 // mask is a pair of misaligned registers
211 bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); }
212 // Test for single register
213 int is_bound1() const;
214 // Test for a single adjacent pair
215 int is_bound_pair() const;
216 // Test for a single adjacent set of ideal register's size.
217 int is_bound(uint ireg) const {
218 if (is_vector(ireg)) {
219 if (is_bound_set(num_registers(ireg)))
220 return true;
221 } else if (is_bound1() || is_bound_pair()) {
222 return true;
223 }
224 return false;
225 }
226
227 // Find the lowest-numbered register set in the mask. Return the
228 // HIGHEST register number in the set, or BAD if no sets.
229 // Assert that the mask contains only bit sets.
230 OptoReg::Name find_first_set(const int size) const;
231
232 // Clear out partial bits; leave only aligned adjacent bit sets of size.
233 void clear_to_sets(const int size);
234 // Smear out partial bits to aligned adjacent bit sets.
235 void smear_to_sets(const int size);
236 // Verify that the mask contains only aligned adjacent bit sets
237 void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); }
238 // Test that the mask contains only aligned adjacent bit sets
239 bool is_aligned_sets(const int size) const;
240
241 // mask is a set of misaligned registers
242 bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);}
243
244 // Test for a single adjacent set
245 int is_bound_set(const int size) const;
246
247 static bool is_vector(uint ireg);
248 static int num_registers(uint ireg);
249
250 // Fast overlap test. Non-zero if any registers in common.
251 int overlap( const RegMask &rm ) const {
252 return
253 # define BODY(I) (_A[I] & rm._A[I]) |
254 FORALL_BODY
255 # undef BODY
256 0 ;
257 }
258
259 // Special test for register pressure based splitting
260 // UP means register only, Register plus stack, or stack only is DOWN
261 bool is_UP() const;
262
263 // Clear a register mask
264 void Clear( ) {
265 # define BODY(I) _A[I] = 0;
266 FORALL_BODY
267 # undef BODY
268 }
269
270 // Fill a register mask with 1's
271 void Set_All( ) {
272 # define BODY(I) _A[I] = -1;
273 FORALL_BODY
274 # undef BODY
275 }
276
277 // Insert register into mask
278 void Insert( OptoReg::Name reg ) {
279 assert( reg < CHUNK_SIZE, "" );
280 _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1)));
281 }
282
283 // Remove register from mask
284 void Remove( OptoReg::Name reg ) {
285 assert( reg < CHUNK_SIZE, "" );
286 _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1)));
287 }
288
289 // OR 'rm' into 'this'
290 void OR( const RegMask &rm ) {
291 # define BODY(I) this->_A[I] |= rm._A[I];
292 FORALL_BODY
293 # undef BODY
294 }
295
296 // AND 'rm' into 'this'
297 void AND( const RegMask &rm ) {
298 # define BODY(I) this->_A[I] &= rm._A[I];
299 FORALL_BODY
300 # undef BODY
301 }
302
303 // Subtract 'rm' from 'this'
304 void SUBTRACT( const RegMask &rm ) {
305 # define BODY(I) _A[I] &= ~rm._A[I];
306 FORALL_BODY
307 # undef BODY
308 }
309
310 // Compute size of register mask: number of bits
311 uint Size() const;
312
313 #ifndef PRODUCT
314 void print() const { dump(); }
315 void dump(outputStream *st = tty) const; // Print a mask
316 #endif
317
318 static const RegMask Empty; // Common empty mask
319
320 static bool can_represent(OptoReg::Name reg) {
321 // NOTE: -1 in computation reflects the usage of the last
322 // bit of the regmask as an infinite stack flag and
323 // -7 is to keep mask aligned for largest value (VecY).
324 return (int)reg < (int)(CHUNK_SIZE-1);
325 }
326 static bool can_represent_arg(OptoReg::Name reg) {
327 // NOTE: -SlotsPerVecY in computation reflects the need
328 // to keep mask aligned for largest value (VecY).
329 return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecY);
330 }
331 };
332
333 // Do not use this constant directly in client code!
334 #undef RM_SIZE
335
336 #endif // SHARE_VM_OPTO_REGMASK_HPP