1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
27 #define CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30 #include "memory/allocation.hpp"
31 #include "runtime/icache.hpp"
32 #include "runtime/os.hpp"
33
34 // We have interfaces for the following instructions:
35 // - NativeInstruction
36 // - - NativeCall
37 // - - NativeMovConstReg
38 // - - NativeMovConstRegPatching
39 // - - NativeMovRegMem
40 // - - NativeMovRegMemPatching
41 // - - NativeJump
42 // - - NativeIllegalOpCode
43 // - - NativeGeneralJump
44 // - - NativeReturn
45 // - - NativeReturnX (return with argument)
46 // - - NativePushConst
47 // - - NativeTstRegMem
48
49 // The base class for different kinds of native instruction abstractions.
50 // Provides the primitive operations to manipulate code relative to this.
51
52 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
53 friend class Relocation;
54 friend bool is_NativeCallTrampolineStub_at(address);
55 public:
56 enum {
57 instruction_size = 4
58 };
59
60 juint encoding() const {
61 return uint_at(0);
62 }
63
64 bool is_blr() const { return (encoding() & 0xff9ffc1f) == 0xd61f0000; } // blr(register) or br(register)
65 bool is_adr_aligned() const { return (encoding() & 0xff000000) == 0x10000000; } // adr Xn, <label>, where label is aligned to 4 bytes (address of instruction).
66
67 inline bool is_nop();
68 inline bool is_illegal();
69 inline bool is_return();
70 bool is_jump();
71 bool is_general_jump();
72 inline bool is_jump_or_nop();
73 inline bool is_cond_jump();
74 bool is_safepoint_poll();
75 bool is_movz();
76 bool is_movk();
77 bool is_sigill_zombie_not_entrant();
78
79 protected:
80 address addr_at(int offset) const { return address(this) + offset; }
81
82 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); }
83 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); }
84
85 jint int_at(int offset) const { return *(jint*) addr_at(offset); }
86 juint uint_at(int offset) const { return *(juint*) addr_at(offset); }
87
88 address ptr_at(int offset) const { return *(address*) addr_at(offset); }
89
90 oop oop_at (int offset) const { return *(oop*) addr_at(offset); }
91
92
93 void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; }
94 void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; }
95 void set_uint_at(int offset, jint i) { *(juint*)addr_at(offset) = i; }
96 void set_ptr_at (int offset, address ptr) { *(address*) addr_at(offset) = ptr; }
97 void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; }
98
99 public:
100
101 // unit test stuff
102 static void test() {} // override for testing
103
104 inline friend NativeInstruction* nativeInstruction_at(address address);
105
106 static bool is_adrp_at(address instr);
107
108 static bool is_ldr_literal_at(address instr);
109
110 bool is_ldr_literal() {
111 return is_ldr_literal_at(addr_at(0));
112 }
113
114 static bool is_ldrw_to_zr(address instr);
115
116 static bool is_call_at(address instr) {
117 const uint32_t insn = (*(uint32_t*)instr);
118 return (insn >> 26) == 0b100101;
119 }
120
121 bool is_call() {
122 return is_call_at(addr_at(0));
123 }
124
125 static bool maybe_cpool_ref(address instr) {
126 return is_adrp_at(instr) || is_ldr_literal_at(instr);
127 }
128
129 bool is_Membar() {
130 unsigned int insn = uint_at(0);
131 return Instruction_aarch64::extract(insn, 31, 12) == 0b11010101000000110011 &&
132 Instruction_aarch64::extract(insn, 7, 0) == 0b10111111;
133 }
134
135 bool is_Imm_LdSt() {
136 unsigned int insn = uint_at(0);
137 return Instruction_aarch64::extract(insn, 29, 27) == 0b111 &&
138 Instruction_aarch64::extract(insn, 23, 23) == 0b0 &&
139 Instruction_aarch64::extract(insn, 26, 25) == 0b00;
140 }
141 };
142
143 inline NativeInstruction* nativeInstruction_at(address address) {
144 return (NativeInstruction*)address;
145 }
146
147 // The natural type of an AArch64 instruction is uint32_t
148 inline NativeInstruction* nativeInstruction_at(uint32_t *address) {
149 return (NativeInstruction*)address;
150 }
151
152 inline NativeCall* nativeCall_at(address address);
153 // The NativeCall is an abstraction for accessing/manipulating native
154 // call instructions (used to manipulate inline caches, primitive &
155 // DSO calls, etc.).
156
157 class NativeCall: public NativeInstruction {
158 public:
159 enum Aarch64_specific_constants {
160 instruction_size = 4,
161 instruction_offset = 0,
162 displacement_offset = 0,
163 return_address_offset = 4
164 };
165
166 address instruction_address() const { return addr_at(instruction_offset); }
167 address next_instruction_address() const { return addr_at(return_address_offset); }
168 int displacement() const { return (int_at(displacement_offset) << 6) >> 4; }
169 address displacement_address() const { return addr_at(displacement_offset); }
170 address return_address() const { return addr_at(return_address_offset); }
171 address destination() const;
172
173 void set_destination(address dest) {
174 int offset = dest - instruction_address();
175 unsigned int insn = 0b100101 << 26;
176 assert((offset & 3) == 0, "should be");
177 offset >>= 2;
178 offset &= (1 << 26) - 1; // mask off insn part
179 insn |= offset;
180 set_int_at(displacement_offset, insn);
181 }
182
183 void verify_alignment() { ; }
184 void verify();
185 void print();
186
187 // Creation
188 inline friend NativeCall* nativeCall_at(address address);
189 inline friend NativeCall* nativeCall_before(address return_address);
190
191 static bool is_call_before(address return_address) {
192 return is_call_at(return_address - NativeCall::return_address_offset);
193 }
194
195 // MT-safe patching of a call instruction.
196 static void insert(address code_pos, address entry);
197
198 static void replace_mt_safe(address instr_addr, address code_buffer);
199
200 // Similar to replace_mt_safe, but just changes the destination. The
201 // important thing is that free-running threads are able to execute
202 // this call instruction at all times. If the call is an immediate BL
203 // instruction we can simply rely on atomicity of 32-bit writes to
204 // make sure other threads will see no intermediate states.
205
206 // We cannot rely on locks here, since the free-running threads must run at
207 // full speed.
208 //
209 // Used in the runtime linkage of calls; see class CompiledIC.
210 // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
211
212 // The parameter assert_lock disables the assertion during code generation.
213 void set_destination_mt_safe(address dest, bool assert_lock = true);
214
215 address get_trampoline();
216 address trampoline_jump(CodeBuffer &cbuf, address dest);
217 };
218
219 inline NativeCall* nativeCall_at(address address) {
220 NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
221 #ifdef ASSERT
222 call->verify();
223 #endif
224 return call;
225 }
226
227 inline NativeCall* nativeCall_before(address return_address) {
228 NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
229 #ifdef ASSERT
230 call->verify();
231 #endif
232 return call;
233 }
234
235 // An interface for accessing/manipulating native mov reg, imm instructions.
236 // (used to manipulate inlined 64-bit data calls, etc.)
237 class NativeMovConstReg: public NativeInstruction {
238 public:
239 enum Aarch64_specific_constants {
240 instruction_size = 3 * 4, // movz, movk, movk. See movptr().
241 instruction_offset = 0,
242 displacement_offset = 0,
243 };
244
245 address instruction_address() const { return addr_at(instruction_offset); }
246 address next_instruction_address() const {
247 if (nativeInstruction_at(instruction_address())->is_movz())
248 // Assume movz, movk, movk
249 return addr_at(instruction_size);
250 else if (is_adrp_at(instruction_address()))
251 return addr_at(2*4);
252 else if (is_ldr_literal_at(instruction_address()))
253 return(addr_at(4));
254 assert(false, "Unknown instruction in NativeMovConstReg");
255 return NULL;
256 }
257
258 intptr_t data() const;
259 void set_data(intptr_t x);
260
261 void flush() {
262 if (! maybe_cpool_ref(instruction_address())) {
263 ICache::invalidate_range(instruction_address(), instruction_size);
264 }
265 }
266
267 void verify();
268 void print();
269
270 // unit test stuff
271 static void test() {}
272
273 // Creation
274 inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
275 inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
276 };
277
278 inline NativeMovConstReg* nativeMovConstReg_at(address address) {
279 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
280 #ifdef ASSERT
281 test->verify();
282 #endif
283 return test;
284 }
285
286 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
287 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
288 #ifdef ASSERT
289 test->verify();
290 #endif
291 return test;
292 }
293
294 class NativeMovConstRegPatching: public NativeMovConstReg {
295 private:
296 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
297 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
298 #ifdef ASSERT
299 test->verify();
300 #endif
301 return test;
302 }
303 };
304
305 // An interface for accessing/manipulating native moves of the form:
306 // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem)
307 // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg
308 // mov[s/z]x[w/b/q] [reg + offset], reg
309 // fld_s [reg+offset]
310 // fld_d [reg+offset]
311 // fstp_s [reg + offset]
312 // fstp_d [reg + offset]
313 // mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
314 //
315 // Warning: These routines must be able to handle any instruction sequences
316 // that are generated as a result of the load/store byte,word,long
317 // macros. For example: The load_unsigned_byte instruction generates
318 // an xor reg,reg inst prior to generating the movb instruction. This
319 // class must skip the xor instruction.
320
321 class NativeMovRegMem: public NativeInstruction {
322 enum AArch64_specific_constants {
323 instruction_size = 4,
324 instruction_offset = 0,
325 data_offset = 0,
326 next_instruction_offset = 4
327 };
328
329 public:
330 // helper
331 int instruction_start() const;
332
333 address instruction_address() const;
334
335 address next_instruction_address() const;
336
337 int offset() const;
338
339 void set_offset(int x);
340
341 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); }
342
343 void verify();
344 void print ();
345
346 // unit test stuff
347 static void test() {}
348
349 private:
350 inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
351 };
352
353 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
354 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
355 #ifdef ASSERT
356 test->verify();
357 #endif
358 return test;
359 }
360
361 class NativeMovRegMemPatching: public NativeMovRegMem {
362 private:
363 friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {Unimplemented(); return 0; }
364 };
365
366 // An interface for accessing/manipulating native leal instruction of form:
367 // leal reg, [reg + offset]
368
369 class NativeLoadAddress: public NativeInstruction {
370 enum AArch64_specific_constants {
371 instruction_size = 4,
372 instruction_offset = 0,
373 data_offset = 0,
374 next_instruction_offset = 4
375 };
376
377 public:
378 void verify();
379 void print ();
380
381 // unit test stuff
382 static void test() {}
383 };
384
385 class NativeJump: public NativeInstruction {
386 public:
387 enum AArch64_specific_constants {
388 instruction_size = 4,
389 instruction_offset = 0,
390 data_offset = 0,
391 next_instruction_offset = 4
392 };
393
394 address instruction_address() const { return addr_at(instruction_offset); }
395 address next_instruction_address() const { return addr_at(instruction_size); }
396 address jump_destination() const;
397 void set_jump_destination(address dest);
398
399 // Creation
400 inline friend NativeJump* nativeJump_at(address address);
401
402 void verify();
403
404 // Unit testing stuff
405 static void test() {}
406
407 // Insertion of native jump instruction
408 static void insert(address code_pos, address entry);
409 // MT-safe insertion of native jump at verified method entry
410 static void check_verified_entry_alignment(address entry, address verified_entry);
411 static void patch_verified_entry(address entry, address verified_entry, address dest);
412 };
413
414 inline NativeJump* nativeJump_at(address address) {
415 NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
416 #ifdef ASSERT
417 jump->verify();
418 #endif
419 return jump;
420 }
421
422 class NativeGeneralJump: public NativeJump {
423 public:
424 enum AArch64_specific_constants {
425 instruction_size = 4 * 4,
426 instruction_offset = 0,
427 data_offset = 0,
428 next_instruction_offset = 4 * 4
429 };
430
431 address jump_destination() const;
432 void set_jump_destination(address dest);
433
434 static void insert_unconditional(address code_pos, address entry);
435 static void replace_mt_safe(address instr_addr, address code_buffer);
436 static void verify();
437 };
438
439 inline NativeGeneralJump* nativeGeneralJump_at(address address) {
440 NativeGeneralJump* jump = (NativeGeneralJump*)(address);
441 debug_only(jump->verify();)
442 return jump;
443 }
444
445 class NativePopReg : public NativeInstruction {
446 public:
447 // Insert a pop instruction
448 static void insert(address code_pos, Register reg);
449 };
450
451
452 class NativeIllegalInstruction: public NativeInstruction {
453 public:
454 // Insert illegal opcode as specific address
455 static void insert(address code_pos);
456 };
457
458 // return instruction that does not pop values of the stack
459 class NativeReturn: public NativeInstruction {
460 public:
461 };
462
463 // return instruction that does pop values of the stack
464 class NativeReturnX: public NativeInstruction {
465 public:
466 };
467
468 // Simple test vs memory
469 class NativeTstRegMem: public NativeInstruction {
470 public:
471 };
472
473 inline bool NativeInstruction::is_nop() {
474 uint32_t insn = *(uint32_t*)addr_at(0);
475 return insn == 0xd503201f;
476 }
477
478 inline bool NativeInstruction::is_jump() {
479 uint32_t insn = *(uint32_t*)addr_at(0);
480
481 if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
482 // Unconditional branch (immediate)
483 return true;
484 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
485 // Conditional branch (immediate)
486 return true;
487 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
488 // Compare & branch (immediate)
489 return true;
490 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
491 // Test & branch (immediate)
492 return true;
493 } else
494 return false;
495 }
496
497 inline bool NativeInstruction::is_jump_or_nop() {
498 return is_nop() || is_jump();
499 }
500
501 // Call trampoline stubs.
502 class NativeCallTrampolineStub : public NativeInstruction {
503 public:
504
505 enum AArch64_specific_constants {
506 instruction_size = 4 * 4,
507 instruction_offset = 0,
508 data_offset = 2 * 4,
509 next_instruction_offset = 4 * 4
510 };
511
512 address destination(nmethod *nm = NULL) const;
513 void set_destination(address new_destination);
514 ptrdiff_t destination_offset() const;
515 };
516
517 inline bool is_NativeCallTrampolineStub_at(address addr) {
518 // Ensure that the stub is exactly
519 // ldr xscratch1, L
520 // br xscratch1
521 // L:
522 uint32_t *i = (uint32_t *)addr;
523 return i[0] == 0x58000048 && i[1] == 0xd61f0100;
524 }
525
526 inline NativeCallTrampolineStub* nativeCallTrampolineStub_at(address addr) {
527 assert(is_NativeCallTrampolineStub_at(addr), "no call trampoline found");
528 return (NativeCallTrampolineStub*)addr;
529 }
530
531 class NativeMembar : public NativeInstruction {
532 public:
533 unsigned int get_kind() { return Instruction_aarch64::extract(uint_at(0), 11, 8); }
534 void set_kind(int order_kind) { Instruction_aarch64::patch(addr_at(0), 11, 8, order_kind); }
535 };
536
537 inline NativeMembar *NativeMembar_at(address addr) {
538 assert(nativeInstruction_at(addr)->is_Membar(), "no membar found");
539 return (NativeMembar*)addr;
540 }
541
542 class NativeLdSt : public NativeInstruction {
543 private:
544 int32_t size() { return Instruction_aarch64::extract(uint_at(0), 31, 30); }
545 // Check whether instruction is with unscaled offset.
546 bool is_ldst_ur() {
547 return (Instruction_aarch64::extract(uint_at(0), 29, 21) == 0b111000010 ||
548 Instruction_aarch64::extract(uint_at(0), 29, 21) == 0b111000000) &&
549 Instruction_aarch64::extract(uint_at(0), 11, 10) == 0b00;
550 }
551 bool is_ldst_unsigned_offset() {
552 return Instruction_aarch64::extract(uint_at(0), 29, 22) == 0b11100101 ||
553 Instruction_aarch64::extract(uint_at(0), 29, 22) == 0b11100100;
554 }
555 public:
556 Register target() {
557 uint32_t r = Instruction_aarch64::extract(uint_at(0), 4, 0);
558 return r == 0x1f ? zr : as_Register(r);
559 }
560 Register base() {
561 uint32_t b = Instruction_aarch64::extract(uint_at(0), 9, 5);
562 return b == 0x1f ? sp : as_Register(b);
563 }
564 int64_t offset() {
565 if (is_ldst_ur()) {
566 return Instruction_aarch64::sextract(uint_at(0), 20, 12);
567 } else if (is_ldst_unsigned_offset()) {
568 return Instruction_aarch64::extract(uint_at(0), 21, 10) << size();
569 } else {
570 // others like: pre-index or post-index.
571 ShouldNotReachHere();
572 return 0;
573 }
574 }
575 size_t size_in_bytes() { return 1 << size(); }
576 bool is_not_pre_post_index() { return (is_ldst_ur() || is_ldst_unsigned_offset()); }
577 bool is_load() {
578 assert(Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01 ||
579 Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00, "must be ldr or str");
580
581 return Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01;
582 }
583 bool is_store() {
584 assert(Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01 ||
585 Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00, "must be ldr or str");
586
587 return Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00;
588 }
589 };
590
591 inline NativeLdSt *NativeLdSt_at(address addr) {
592 assert(nativeInstruction_at(addr)->is_Imm_LdSt(), "no immediate load/store found");
593 return (NativeLdSt*)addr;
594 }
595 #endif // CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP