1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include <sys/types.h> 27 28 #include "precompiled.hpp" 29 #include "jvm.h" 30 #include "asm/assembler.hpp" 31 #include "asm/assembler.inline.hpp" 32 #include "interpreter/interpreter.hpp" 33 34 #include "compiler/disassembler.hpp" 35 #include "memory/resourceArea.hpp" 36 #include "nativeInst_aarch64.hpp" 37 #include "oops/klass.inline.hpp" 38 #include "oops/oop.inline.hpp" 39 #include "opto/compile.hpp" 40 #include "opto/intrinsicnode.hpp" 41 #include "opto/node.hpp" 42 #include "runtime/biasedLocking.hpp" 43 #include "runtime/icache.hpp" 44 #include "runtime/interfaceSupport.hpp" 45 #include "runtime/sharedRuntime.hpp" 46 #include "runtime/thread.hpp" 47 48 #if INCLUDE_ALL_GCS 49 #include "gc/g1/g1CollectedHeap.inline.hpp" 50 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 51 #include "gc/g1/heapRegion.hpp" 52 #endif 53 54 #ifdef PRODUCT 55 #define BLOCK_COMMENT(str) /* nothing */ 56 #define STOP(error) stop(error) 57 #else 58 #define BLOCK_COMMENT(str) block_comment(str) 59 #define STOP(error) block_comment(error); stop(error) 60 #endif 61 62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 63 64 // Patch any kind of instruction; there may be several instructions. 65 // Return the total length (in bytes) of the instructions. 66 int MacroAssembler::pd_patch_instruction_size(address branch, address target) { 67 int instructions = 1; 68 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant"); 69 long offset = (target - branch) >> 2; 70 unsigned insn = *(unsigned*)branch; 71 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) { 72 // Load register (literal) 73 Instruction_aarch64::spatch(branch, 23, 5, offset); 74 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 75 // Unconditional branch (immediate) 76 Instruction_aarch64::spatch(branch, 25, 0, offset); 77 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 78 // Conditional branch (immediate) 79 Instruction_aarch64::spatch(branch, 23, 5, offset); 80 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 81 // Compare & branch (immediate) 82 Instruction_aarch64::spatch(branch, 23, 5, offset); 83 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 84 // Test & branch (immediate) 85 Instruction_aarch64::spatch(branch, 18, 5, offset); 86 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 87 // PC-rel. addressing 88 offset = target-branch; 89 int shift = Instruction_aarch64::extract(insn, 31, 31); 90 if (shift) { 91 u_int64_t dest = (u_int64_t)target; 92 uint64_t pc_page = (uint64_t)branch >> 12; 93 uint64_t adr_page = (uint64_t)target >> 12; 94 unsigned offset_lo = dest & 0xfff; 95 offset = adr_page - pc_page; 96 97 // We handle 4 types of PC relative addressing 98 // 1 - adrp Rx, target_page 99 // ldr/str Ry, [Rx, #offset_in_page] 100 // 2 - adrp Rx, target_page 101 // add Ry, Rx, #offset_in_page 102 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 103 // movk Rx, #imm16<<32 104 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 105 // In the first 3 cases we must check that Rx is the same in the adrp and the 106 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end 107 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened 108 // to be followed by a random unrelated ldr/str, add or movk instruction. 109 // 110 unsigned insn2 = ((unsigned*)branch)[1]; 111 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 112 Instruction_aarch64::extract(insn, 4, 0) == 113 Instruction_aarch64::extract(insn2, 9, 5)) { 114 // Load/store register (unsigned immediate) 115 unsigned size = Instruction_aarch64::extract(insn2, 31, 30); 116 Instruction_aarch64::patch(branch + sizeof (unsigned), 117 21, 10, offset_lo >> size); 118 guarantee(((dest >> size) << size) == dest, "misaligned target"); 119 instructions = 2; 120 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 121 Instruction_aarch64::extract(insn, 4, 0) == 122 Instruction_aarch64::extract(insn2, 4, 0)) { 123 // add (immediate) 124 Instruction_aarch64::patch(branch + sizeof (unsigned), 125 21, 10, offset_lo); 126 instructions = 2; 127 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 128 Instruction_aarch64::extract(insn, 4, 0) == 129 Instruction_aarch64::extract(insn2, 4, 0)) { 130 // movk #imm16<<32 131 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32); 132 long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L); 133 long pc_page = (long)branch >> 12; 134 long adr_page = (long)dest >> 12; 135 offset = adr_page - pc_page; 136 instructions = 2; 137 } 138 } 139 int offset_lo = offset & 3; 140 offset >>= 2; 141 Instruction_aarch64::spatch(branch, 23, 5, offset); 142 Instruction_aarch64::patch(branch, 30, 29, offset_lo); 143 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) { 144 u_int64_t dest = (u_int64_t)target; 145 // Move wide constant 146 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch"); 147 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch"); 148 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff); 149 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff); 150 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff); 151 assert(target_addr_for_insn(branch) == target, "should be"); 152 instructions = 3; 153 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 154 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 155 // nothing to do 156 assert(target == 0, "did not expect to relocate target for polling page load"); 157 } else { 158 ShouldNotReachHere(); 159 } 160 return instructions * NativeInstruction::instruction_size; 161 } 162 163 int MacroAssembler::patch_oop(address insn_addr, address o) { 164 int instructions; 165 unsigned insn = *(unsigned*)insn_addr; 166 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 167 168 // OOPs are either narrow (32 bits) or wide (48 bits). We encode 169 // narrow OOPs by setting the upper 16 bits in the first 170 // instruction. 171 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) { 172 // Move narrow OOP 173 narrowOop n = oopDesc::encode_heap_oop((oop)o); 174 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 175 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 176 instructions = 2; 177 } else { 178 // Move wide OOP 179 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); 180 uintptr_t dest = (uintptr_t)o; 181 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff); 182 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff); 183 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff); 184 instructions = 3; 185 } 186 return instructions * NativeInstruction::instruction_size; 187 } 188 189 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) { 190 // Metatdata pointers are either narrow (32 bits) or wide (48 bits). 191 // We encode narrow ones by setting the upper 16 bits in the first 192 // instruction. 193 NativeInstruction *insn = nativeInstruction_at(insn_addr); 194 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 && 195 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 196 197 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 198 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 199 return 2 * NativeInstruction::instruction_size; 200 } 201 202 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) { 203 long offset = 0; 204 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) { 205 // Load register (literal) 206 offset = Instruction_aarch64::sextract(insn, 23, 5); 207 return address(((uint64_t)insn_addr + (offset << 2))); 208 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 209 // Unconditional branch (immediate) 210 offset = Instruction_aarch64::sextract(insn, 25, 0); 211 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 212 // Conditional branch (immediate) 213 offset = Instruction_aarch64::sextract(insn, 23, 5); 214 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 215 // Compare & branch (immediate) 216 offset = Instruction_aarch64::sextract(insn, 23, 5); 217 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 218 // Test & branch (immediate) 219 offset = Instruction_aarch64::sextract(insn, 18, 5); 220 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 221 // PC-rel. addressing 222 offset = Instruction_aarch64::extract(insn, 30, 29); 223 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2; 224 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0; 225 if (shift) { 226 offset <<= shift; 227 uint64_t target_page = ((uint64_t)insn_addr) + offset; 228 target_page &= ((uint64_t)-1) << shift; 229 // Return the target address for the following sequences 230 // 1 - adrp Rx, target_page 231 // ldr/str Ry, [Rx, #offset_in_page] 232 // 2 - adrp Rx, target_page 233 // add Ry, Rx, #offset_in_page 234 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 235 // movk Rx, #imm12<<32 236 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 237 // 238 // In the first two cases we check that the register is the same and 239 // return the target_page + the offset within the page. 240 // Otherwise we assume it is a page aligned relocation and return 241 // the target page only. 242 // 243 unsigned insn2 = ((unsigned*)insn_addr)[1]; 244 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 245 Instruction_aarch64::extract(insn, 4, 0) == 246 Instruction_aarch64::extract(insn2, 9, 5)) { 247 // Load/store register (unsigned immediate) 248 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 249 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30); 250 return address(target_page + (byte_offset << size)); 251 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 252 Instruction_aarch64::extract(insn, 4, 0) == 253 Instruction_aarch64::extract(insn2, 4, 0)) { 254 // add (immediate) 255 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 256 return address(target_page + byte_offset); 257 } else { 258 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 259 Instruction_aarch64::extract(insn, 4, 0) == 260 Instruction_aarch64::extract(insn2, 4, 0)) { 261 target_page = (target_page & 0xffffffff) | 262 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32); 263 } 264 return (address)target_page; 265 } 266 } else { 267 ShouldNotReachHere(); 268 } 269 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) { 270 u_int32_t *insns = (u_int32_t *)insn_addr; 271 // Move wide constant: movz, movk, movk. See movptr(). 272 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); 273 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); 274 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5)) 275 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) 276 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); 277 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 278 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 279 return 0; 280 } else { 281 ShouldNotReachHere(); 282 } 283 return address(((uint64_t)insn_addr + (offset << 2))); 284 } 285 286 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 287 dsb(Assembler::SY); 288 } 289 290 void MacroAssembler::safepoint_poll(Label& slow_path) { 291 if (SafepointMechanism::uses_thread_local_poll()) { 292 ldr(rscratch1, Address(rthread, Thread::polling_page_offset())); 293 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path); 294 } else { 295 unsigned long offset; 296 adrp(rscratch1, ExternalAddress(SafepointSynchronize::address_of_state()), offset); 297 ldrw(rscratch1, Address(rscratch1, offset)); 298 assert(SafepointSynchronize::_not_synchronized == 0, "rewrite this code"); 299 cbnz(rscratch1, slow_path); 300 } 301 } 302 303 // Just like safepoint_poll, but use an acquiring load for thread- 304 // local polling. 305 // 306 // We need an acquire here to ensure that any subsequent load of the 307 // global SafepointSynchronize::_state flag is ordered after this load 308 // of the local Thread::_polling page. We don't want this poll to 309 // return false (i.e. not safepointing) and a later poll of the global 310 // SafepointSynchronize::_state spuriously to return true. 311 // 312 // This is to avoid a race when we're in a native->Java transition 313 // racing the code which wakes up from a safepoint. 314 // 315 void MacroAssembler::safepoint_poll_acquire(Label& slow_path) { 316 if (SafepointMechanism::uses_thread_local_poll()) { 317 lea(rscratch1, Address(rthread, Thread::polling_page_offset())); 318 ldar(rscratch1, rscratch1); 319 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path); 320 } else { 321 safepoint_poll(slow_path); 322 } 323 } 324 325 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 326 // we must set sp to zero to clear frame 327 str(zr, Address(rthread, JavaThread::last_Java_sp_offset())); 328 329 // must clear fp, so that compiled frames are not confused; it is 330 // possible that we need it only for debugging 331 if (clear_fp) { 332 str(zr, Address(rthread, JavaThread::last_Java_fp_offset())); 333 } 334 335 // Always clear the pc because it could have been set by make_walkable() 336 str(zr, Address(rthread, JavaThread::last_Java_pc_offset())); 337 } 338 339 // Calls to C land 340 // 341 // When entering C land, the rfp, & resp of the last Java frame have to be recorded 342 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 343 // has to be reset to 0. This is required to allow proper stack traversal. 344 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 345 Register last_java_fp, 346 Register last_java_pc, 347 Register scratch) { 348 349 if (last_java_pc->is_valid()) { 350 str(last_java_pc, Address(rthread, 351 JavaThread::frame_anchor_offset() 352 + JavaFrameAnchor::last_Java_pc_offset())); 353 } 354 355 // determine last_java_sp register 356 if (last_java_sp == sp) { 357 mov(scratch, sp); 358 last_java_sp = scratch; 359 } else if (!last_java_sp->is_valid()) { 360 last_java_sp = esp; 361 } 362 363 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset())); 364 365 // last_java_fp is optional 366 if (last_java_fp->is_valid()) { 367 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset())); 368 } 369 } 370 371 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 372 Register last_java_fp, 373 address last_java_pc, 374 Register scratch) { 375 if (last_java_pc != NULL) { 376 adr(scratch, last_java_pc); 377 } else { 378 // FIXME: This is almost never correct. We should delete all 379 // cases of set_last_Java_frame with last_java_pc=NULL and use the 380 // correct return address instead. 381 adr(scratch, pc()); 382 } 383 384 str(scratch, Address(rthread, 385 JavaThread::frame_anchor_offset() 386 + JavaFrameAnchor::last_Java_pc_offset())); 387 388 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch); 389 } 390 391 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 392 Register last_java_fp, 393 Label &L, 394 Register scratch) { 395 if (L.is_bound()) { 396 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch); 397 } else { 398 InstructionMark im(this); 399 L.add_patch_at(code(), locator()); 400 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch); 401 } 402 } 403 404 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) { 405 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 406 assert(CodeCache::find_blob(entry.target()) != NULL, 407 "destination of far call not found in code cache"); 408 if (far_branches()) { 409 unsigned long offset; 410 // We can use ADRP here because we know that the total size of 411 // the code cache cannot exceed 2Gb. 412 adrp(tmp, entry, offset); 413 add(tmp, tmp, offset); 414 if (cbuf) cbuf->set_insts_mark(); 415 blr(tmp); 416 } else { 417 if (cbuf) cbuf->set_insts_mark(); 418 bl(entry); 419 } 420 } 421 422 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) { 423 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 424 assert(CodeCache::find_blob(entry.target()) != NULL, 425 "destination of far call not found in code cache"); 426 if (far_branches()) { 427 unsigned long offset; 428 // We can use ADRP here because we know that the total size of 429 // the code cache cannot exceed 2Gb. 430 adrp(tmp, entry, offset); 431 add(tmp, tmp, offset); 432 if (cbuf) cbuf->set_insts_mark(); 433 br(tmp); 434 } else { 435 if (cbuf) cbuf->set_insts_mark(); 436 b(entry); 437 } 438 } 439 440 void MacroAssembler::reserved_stack_check() { 441 // testing if reserved zone needs to be enabled 442 Label no_reserved_zone_enabling; 443 444 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset())); 445 cmp(sp, rscratch1); 446 br(Assembler::LO, no_reserved_zone_enabling); 447 448 enter(); // LR and FP are live. 449 lea(rscratch1, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)); 450 mov(c_rarg0, rthread); 451 blr(rscratch1); 452 leave(); 453 454 // We have already removed our own frame. 455 // throw_delayed_StackOverflowError will think that it's been 456 // called by our caller. 457 lea(rscratch1, RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 458 br(rscratch1); 459 should_not_reach_here(); 460 461 bind(no_reserved_zone_enabling); 462 } 463 464 int MacroAssembler::biased_locking_enter(Register lock_reg, 465 Register obj_reg, 466 Register swap_reg, 467 Register tmp_reg, 468 bool swap_reg_contains_mark, 469 Label& done, 470 Label* slow_case, 471 BiasedLockingCounters* counters) { 472 assert(UseBiasedLocking, "why call this otherwise?"); 473 assert_different_registers(lock_reg, obj_reg, swap_reg); 474 475 if (PrintBiasedLockingStatistics && counters == NULL) 476 counters = BiasedLocking::counters(); 477 478 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg); 479 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 480 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 481 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); 482 Address saved_mark_addr(lock_reg, 0); 483 484 // Biased locking 485 // See whether the lock is currently biased toward our thread and 486 // whether the epoch is still valid 487 // Note that the runtime guarantees sufficient alignment of JavaThread 488 // pointers to allow age to be placed into low bits 489 // First check to see whether biasing is even enabled for this object 490 Label cas_label; 491 int null_check_offset = -1; 492 if (!swap_reg_contains_mark) { 493 null_check_offset = offset(); 494 ldr(swap_reg, mark_addr); 495 } 496 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place); 497 cmp(tmp_reg, markOopDesc::biased_lock_pattern); 498 br(Assembler::NE, cas_label); 499 // The bias pattern is present in the object's header. Need to check 500 // whether the bias owner and the epoch are both still current. 501 load_prototype_header(tmp_reg, obj_reg); 502 orr(tmp_reg, tmp_reg, rthread); 503 eor(tmp_reg, swap_reg, tmp_reg); 504 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place)); 505 if (counters != NULL) { 506 Label around; 507 cbnz(tmp_reg, around); 508 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2); 509 b(done); 510 bind(around); 511 } else { 512 cbz(tmp_reg, done); 513 } 514 515 Label try_revoke_bias; 516 Label try_rebias; 517 518 // At this point we know that the header has the bias pattern and 519 // that we are not the bias owner in the current epoch. We need to 520 // figure out more details about the state of the header in order to 521 // know what operations can be legally performed on the object's 522 // header. 523 524 // If the low three bits in the xor result aren't clear, that means 525 // the prototype header is no longer biased and we have to revoke 526 // the bias on this object. 527 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place); 528 cbnz(rscratch1, try_revoke_bias); 529 530 // Biasing is still enabled for this data type. See whether the 531 // epoch of the current bias is still valid, meaning that the epoch 532 // bits of the mark word are equal to the epoch bits of the 533 // prototype header. (Note that the prototype header's epoch bits 534 // only change at a safepoint.) If not, attempt to rebias the object 535 // toward the current thread. Note that we must be absolutely sure 536 // that the current epoch is invalid in order to do this because 537 // otherwise the manipulations it performs on the mark word are 538 // illegal. 539 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place); 540 cbnz(rscratch1, try_rebias); 541 542 // The epoch of the current bias is still valid but we know nothing 543 // about the owner; it might be set or it might be clear. Try to 544 // acquire the bias of the object using an atomic operation. If this 545 // fails we will go in to the runtime to revoke the object's bias. 546 // Note that we first construct the presumed unbiased header so we 547 // don't accidentally blow away another thread's valid bias. 548 { 549 Label here; 550 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 551 andr(swap_reg, swap_reg, rscratch1); 552 orr(tmp_reg, swap_reg, rthread); 553 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 554 // If the biasing toward our thread failed, this means that 555 // another thread succeeded in biasing it toward itself and we 556 // need to revoke that bias. The revocation will occur in the 557 // interpreter runtime in the slow case. 558 bind(here); 559 if (counters != NULL) { 560 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()), 561 tmp_reg, rscratch1, rscratch2); 562 } 563 } 564 b(done); 565 566 bind(try_rebias); 567 // At this point we know the epoch has expired, meaning that the 568 // current "bias owner", if any, is actually invalid. Under these 569 // circumstances _only_, we are allowed to use the current header's 570 // value as the comparison value when doing the cas to acquire the 571 // bias in the current epoch. In other words, we allow transfer of 572 // the bias from one thread to another directly in this situation. 573 // 574 // FIXME: due to a lack of registers we currently blow away the age 575 // bits in this situation. Should attempt to preserve them. 576 { 577 Label here; 578 load_prototype_header(tmp_reg, obj_reg); 579 orr(tmp_reg, rthread, tmp_reg); 580 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 581 // If the biasing toward our thread failed, then another thread 582 // succeeded in biasing it toward itself and we need to revoke that 583 // bias. The revocation will occur in the runtime in the slow case. 584 bind(here); 585 if (counters != NULL) { 586 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()), 587 tmp_reg, rscratch1, rscratch2); 588 } 589 } 590 b(done); 591 592 bind(try_revoke_bias); 593 // The prototype mark in the klass doesn't have the bias bit set any 594 // more, indicating that objects of this data type are not supposed 595 // to be biased any more. We are going to try to reset the mark of 596 // this object to the prototype value and fall through to the 597 // CAS-based locking scheme. Note that if our CAS fails, it means 598 // that another thread raced us for the privilege of revoking the 599 // bias of this particular object, so it's okay to continue in the 600 // normal locking code. 601 // 602 // FIXME: due to a lack of registers we currently blow away the age 603 // bits in this situation. Should attempt to preserve them. 604 { 605 Label here, nope; 606 load_prototype_header(tmp_reg, obj_reg); 607 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope); 608 bind(here); 609 610 // Fall through to the normal CAS-based lock, because no matter what 611 // the result of the above CAS, some thread must have succeeded in 612 // removing the bias bit from the object's header. 613 if (counters != NULL) { 614 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg, 615 rscratch1, rscratch2); 616 } 617 bind(nope); 618 } 619 620 bind(cas_label); 621 622 return null_check_offset; 623 } 624 625 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 626 assert(UseBiasedLocking, "why call this otherwise?"); 627 628 // Check for biased locking unlock case, which is a no-op 629 // Note: we do not have to check the thread ID for two reasons. 630 // First, the interpreter checks for IllegalMonitorStateException at 631 // a higher level. Second, if the bias was revoked while we held the 632 // lock, the object could not be rebiased toward another thread, so 633 // the bias bit would be clear. 634 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 635 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place); 636 cmp(temp_reg, markOopDesc::biased_lock_pattern); 637 br(Assembler::EQ, done); 638 } 639 640 static void pass_arg0(MacroAssembler* masm, Register arg) { 641 if (c_rarg0 != arg ) { 642 masm->mov(c_rarg0, arg); 643 } 644 } 645 646 static void pass_arg1(MacroAssembler* masm, Register arg) { 647 if (c_rarg1 != arg ) { 648 masm->mov(c_rarg1, arg); 649 } 650 } 651 652 static void pass_arg2(MacroAssembler* masm, Register arg) { 653 if (c_rarg2 != arg ) { 654 masm->mov(c_rarg2, arg); 655 } 656 } 657 658 static void pass_arg3(MacroAssembler* masm, Register arg) { 659 if (c_rarg3 != arg ) { 660 masm->mov(c_rarg3, arg); 661 } 662 } 663 664 void MacroAssembler::call_VM_base(Register oop_result, 665 Register java_thread, 666 Register last_java_sp, 667 address entry_point, 668 int number_of_arguments, 669 bool check_exceptions) { 670 // determine java_thread register 671 if (!java_thread->is_valid()) { 672 java_thread = rthread; 673 } 674 675 // determine last_java_sp register 676 if (!last_java_sp->is_valid()) { 677 last_java_sp = esp; 678 } 679 680 // debugging support 681 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 682 assert(java_thread == rthread, "unexpected register"); 683 #ifdef ASSERT 684 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 685 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?"); 686 #endif // ASSERT 687 688 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 689 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 690 691 // push java thread (becomes first argument of C function) 692 693 mov(c_rarg0, java_thread); 694 695 // set last Java frame before call 696 assert(last_java_sp != rfp, "can't use rfp"); 697 698 Label l; 699 set_last_Java_frame(last_java_sp, rfp, l, rscratch1); 700 701 // do the call, remove parameters 702 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l); 703 704 // reset last Java frame 705 // Only interpreter should have to clear fp 706 reset_last_Java_frame(true); 707 708 // C++ interp handles this in the interpreter 709 check_and_handle_popframe(java_thread); 710 check_and_handle_earlyret(java_thread); 711 712 if (check_exceptions) { 713 // check for pending exceptions (java_thread is set upon return) 714 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset()))); 715 Label ok; 716 cbz(rscratch1, ok); 717 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry())); 718 br(rscratch1); 719 bind(ok); 720 } 721 722 // get oop result if there is one and reset the value in the thread 723 if (oop_result->is_valid()) { 724 get_vm_result(oop_result, java_thread); 725 } 726 } 727 728 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 729 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); 730 } 731 732 // Maybe emit a call via a trampoline. If the code cache is small 733 // trampolines won't be emitted. 734 735 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) { 736 assert(JavaThread::current()->is_Compiler_thread(), "just checking"); 737 assert(entry.rspec().type() == relocInfo::runtime_call_type 738 || entry.rspec().type() == relocInfo::opt_virtual_call_type 739 || entry.rspec().type() == relocInfo::static_call_type 740 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type"); 741 742 unsigned int start_offset = offset(); 743 if (far_branches() && !Compile::current()->in_scratch_emit_size()) { 744 address stub = emit_trampoline_stub(start_offset, entry.target()); 745 if (stub == NULL) { 746 return NULL; // CodeCache is full 747 } 748 } 749 750 if (cbuf) cbuf->set_insts_mark(); 751 relocate(entry.rspec()); 752 if (!far_branches()) { 753 bl(entry.target()); 754 } else { 755 bl(pc()); 756 } 757 // just need to return a non-null address 758 return pc(); 759 } 760 761 762 // Emit a trampoline stub for a call to a target which is too far away. 763 // 764 // code sequences: 765 // 766 // call-site: 767 // branch-and-link to <destination> or <trampoline stub> 768 // 769 // Related trampoline stub for this call site in the stub section: 770 // load the call target from the constant pool 771 // branch (LR still points to the call site above) 772 773 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset, 774 address dest) { 775 address stub = start_a_stub(Compile::MAX_stubs_size/2); 776 if (stub == NULL) { 777 return NULL; // CodeBuffer::expand failed 778 } 779 780 // Create a trampoline stub relocation which relates this trampoline stub 781 // with the call instruction at insts_call_instruction_offset in the 782 // instructions code-section. 783 align(wordSize); 784 relocate(trampoline_stub_Relocation::spec(code()->insts()->start() 785 + insts_call_instruction_offset)); 786 const int stub_start_offset = offset(); 787 788 // Now, create the trampoline stub's code: 789 // - load the call 790 // - call 791 Label target; 792 ldr(rscratch1, target); 793 br(rscratch1); 794 bind(target); 795 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset, 796 "should be"); 797 emit_int64((int64_t)dest); 798 799 const address stub_start_addr = addr_at(stub_start_offset); 800 801 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 802 803 end_a_stub(); 804 return stub_start_addr; 805 } 806 807 address MacroAssembler::ic_call(address entry, jint method_index) { 808 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 809 // address const_ptr = long_constant((jlong)Universe::non_oop_word()); 810 // unsigned long offset; 811 // ldr_constant(rscratch2, const_ptr); 812 movptr(rscratch2, (uintptr_t)Universe::non_oop_word()); 813 return trampoline_call(Address(entry, rh)); 814 } 815 816 // Implementation of call_VM versions 817 818 void MacroAssembler::call_VM(Register oop_result, 819 address entry_point, 820 bool check_exceptions) { 821 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 822 } 823 824 void MacroAssembler::call_VM(Register oop_result, 825 address entry_point, 826 Register arg_1, 827 bool check_exceptions) { 828 pass_arg1(this, arg_1); 829 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 830 } 831 832 void MacroAssembler::call_VM(Register oop_result, 833 address entry_point, 834 Register arg_1, 835 Register arg_2, 836 bool check_exceptions) { 837 assert(arg_1 != c_rarg2, "smashed arg"); 838 pass_arg2(this, arg_2); 839 pass_arg1(this, arg_1); 840 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 841 } 842 843 void MacroAssembler::call_VM(Register oop_result, 844 address entry_point, 845 Register arg_1, 846 Register arg_2, 847 Register arg_3, 848 bool check_exceptions) { 849 assert(arg_1 != c_rarg3, "smashed arg"); 850 assert(arg_2 != c_rarg3, "smashed arg"); 851 pass_arg3(this, arg_3); 852 853 assert(arg_1 != c_rarg2, "smashed arg"); 854 pass_arg2(this, arg_2); 855 856 pass_arg1(this, arg_1); 857 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 858 } 859 860 void MacroAssembler::call_VM(Register oop_result, 861 Register last_java_sp, 862 address entry_point, 863 int number_of_arguments, 864 bool check_exceptions) { 865 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 866 } 867 868 void MacroAssembler::call_VM(Register oop_result, 869 Register last_java_sp, 870 address entry_point, 871 Register arg_1, 872 bool check_exceptions) { 873 pass_arg1(this, arg_1); 874 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 875 } 876 877 void MacroAssembler::call_VM(Register oop_result, 878 Register last_java_sp, 879 address entry_point, 880 Register arg_1, 881 Register arg_2, 882 bool check_exceptions) { 883 884 assert(arg_1 != c_rarg2, "smashed arg"); 885 pass_arg2(this, arg_2); 886 pass_arg1(this, arg_1); 887 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 888 } 889 890 void MacroAssembler::call_VM(Register oop_result, 891 Register last_java_sp, 892 address entry_point, 893 Register arg_1, 894 Register arg_2, 895 Register arg_3, 896 bool check_exceptions) { 897 assert(arg_1 != c_rarg3, "smashed arg"); 898 assert(arg_2 != c_rarg3, "smashed arg"); 899 pass_arg3(this, arg_3); 900 assert(arg_1 != c_rarg2, "smashed arg"); 901 pass_arg2(this, arg_2); 902 pass_arg1(this, arg_1); 903 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 904 } 905 906 907 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 908 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 909 str(zr, Address(java_thread, JavaThread::vm_result_offset())); 910 verify_oop(oop_result, "broken oop in call_VM_base"); 911 } 912 913 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 914 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 915 str(zr, Address(java_thread, JavaThread::vm_result_2_offset())); 916 } 917 918 void MacroAssembler::align(int modulus) { 919 while (offset() % modulus != 0) nop(); 920 } 921 922 // these are no-ops overridden by InterpreterMacroAssembler 923 924 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { } 925 926 void MacroAssembler::check_and_handle_popframe(Register java_thread) { } 927 928 929 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 930 Register tmp, 931 int offset) { 932 intptr_t value = *delayed_value_addr; 933 if (value != 0) 934 return RegisterOrConstant(value + offset); 935 936 // load indirectly to solve generation ordering problem 937 ldr(tmp, ExternalAddress((address) delayed_value_addr)); 938 939 if (offset != 0) 940 add(tmp, tmp, offset); 941 942 return RegisterOrConstant(tmp); 943 } 944 945 946 void MacroAssembler:: notify(int type) { 947 if (type == bytecode_start) { 948 // set_last_Java_frame(esp, rfp, (address)NULL); 949 Assembler:: notify(type); 950 // reset_last_Java_frame(true); 951 } 952 else 953 Assembler:: notify(type); 954 } 955 956 // Look up the method for a megamorphic invokeinterface call. 957 // The target method is determined by <intf_klass, itable_index>. 958 // The receiver klass is in recv_klass. 959 // On success, the result will be in method_result, and execution falls through. 960 // On failure, execution transfers to the given label. 961 void MacroAssembler::lookup_interface_method(Register recv_klass, 962 Register intf_klass, 963 RegisterOrConstant itable_index, 964 Register method_result, 965 Register scan_temp, 966 Label& L_no_such_interface, 967 bool return_method) { 968 assert_different_registers(recv_klass, intf_klass, scan_temp); 969 assert_different_registers(method_result, intf_klass, scan_temp); 970 assert(recv_klass != method_result || !return_method, 971 "recv_klass can be destroyed when method isn't needed"); 972 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 973 "caller must use same register for non-constant itable index as for method"); 974 975 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 976 int vtable_base = in_bytes(Klass::vtable_start_offset()); 977 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 978 int scan_step = itableOffsetEntry::size() * wordSize; 979 int vte_size = vtableEntry::size_in_bytes(); 980 assert(vte_size == wordSize, "else adjust times_vte_scale"); 981 982 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 983 984 // %%% Could store the aligned, prescaled offset in the klassoop. 985 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 986 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3))); 987 add(scan_temp, scan_temp, vtable_base); 988 989 if (return_method) { 990 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 991 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 992 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 993 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3))); 994 if (itentry_off) 995 add(recv_klass, recv_klass, itentry_off); 996 } 997 998 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 999 // if (scan->interface() == intf) { 1000 // result = (klass + scan->offset() + itable_index); 1001 // } 1002 // } 1003 Label search, found_method; 1004 1005 for (int peel = 1; peel >= 0; peel--) { 1006 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 1007 cmp(intf_klass, method_result); 1008 1009 if (peel) { 1010 br(Assembler::EQ, found_method); 1011 } else { 1012 br(Assembler::NE, search); 1013 // (invert the test to fall through to found_method...) 1014 } 1015 1016 if (!peel) break; 1017 1018 bind(search); 1019 1020 // Check that the previous entry is non-null. A null entry means that 1021 // the receiver class doesn't implement the interface, and wasn't the 1022 // same as when the caller was compiled. 1023 cbz(method_result, L_no_such_interface); 1024 add(scan_temp, scan_temp, scan_step); 1025 } 1026 1027 bind(found_method); 1028 1029 // Got a hit. 1030 if (return_method) { 1031 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 1032 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0))); 1033 } 1034 } 1035 1036 // virtual method calling 1037 void MacroAssembler::lookup_virtual_method(Register recv_klass, 1038 RegisterOrConstant vtable_index, 1039 Register method_result) { 1040 const int base = in_bytes(Klass::vtable_start_offset()); 1041 assert(vtableEntry::size() * wordSize == 8, 1042 "adjust the scaling in the code below"); 1043 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes(); 1044 1045 if (vtable_index.is_register()) { 1046 lea(method_result, Address(recv_klass, 1047 vtable_index.as_register(), 1048 Address::lsl(LogBytesPerWord))); 1049 ldr(method_result, Address(method_result, vtable_offset_in_bytes)); 1050 } else { 1051 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize; 1052 ldr(method_result, 1053 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0)); 1054 } 1055 } 1056 1057 void MacroAssembler::check_klass_subtype(Register sub_klass, 1058 Register super_klass, 1059 Register temp_reg, 1060 Label& L_success) { 1061 Label L_failure; 1062 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 1063 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 1064 bind(L_failure); 1065 } 1066 1067 1068 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 1069 Register super_klass, 1070 Register temp_reg, 1071 Label* L_success, 1072 Label* L_failure, 1073 Label* L_slow_path, 1074 RegisterOrConstant super_check_offset) { 1075 assert_different_registers(sub_klass, super_klass, temp_reg); 1076 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 1077 if (super_check_offset.is_register()) { 1078 assert_different_registers(sub_klass, super_klass, 1079 super_check_offset.as_register()); 1080 } else if (must_load_sco) { 1081 assert(temp_reg != noreg, "supply either a temp or a register offset"); 1082 } 1083 1084 Label L_fallthrough; 1085 int label_nulls = 0; 1086 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1087 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1088 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 1089 assert(label_nulls <= 1, "at most one NULL in the batch"); 1090 1091 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1092 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 1093 Address super_check_offset_addr(super_klass, sco_offset); 1094 1095 // Hacked jmp, which may only be used just before L_fallthrough. 1096 #define final_jmp(label) \ 1097 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 1098 else b(label) /*omit semi*/ 1099 1100 // If the pointers are equal, we are done (e.g., String[] elements). 1101 // This self-check enables sharing of secondary supertype arrays among 1102 // non-primary types such as array-of-interface. Otherwise, each such 1103 // type would need its own customized SSA. 1104 // We move this check to the front of the fast path because many 1105 // type checks are in fact trivially successful in this manner, 1106 // so we get a nicely predicted branch right at the start of the check. 1107 cmp(sub_klass, super_klass); 1108 br(Assembler::EQ, *L_success); 1109 1110 // Check the supertype display: 1111 if (must_load_sco) { 1112 ldrw(temp_reg, super_check_offset_addr); 1113 super_check_offset = RegisterOrConstant(temp_reg); 1114 } 1115 Address super_check_addr(sub_klass, super_check_offset); 1116 ldr(rscratch1, super_check_addr); 1117 cmp(super_klass, rscratch1); // load displayed supertype 1118 1119 // This check has worked decisively for primary supers. 1120 // Secondary supers are sought in the super_cache ('super_cache_addr'). 1121 // (Secondary supers are interfaces and very deeply nested subtypes.) 1122 // This works in the same check above because of a tricky aliasing 1123 // between the super_cache and the primary super display elements. 1124 // (The 'super_check_addr' can address either, as the case requires.) 1125 // Note that the cache is updated below if it does not help us find 1126 // what we need immediately. 1127 // So if it was a primary super, we can just fail immediately. 1128 // Otherwise, it's the slow path for us (no success at this point). 1129 1130 if (super_check_offset.is_register()) { 1131 br(Assembler::EQ, *L_success); 1132 cmp(super_check_offset.as_register(), sc_offset); 1133 if (L_failure == &L_fallthrough) { 1134 br(Assembler::EQ, *L_slow_path); 1135 } else { 1136 br(Assembler::NE, *L_failure); 1137 final_jmp(*L_slow_path); 1138 } 1139 } else if (super_check_offset.as_constant() == sc_offset) { 1140 // Need a slow path; fast failure is impossible. 1141 if (L_slow_path == &L_fallthrough) { 1142 br(Assembler::EQ, *L_success); 1143 } else { 1144 br(Assembler::NE, *L_slow_path); 1145 final_jmp(*L_success); 1146 } 1147 } else { 1148 // No slow path; it's a fast decision. 1149 if (L_failure == &L_fallthrough) { 1150 br(Assembler::EQ, *L_success); 1151 } else { 1152 br(Assembler::NE, *L_failure); 1153 final_jmp(*L_success); 1154 } 1155 } 1156 1157 bind(L_fallthrough); 1158 1159 #undef final_jmp 1160 } 1161 1162 // These two are taken from x86, but they look generally useful 1163 1164 // scans count pointer sized words at [addr] for occurence of value, 1165 // generic 1166 void MacroAssembler::repne_scan(Register addr, Register value, Register count, 1167 Register scratch) { 1168 Label Lloop, Lexit; 1169 cbz(count, Lexit); 1170 bind(Lloop); 1171 ldr(scratch, post(addr, wordSize)); 1172 cmp(value, scratch); 1173 br(EQ, Lexit); 1174 sub(count, count, 1); 1175 cbnz(count, Lloop); 1176 bind(Lexit); 1177 } 1178 1179 // scans count 4 byte words at [addr] for occurence of value, 1180 // generic 1181 void MacroAssembler::repne_scanw(Register addr, Register value, Register count, 1182 Register scratch) { 1183 Label Lloop, Lexit; 1184 cbz(count, Lexit); 1185 bind(Lloop); 1186 ldrw(scratch, post(addr, wordSize)); 1187 cmpw(value, scratch); 1188 br(EQ, Lexit); 1189 sub(count, count, 1); 1190 cbnz(count, Lloop); 1191 bind(Lexit); 1192 } 1193 1194 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 1195 Register super_klass, 1196 Register temp_reg, 1197 Register temp2_reg, 1198 Label* L_success, 1199 Label* L_failure, 1200 bool set_cond_codes) { 1201 assert_different_registers(sub_klass, super_klass, temp_reg); 1202 if (temp2_reg != noreg) 1203 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1); 1204 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 1205 1206 Label L_fallthrough; 1207 int label_nulls = 0; 1208 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1209 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1210 assert(label_nulls <= 1, "at most one NULL in the batch"); 1211 1212 // a couple of useful fields in sub_klass: 1213 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 1214 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1215 Address secondary_supers_addr(sub_klass, ss_offset); 1216 Address super_cache_addr( sub_klass, sc_offset); 1217 1218 BLOCK_COMMENT("check_klass_subtype_slow_path"); 1219 1220 // Do a linear scan of the secondary super-klass chain. 1221 // This code is rarely used, so simplicity is a virtue here. 1222 // The repne_scan instruction uses fixed registers, which we must spill. 1223 // Don't worry too much about pre-existing connections with the input regs. 1224 1225 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super) 1226 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter) 1227 1228 // Get super_klass value into r0 (even if it was in r5 or r2). 1229 RegSet pushed_registers; 1230 if (!IS_A_TEMP(r2)) pushed_registers += r2; 1231 if (!IS_A_TEMP(r5)) pushed_registers += r5; 1232 1233 if (super_klass != r0 || UseCompressedOops) { 1234 if (!IS_A_TEMP(r0)) pushed_registers += r0; 1235 } 1236 1237 push(pushed_registers, sp); 1238 1239 #ifndef PRODUCT 1240 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr); 1241 Address pst_counter_addr(rscratch2); 1242 ldr(rscratch1, pst_counter_addr); 1243 add(rscratch1, rscratch1, 1); 1244 str(rscratch1, pst_counter_addr); 1245 #endif //PRODUCT 1246 1247 // We will consult the secondary-super array. 1248 ldr(r5, secondary_supers_addr); 1249 // Load the array length. 1250 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes())); 1251 // Skip to start of data. 1252 add(r5, r5, Array<Klass*>::base_offset_in_bytes()); 1253 1254 cmp(sp, zr); // Clear Z flag; SP is never zero 1255 // Scan R2 words at [R5] for an occurrence of R0. 1256 // Set NZ/Z based on last compare. 1257 repne_scan(r5, r0, r2, rscratch1); 1258 1259 // Unspill the temp. registers: 1260 pop(pushed_registers, sp); 1261 1262 br(Assembler::NE, *L_failure); 1263 1264 // Success. Cache the super we found and proceed in triumph. 1265 str(super_klass, super_cache_addr); 1266 1267 if (L_success != &L_fallthrough) { 1268 b(*L_success); 1269 } 1270 1271 #undef IS_A_TEMP 1272 1273 bind(L_fallthrough); 1274 } 1275 1276 1277 void MacroAssembler::verify_oop(Register reg, const char* s) { 1278 if (!VerifyOops) return; 1279 1280 // Pass register number to verify_oop_subroutine 1281 const char* b = NULL; 1282 { 1283 ResourceMark rm; 1284 stringStream ss; 1285 ss.print("verify_oop: %s: %s", reg->name(), s); 1286 b = code_string(ss.as_string()); 1287 } 1288 BLOCK_COMMENT("verify_oop {"); 1289 1290 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1291 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1292 1293 mov(r0, reg); 1294 mov(rscratch1, (address)b); 1295 1296 // call indirectly to solve generation ordering problem 1297 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1298 ldr(rscratch2, Address(rscratch2)); 1299 blr(rscratch2); 1300 1301 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1302 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1303 1304 BLOCK_COMMENT("} verify_oop"); 1305 } 1306 1307 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 1308 if (!VerifyOops) return; 1309 1310 const char* b = NULL; 1311 { 1312 ResourceMark rm; 1313 stringStream ss; 1314 ss.print("verify_oop_addr: %s", s); 1315 b = code_string(ss.as_string()); 1316 } 1317 BLOCK_COMMENT("verify_oop_addr {"); 1318 1319 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1320 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1321 1322 // addr may contain sp so we will have to adjust it based on the 1323 // pushes that we just did. 1324 if (addr.uses(sp)) { 1325 lea(r0, addr); 1326 ldr(r0, Address(r0, 4 * wordSize)); 1327 } else { 1328 ldr(r0, addr); 1329 } 1330 mov(rscratch1, (address)b); 1331 1332 // call indirectly to solve generation ordering problem 1333 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1334 ldr(rscratch2, Address(rscratch2)); 1335 blr(rscratch2); 1336 1337 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1338 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1339 1340 BLOCK_COMMENT("} verify_oop_addr"); 1341 } 1342 1343 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 1344 int extra_slot_offset) { 1345 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 1346 int stackElementSize = Interpreter::stackElementSize; 1347 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 1348 #ifdef ASSERT 1349 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 1350 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 1351 #endif 1352 if (arg_slot.is_constant()) { 1353 return Address(esp, arg_slot.as_constant() * stackElementSize 1354 + offset); 1355 } else { 1356 add(rscratch1, esp, arg_slot.as_register(), 1357 ext::uxtx, exact_log2(stackElementSize)); 1358 return Address(rscratch1, offset); 1359 } 1360 } 1361 1362 void MacroAssembler::call_VM_leaf_base(address entry_point, 1363 int number_of_arguments, 1364 Label *retaddr) { 1365 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr); 1366 } 1367 1368 void MacroAssembler::call_VM_leaf_base1(address entry_point, 1369 int number_of_gp_arguments, 1370 int number_of_fp_arguments, 1371 ret_type type, 1372 Label *retaddr) { 1373 Label E, L; 1374 1375 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); 1376 1377 // We add 1 to number_of_arguments because the thread in arg0 is 1378 // not counted 1379 mov(rscratch1, entry_point); 1380 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type); 1381 if (retaddr) 1382 bind(*retaddr); 1383 1384 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize))); 1385 maybe_isb(); 1386 } 1387 1388 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 1389 call_VM_leaf_base(entry_point, number_of_arguments); 1390 } 1391 1392 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 1393 pass_arg0(this, arg_0); 1394 call_VM_leaf_base(entry_point, 1); 1395 } 1396 1397 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1398 pass_arg0(this, arg_0); 1399 pass_arg1(this, arg_1); 1400 call_VM_leaf_base(entry_point, 2); 1401 } 1402 1403 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, 1404 Register arg_1, Register arg_2) { 1405 pass_arg0(this, arg_0); 1406 pass_arg1(this, arg_1); 1407 pass_arg2(this, arg_2); 1408 call_VM_leaf_base(entry_point, 3); 1409 } 1410 1411 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 1412 pass_arg0(this, arg_0); 1413 MacroAssembler::call_VM_leaf_base(entry_point, 1); 1414 } 1415 1416 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1417 1418 assert(arg_0 != c_rarg1, "smashed arg"); 1419 pass_arg1(this, arg_1); 1420 pass_arg0(this, arg_0); 1421 MacroAssembler::call_VM_leaf_base(entry_point, 2); 1422 } 1423 1424 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1425 assert(arg_0 != c_rarg2, "smashed arg"); 1426 assert(arg_1 != c_rarg2, "smashed arg"); 1427 pass_arg2(this, arg_2); 1428 assert(arg_0 != c_rarg1, "smashed arg"); 1429 pass_arg1(this, arg_1); 1430 pass_arg0(this, arg_0); 1431 MacroAssembler::call_VM_leaf_base(entry_point, 3); 1432 } 1433 1434 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1435 assert(arg_0 != c_rarg3, "smashed arg"); 1436 assert(arg_1 != c_rarg3, "smashed arg"); 1437 assert(arg_2 != c_rarg3, "smashed arg"); 1438 pass_arg3(this, arg_3); 1439 assert(arg_0 != c_rarg2, "smashed arg"); 1440 assert(arg_1 != c_rarg2, "smashed arg"); 1441 pass_arg2(this, arg_2); 1442 assert(arg_0 != c_rarg1, "smashed arg"); 1443 pass_arg1(this, arg_1); 1444 pass_arg0(this, arg_0); 1445 MacroAssembler::call_VM_leaf_base(entry_point, 4); 1446 } 1447 1448 void MacroAssembler::null_check(Register reg, int offset) { 1449 if (needs_explicit_null_check(offset)) { 1450 // provoke OS NULL exception if reg = NULL by 1451 // accessing M[reg] w/o changing any registers 1452 // NOTE: this is plenty to provoke a segv 1453 ldr(zr, Address(reg)); 1454 } else { 1455 // nothing to do, (later) access of M[reg + offset] 1456 // will provoke OS NULL exception if reg = NULL 1457 } 1458 } 1459 1460 // MacroAssembler protected routines needed to implement 1461 // public methods 1462 1463 void MacroAssembler::mov(Register r, Address dest) { 1464 code_section()->relocate(pc(), dest.rspec()); 1465 u_int64_t imm64 = (u_int64_t)dest.target(); 1466 movptr(r, imm64); 1467 } 1468 1469 // Move a constant pointer into r. In AArch64 mode the virtual 1470 // address space is 48 bits in size, so we only need three 1471 // instructions to create a patchable instruction sequence that can 1472 // reach anywhere. 1473 void MacroAssembler::movptr(Register r, uintptr_t imm64) { 1474 #ifndef PRODUCT 1475 { 1476 char buffer[64]; 1477 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1478 block_comment(buffer); 1479 } 1480 #endif 1481 assert(imm64 < (1ul << 48), "48-bit overflow in address constant"); 1482 movz(r, imm64 & 0xffff); 1483 imm64 >>= 16; 1484 movk(r, imm64 & 0xffff, 16); 1485 imm64 >>= 16; 1486 movk(r, imm64 & 0xffff, 32); 1487 } 1488 1489 // Macro to mov replicated immediate to vector register. 1490 // Vd will get the following values for different arrangements in T 1491 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh 1492 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh 1493 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh 1494 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh 1495 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh 1496 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh 1497 // T1D/T2D: invalid 1498 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) { 1499 assert(T != T1D && T != T2D, "invalid arrangement"); 1500 if (T == T8B || T == T16B) { 1501 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)"); 1502 movi(Vd, T, imm32 & 0xff, 0); 1503 return; 1504 } 1505 u_int32_t nimm32 = ~imm32; 1506 if (T == T4H || T == T8H) { 1507 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)"); 1508 imm32 &= 0xffff; 1509 nimm32 &= 0xffff; 1510 } 1511 u_int32_t x = imm32; 1512 int movi_cnt = 0; 1513 int movn_cnt = 0; 1514 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; } 1515 x = nimm32; 1516 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; } 1517 if (movn_cnt < movi_cnt) imm32 = nimm32; 1518 unsigned lsl = 0; 1519 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1520 if (movn_cnt < movi_cnt) 1521 mvni(Vd, T, imm32 & 0xff, lsl); 1522 else 1523 movi(Vd, T, imm32 & 0xff, lsl); 1524 imm32 >>= 8; lsl += 8; 1525 while (imm32) { 1526 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1527 if (movn_cnt < movi_cnt) 1528 bici(Vd, T, imm32 & 0xff, lsl); 1529 else 1530 orri(Vd, T, imm32 & 0xff, lsl); 1531 lsl += 8; imm32 >>= 8; 1532 } 1533 } 1534 1535 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64) 1536 { 1537 #ifndef PRODUCT 1538 { 1539 char buffer[64]; 1540 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1541 block_comment(buffer); 1542 } 1543 #endif 1544 if (operand_valid_for_logical_immediate(false, imm64)) { 1545 orr(dst, zr, imm64); 1546 } else { 1547 // we can use a combination of MOVZ or MOVN with 1548 // MOVK to build up the constant 1549 u_int64_t imm_h[4]; 1550 int zero_count = 0; 1551 int neg_count = 0; 1552 int i; 1553 for (i = 0; i < 4; i++) { 1554 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL); 1555 if (imm_h[i] == 0) { 1556 zero_count++; 1557 } else if (imm_h[i] == 0xffffL) { 1558 neg_count++; 1559 } 1560 } 1561 if (zero_count == 4) { 1562 // one MOVZ will do 1563 movz(dst, 0); 1564 } else if (neg_count == 4) { 1565 // one MOVN will do 1566 movn(dst, 0); 1567 } else if (zero_count == 3) { 1568 for (i = 0; i < 4; i++) { 1569 if (imm_h[i] != 0L) { 1570 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1571 break; 1572 } 1573 } 1574 } else if (neg_count == 3) { 1575 // one MOVN will do 1576 for (int i = 0; i < 4; i++) { 1577 if (imm_h[i] != 0xffffL) { 1578 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1579 break; 1580 } 1581 } 1582 } else if (zero_count == 2) { 1583 // one MOVZ and one MOVK will do 1584 for (i = 0; i < 3; i++) { 1585 if (imm_h[i] != 0L) { 1586 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1587 i++; 1588 break; 1589 } 1590 } 1591 for (;i < 4; i++) { 1592 if (imm_h[i] != 0L) { 1593 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1594 } 1595 } 1596 } else if (neg_count == 2) { 1597 // one MOVN and one MOVK will do 1598 for (i = 0; i < 4; i++) { 1599 if (imm_h[i] != 0xffffL) { 1600 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1601 i++; 1602 break; 1603 } 1604 } 1605 for (;i < 4; i++) { 1606 if (imm_h[i] != 0xffffL) { 1607 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1608 } 1609 } 1610 } else if (zero_count == 1) { 1611 // one MOVZ and two MOVKs will do 1612 for (i = 0; i < 4; i++) { 1613 if (imm_h[i] != 0L) { 1614 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1615 i++; 1616 break; 1617 } 1618 } 1619 for (;i < 4; i++) { 1620 if (imm_h[i] != 0x0L) { 1621 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1622 } 1623 } 1624 } else if (neg_count == 1) { 1625 // one MOVN and two MOVKs will do 1626 for (i = 0; i < 4; i++) { 1627 if (imm_h[i] != 0xffffL) { 1628 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1629 i++; 1630 break; 1631 } 1632 } 1633 for (;i < 4; i++) { 1634 if (imm_h[i] != 0xffffL) { 1635 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1636 } 1637 } 1638 } else { 1639 // use a MOVZ and 3 MOVKs (makes it easier to debug) 1640 movz(dst, (u_int32_t)imm_h[0], 0); 1641 for (i = 1; i < 4; i++) { 1642 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1643 } 1644 } 1645 } 1646 } 1647 1648 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32) 1649 { 1650 #ifndef PRODUCT 1651 { 1652 char buffer[64]; 1653 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32); 1654 block_comment(buffer); 1655 } 1656 #endif 1657 if (operand_valid_for_logical_immediate(true, imm32)) { 1658 orrw(dst, zr, imm32); 1659 } else { 1660 // we can use MOVZ, MOVN or two calls to MOVK to build up the 1661 // constant 1662 u_int32_t imm_h[2]; 1663 imm_h[0] = imm32 & 0xffff; 1664 imm_h[1] = ((imm32 >> 16) & 0xffff); 1665 if (imm_h[0] == 0) { 1666 movzw(dst, imm_h[1], 16); 1667 } else if (imm_h[0] == 0xffff) { 1668 movnw(dst, imm_h[1] ^ 0xffff, 16); 1669 } else if (imm_h[1] == 0) { 1670 movzw(dst, imm_h[0], 0); 1671 } else if (imm_h[1] == 0xffff) { 1672 movnw(dst, imm_h[0] ^ 0xffff, 0); 1673 } else { 1674 // use a MOVZ and MOVK (makes it easier to debug) 1675 movzw(dst, imm_h[0], 0); 1676 movkw(dst, imm_h[1], 16); 1677 } 1678 } 1679 } 1680 1681 // Form an address from base + offset in Rd. Rd may or may 1682 // not actually be used: you must use the Address that is returned. 1683 // It is up to you to ensure that the shift provided matches the size 1684 // of your data. 1685 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) { 1686 if (Address::offset_ok_for_immed(byte_offset, shift)) 1687 // It fits; no need for any heroics 1688 return Address(base, byte_offset); 1689 1690 // Don't do anything clever with negative or misaligned offsets 1691 unsigned mask = (1 << shift) - 1; 1692 if (byte_offset < 0 || byte_offset & mask) { 1693 mov(Rd, byte_offset); 1694 add(Rd, base, Rd); 1695 return Address(Rd); 1696 } 1697 1698 // See if we can do this with two 12-bit offsets 1699 { 1700 unsigned long word_offset = byte_offset >> shift; 1701 unsigned long masked_offset = word_offset & 0xfff000; 1702 if (Address::offset_ok_for_immed(word_offset - masked_offset) 1703 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { 1704 add(Rd, base, masked_offset << shift); 1705 word_offset -= masked_offset; 1706 return Address(Rd, word_offset << shift); 1707 } 1708 } 1709 1710 // Do it the hard way 1711 mov(Rd, byte_offset); 1712 add(Rd, base, Rd); 1713 return Address(Rd); 1714 } 1715 1716 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) { 1717 if (UseLSE) { 1718 mov(tmp, 1); 1719 ldadd(Assembler::word, tmp, zr, counter_addr); 1720 return; 1721 } 1722 Label retry_load; 1723 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 1724 prfm(Address(counter_addr), PSTL1STRM); 1725 bind(retry_load); 1726 // flush and load exclusive from the memory location 1727 ldxrw(tmp, counter_addr); 1728 addw(tmp, tmp, 1); 1729 // if we store+flush with no intervening write tmp wil be zero 1730 stxrw(tmp2, tmp, counter_addr); 1731 cbnzw(tmp2, retry_load); 1732 } 1733 1734 1735 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb, 1736 bool want_remainder, Register scratch) 1737 { 1738 // Full implementation of Java idiv and irem. The function 1739 // returns the (pc) offset of the div instruction - may be needed 1740 // for implicit exceptions. 1741 // 1742 // constraint : ra/rb =/= scratch 1743 // normal case 1744 // 1745 // input : ra: dividend 1746 // rb: divisor 1747 // 1748 // result: either 1749 // quotient (= ra idiv rb) 1750 // remainder (= ra irem rb) 1751 1752 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1753 1754 int idivl_offset = offset(); 1755 if (! want_remainder) { 1756 sdivw(result, ra, rb); 1757 } else { 1758 sdivw(scratch, ra, rb); 1759 Assembler::msubw(result, scratch, rb, ra); 1760 } 1761 1762 return idivl_offset; 1763 } 1764 1765 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb, 1766 bool want_remainder, Register scratch) 1767 { 1768 // Full implementation of Java ldiv and lrem. The function 1769 // returns the (pc) offset of the div instruction - may be needed 1770 // for implicit exceptions. 1771 // 1772 // constraint : ra/rb =/= scratch 1773 // normal case 1774 // 1775 // input : ra: dividend 1776 // rb: divisor 1777 // 1778 // result: either 1779 // quotient (= ra idiv rb) 1780 // remainder (= ra irem rb) 1781 1782 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1783 1784 int idivq_offset = offset(); 1785 if (! want_remainder) { 1786 sdiv(result, ra, rb); 1787 } else { 1788 sdiv(scratch, ra, rb); 1789 Assembler::msub(result, scratch, rb, ra); 1790 } 1791 1792 return idivq_offset; 1793 } 1794 1795 void MacroAssembler::membar(Membar_mask_bits order_constraint) { 1796 address prev = pc() - NativeMembar::instruction_size; 1797 if (prev == code()->last_membar()) { 1798 NativeMembar *bar = NativeMembar_at(prev); 1799 // We are merging two memory barrier instructions. On AArch64 we 1800 // can do this simply by ORing them together. 1801 bar->set_kind(bar->get_kind() | order_constraint); 1802 BLOCK_COMMENT("merged membar"); 1803 } else { 1804 code()->set_last_membar(pc()); 1805 dmb(Assembler::barrier(order_constraint)); 1806 } 1807 } 1808 1809 // MacroAssembler routines found actually to be needed 1810 1811 void MacroAssembler::push(Register src) 1812 { 1813 str(src, Address(pre(esp, -1 * wordSize))); 1814 } 1815 1816 void MacroAssembler::pop(Register dst) 1817 { 1818 ldr(dst, Address(post(esp, 1 * wordSize))); 1819 } 1820 1821 // Note: load_unsigned_short used to be called load_unsigned_word. 1822 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 1823 int off = offset(); 1824 ldrh(dst, src); 1825 return off; 1826 } 1827 1828 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 1829 int off = offset(); 1830 ldrb(dst, src); 1831 return off; 1832 } 1833 1834 int MacroAssembler::load_signed_short(Register dst, Address src) { 1835 int off = offset(); 1836 ldrsh(dst, src); 1837 return off; 1838 } 1839 1840 int MacroAssembler::load_signed_byte(Register dst, Address src) { 1841 int off = offset(); 1842 ldrsb(dst, src); 1843 return off; 1844 } 1845 1846 int MacroAssembler::load_signed_short32(Register dst, Address src) { 1847 int off = offset(); 1848 ldrshw(dst, src); 1849 return off; 1850 } 1851 1852 int MacroAssembler::load_signed_byte32(Register dst, Address src) { 1853 int off = offset(); 1854 ldrsbw(dst, src); 1855 return off; 1856 } 1857 1858 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 1859 switch (size_in_bytes) { 1860 case 8: ldr(dst, src); break; 1861 case 4: ldrw(dst, src); break; 1862 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 1863 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 1864 default: ShouldNotReachHere(); 1865 } 1866 } 1867 1868 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 1869 switch (size_in_bytes) { 1870 case 8: str(src, dst); break; 1871 case 4: strw(src, dst); break; 1872 case 2: strh(src, dst); break; 1873 case 1: strb(src, dst); break; 1874 default: ShouldNotReachHere(); 1875 } 1876 } 1877 1878 void MacroAssembler::decrementw(Register reg, int value) 1879 { 1880 if (value < 0) { incrementw(reg, -value); return; } 1881 if (value == 0) { return; } 1882 if (value < (1 << 12)) { subw(reg, reg, value); return; } 1883 /* else */ { 1884 guarantee(reg != rscratch2, "invalid dst for register decrement"); 1885 movw(rscratch2, (unsigned)value); 1886 subw(reg, reg, rscratch2); 1887 } 1888 } 1889 1890 void MacroAssembler::decrement(Register reg, int value) 1891 { 1892 if (value < 0) { increment(reg, -value); return; } 1893 if (value == 0) { return; } 1894 if (value < (1 << 12)) { sub(reg, reg, value); return; } 1895 /* else */ { 1896 assert(reg != rscratch2, "invalid dst for register decrement"); 1897 mov(rscratch2, (unsigned long)value); 1898 sub(reg, reg, rscratch2); 1899 } 1900 } 1901 1902 void MacroAssembler::decrementw(Address dst, int value) 1903 { 1904 assert(!dst.uses(rscratch1), "invalid dst for address decrement"); 1905 ldrw(rscratch1, dst); 1906 decrementw(rscratch1, value); 1907 strw(rscratch1, dst); 1908 } 1909 1910 void MacroAssembler::decrement(Address dst, int value) 1911 { 1912 assert(!dst.uses(rscratch1), "invalid address for decrement"); 1913 ldr(rscratch1, dst); 1914 decrement(rscratch1, value); 1915 str(rscratch1, dst); 1916 } 1917 1918 void MacroAssembler::incrementw(Register reg, int value) 1919 { 1920 if (value < 0) { decrementw(reg, -value); return; } 1921 if (value == 0) { return; } 1922 if (value < (1 << 12)) { addw(reg, reg, value); return; } 1923 /* else */ { 1924 assert(reg != rscratch2, "invalid dst for register increment"); 1925 movw(rscratch2, (unsigned)value); 1926 addw(reg, reg, rscratch2); 1927 } 1928 } 1929 1930 void MacroAssembler::increment(Register reg, int value) 1931 { 1932 if (value < 0) { decrement(reg, -value); return; } 1933 if (value == 0) { return; } 1934 if (value < (1 << 12)) { add(reg, reg, value); return; } 1935 /* else */ { 1936 assert(reg != rscratch2, "invalid dst for register increment"); 1937 movw(rscratch2, (unsigned)value); 1938 add(reg, reg, rscratch2); 1939 } 1940 } 1941 1942 void MacroAssembler::incrementw(Address dst, int value) 1943 { 1944 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1945 ldrw(rscratch1, dst); 1946 incrementw(rscratch1, value); 1947 strw(rscratch1, dst); 1948 } 1949 1950 void MacroAssembler::increment(Address dst, int value) 1951 { 1952 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1953 ldr(rscratch1, dst); 1954 increment(rscratch1, value); 1955 str(rscratch1, dst); 1956 } 1957 1958 1959 void MacroAssembler::pusha() { 1960 push(0x7fffffff, sp); 1961 } 1962 1963 void MacroAssembler::popa() { 1964 pop(0x7fffffff, sp); 1965 } 1966 1967 // Push lots of registers in the bit set supplied. Don't push sp. 1968 // Return the number of words pushed 1969 int MacroAssembler::push(unsigned int bitset, Register stack) { 1970 int words_pushed = 0; 1971 1972 // Scan bitset to accumulate register pairs 1973 unsigned char regs[32]; 1974 int count = 0; 1975 for (int reg = 0; reg <= 30; reg++) { 1976 if (1 & bitset) 1977 regs[count++] = reg; 1978 bitset >>= 1; 1979 } 1980 regs[count++] = zr->encoding_nocheck(); 1981 count &= ~1; // Only push an even nuber of regs 1982 1983 if (count) { 1984 stp(as_Register(regs[0]), as_Register(regs[1]), 1985 Address(pre(stack, -count * wordSize))); 1986 words_pushed += 2; 1987 } 1988 for (int i = 2; i < count; i += 2) { 1989 stp(as_Register(regs[i]), as_Register(regs[i+1]), 1990 Address(stack, i * wordSize)); 1991 words_pushed += 2; 1992 } 1993 1994 assert(words_pushed == count, "oops, pushed != count"); 1995 1996 return count; 1997 } 1998 1999 int MacroAssembler::pop(unsigned int bitset, Register stack) { 2000 int words_pushed = 0; 2001 2002 // Scan bitset to accumulate register pairs 2003 unsigned char regs[32]; 2004 int count = 0; 2005 for (int reg = 0; reg <= 30; reg++) { 2006 if (1 & bitset) 2007 regs[count++] = reg; 2008 bitset >>= 1; 2009 } 2010 regs[count++] = zr->encoding_nocheck(); 2011 count &= ~1; 2012 2013 for (int i = 2; i < count; i += 2) { 2014 ldp(as_Register(regs[i]), as_Register(regs[i+1]), 2015 Address(stack, i * wordSize)); 2016 words_pushed += 2; 2017 } 2018 if (count) { 2019 ldp(as_Register(regs[0]), as_Register(regs[1]), 2020 Address(post(stack, count * wordSize))); 2021 words_pushed += 2; 2022 } 2023 2024 assert(words_pushed == count, "oops, pushed != count"); 2025 2026 return count; 2027 } 2028 #ifdef ASSERT 2029 void MacroAssembler::verify_heapbase(const char* msg) { 2030 #if 0 2031 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed"); 2032 assert (Universe::heap() != NULL, "java heap should be initialized"); 2033 if (CheckCompressedOops) { 2034 Label ok; 2035 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1 2036 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 2037 br(Assembler::EQ, ok); 2038 stop(msg); 2039 bind(ok); 2040 pop(1 << rscratch1->encoding(), sp); 2041 } 2042 #endif 2043 } 2044 #endif 2045 2046 void MacroAssembler::stop(const char* msg) { 2047 address ip = pc(); 2048 pusha(); 2049 mov(c_rarg0, (address)msg); 2050 mov(c_rarg1, (address)ip); 2051 mov(c_rarg2, sp); 2052 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64)); 2053 // call(c_rarg3); 2054 blrt(c_rarg3, 3, 0, 1); 2055 hlt(0); 2056 } 2057 2058 void MacroAssembler::unimplemented(const char* what) { 2059 char* b = new char[1024]; 2060 jio_snprintf(b, 1024, "unimplemented: %s", what); 2061 stop(b); 2062 } 2063 2064 // If a constant does not fit in an immediate field, generate some 2065 // number of MOV instructions and then perform the operation. 2066 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 2067 add_sub_imm_insn insn1, 2068 add_sub_reg_insn insn2) { 2069 assert(Rd != zr, "Rd = zr and not setting flags?"); 2070 if (operand_valid_for_add_sub_immediate((int)imm)) { 2071 (this->*insn1)(Rd, Rn, imm); 2072 } else { 2073 if (uabs(imm) < (1 << 24)) { 2074 (this->*insn1)(Rd, Rn, imm & -(1 << 12)); 2075 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1)); 2076 } else { 2077 assert_different_registers(Rd, Rn); 2078 mov(Rd, (uint64_t)imm); 2079 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 2080 } 2081 } 2082 } 2083 2084 // Seperate vsn which sets the flags. Optimisations are more restricted 2085 // because we must set the flags correctly. 2086 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 2087 add_sub_imm_insn insn1, 2088 add_sub_reg_insn insn2) { 2089 if (operand_valid_for_add_sub_immediate((int)imm)) { 2090 (this->*insn1)(Rd, Rn, imm); 2091 } else { 2092 assert_different_registers(Rd, Rn); 2093 assert(Rd != zr, "overflow in immediate operand"); 2094 mov(Rd, (uint64_t)imm); 2095 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 2096 } 2097 } 2098 2099 2100 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) { 2101 if (increment.is_register()) { 2102 add(Rd, Rn, increment.as_register()); 2103 } else { 2104 add(Rd, Rn, increment.as_constant()); 2105 } 2106 } 2107 2108 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) { 2109 if (increment.is_register()) { 2110 addw(Rd, Rn, increment.as_register()); 2111 } else { 2112 addw(Rd, Rn, increment.as_constant()); 2113 } 2114 } 2115 2116 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) { 2117 if (decrement.is_register()) { 2118 sub(Rd, Rn, decrement.as_register()); 2119 } else { 2120 sub(Rd, Rn, decrement.as_constant()); 2121 } 2122 } 2123 2124 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) { 2125 if (decrement.is_register()) { 2126 subw(Rd, Rn, decrement.as_register()); 2127 } else { 2128 subw(Rd, Rn, decrement.as_constant()); 2129 } 2130 } 2131 2132 void MacroAssembler::reinit_heapbase() 2133 { 2134 if (UseCompressedOops) { 2135 if (Universe::is_fully_initialized()) { 2136 mov(rheapbase, Universe::narrow_ptrs_base()); 2137 } else { 2138 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 2139 ldr(rheapbase, Address(rheapbase)); 2140 } 2141 } 2142 } 2143 2144 // this simulates the behaviour of the x86 cmpxchg instruction using a 2145 // load linked/store conditional pair. we use the acquire/release 2146 // versions of these instructions so that we flush pending writes as 2147 // per Java semantics. 2148 2149 // n.b the x86 version assumes the old value to be compared against is 2150 // in rax and updates rax with the value located in memory if the 2151 // cmpxchg fails. we supply a register for the old value explicitly 2152 2153 // the aarch64 load linked/store conditional instructions do not 2154 // accept an offset. so, unlike x86, we must provide a plain register 2155 // to identify the memory word to be compared/exchanged rather than a 2156 // register+offset Address. 2157 2158 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 2159 Label &succeed, Label *fail) { 2160 // oldv holds comparison value 2161 // newv holds value to write in exchange 2162 // addr identifies memory word to compare against/update 2163 if (UseLSE) { 2164 mov(tmp, oldv); 2165 casal(Assembler::xword, oldv, newv, addr); 2166 cmp(tmp, oldv); 2167 br(Assembler::EQ, succeed); 2168 membar(AnyAny); 2169 } else { 2170 Label retry_load, nope; 2171 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 2172 prfm(Address(addr), PSTL1STRM); 2173 bind(retry_load); 2174 // flush and load exclusive from the memory location 2175 // and fail if it is not what we expect 2176 ldaxr(tmp, addr); 2177 cmp(tmp, oldv); 2178 br(Assembler::NE, nope); 2179 // if we store+flush with no intervening write tmp wil be zero 2180 stlxr(tmp, newv, addr); 2181 cbzw(tmp, succeed); 2182 // retry so we only ever return after a load fails to compare 2183 // ensures we don't return a stale value after a failed write. 2184 b(retry_load); 2185 // if the memory word differs we return it in oldv and signal a fail 2186 bind(nope); 2187 membar(AnyAny); 2188 mov(oldv, tmp); 2189 } 2190 if (fail) 2191 b(*fail); 2192 } 2193 2194 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp, 2195 Label &succeed, Label *fail) { 2196 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption"); 2197 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail); 2198 } 2199 2200 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 2201 Label &succeed, Label *fail) { 2202 // oldv holds comparison value 2203 // newv holds value to write in exchange 2204 // addr identifies memory word to compare against/update 2205 // tmp returns 0/1 for success/failure 2206 if (UseLSE) { 2207 mov(tmp, oldv); 2208 casal(Assembler::word, oldv, newv, addr); 2209 cmp(tmp, oldv); 2210 br(Assembler::EQ, succeed); 2211 membar(AnyAny); 2212 } else { 2213 Label retry_load, nope; 2214 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 2215 prfm(Address(addr), PSTL1STRM); 2216 bind(retry_load); 2217 // flush and load exclusive from the memory location 2218 // and fail if it is not what we expect 2219 ldaxrw(tmp, addr); 2220 cmp(tmp, oldv); 2221 br(Assembler::NE, nope); 2222 // if we store+flush with no intervening write tmp wil be zero 2223 stlxrw(tmp, newv, addr); 2224 cbzw(tmp, succeed); 2225 // retry so we only ever return after a load fails to compare 2226 // ensures we don't return a stale value after a failed write. 2227 b(retry_load); 2228 // if the memory word differs we return it in oldv and signal a fail 2229 bind(nope); 2230 membar(AnyAny); 2231 mov(oldv, tmp); 2232 } 2233 if (fail) 2234 b(*fail); 2235 } 2236 2237 // A generic CAS; success or failure is in the EQ flag. A weak CAS 2238 // doesn't retry and may fail spuriously. If the oldval is wanted, 2239 // Pass a register for the result, otherwise pass noreg. 2240 2241 // Clobbers rscratch1 2242 void MacroAssembler::cmpxchg(Register addr, Register expected, 2243 Register new_val, 2244 enum operand_size size, 2245 bool acquire, bool release, 2246 bool weak, 2247 Register result) { 2248 if (result == noreg) result = rscratch1; 2249 if (UseLSE) { 2250 mov(result, expected); 2251 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true); 2252 cmp(result, expected); 2253 } else { 2254 BLOCK_COMMENT("cmpxchg {"); 2255 Label retry_load, done; 2256 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 2257 prfm(Address(addr), PSTL1STRM); 2258 bind(retry_load); 2259 load_exclusive(result, addr, size, acquire); 2260 if (size == xword) 2261 cmp(result, expected); 2262 else 2263 cmpw(result, expected); 2264 br(Assembler::NE, done); 2265 store_exclusive(rscratch1, new_val, addr, size, release); 2266 if (weak) { 2267 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller. 2268 } else { 2269 cbnzw(rscratch1, retry_load); 2270 } 2271 bind(done); 2272 BLOCK_COMMENT("} cmpxchg"); 2273 } 2274 } 2275 2276 static bool different(Register a, RegisterOrConstant b, Register c) { 2277 if (b.is_constant()) 2278 return a != c; 2279 else 2280 return a != b.as_register() && a != c && b.as_register() != c; 2281 } 2282 2283 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \ 2284 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \ 2285 if (UseLSE) { \ 2286 prev = prev->is_valid() ? prev : zr; \ 2287 if (incr.is_register()) { \ 2288 AOP(sz, incr.as_register(), prev, addr); \ 2289 } else { \ 2290 mov(rscratch2, incr.as_constant()); \ 2291 AOP(sz, rscratch2, prev, addr); \ 2292 } \ 2293 return; \ 2294 } \ 2295 Register result = rscratch2; \ 2296 if (prev->is_valid()) \ 2297 result = different(prev, incr, addr) ? prev : rscratch2; \ 2298 \ 2299 Label retry_load; \ 2300 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \ 2301 prfm(Address(addr), PSTL1STRM); \ 2302 bind(retry_load); \ 2303 LDXR(result, addr); \ 2304 OP(rscratch1, result, incr); \ 2305 STXR(rscratch2, rscratch1, addr); \ 2306 cbnzw(rscratch2, retry_load); \ 2307 if (prev->is_valid() && prev != result) { \ 2308 IOP(prev, rscratch1, incr); \ 2309 } \ 2310 } 2311 2312 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword) 2313 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word) 2314 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword) 2315 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word) 2316 2317 #undef ATOMIC_OP 2318 2319 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \ 2320 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \ 2321 if (UseLSE) { \ 2322 prev = prev->is_valid() ? prev : zr; \ 2323 AOP(sz, newv, prev, addr); \ 2324 return; \ 2325 } \ 2326 Register result = rscratch2; \ 2327 if (prev->is_valid()) \ 2328 result = different(prev, newv, addr) ? prev : rscratch2; \ 2329 \ 2330 Label retry_load; \ 2331 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \ 2332 prfm(Address(addr), PSTL1STRM); \ 2333 bind(retry_load); \ 2334 LDXR(result, addr); \ 2335 STXR(rscratch1, newv, addr); \ 2336 cbnzw(rscratch1, retry_load); \ 2337 if (prev->is_valid() && prev != result) \ 2338 mov(prev, result); \ 2339 } 2340 2341 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword) 2342 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word) 2343 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword) 2344 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word) 2345 2346 #undef ATOMIC_XCHG 2347 2348 void MacroAssembler::incr_allocated_bytes(Register thread, 2349 Register var_size_in_bytes, 2350 int con_size_in_bytes, 2351 Register t1) { 2352 if (!thread->is_valid()) { 2353 thread = rthread; 2354 } 2355 assert(t1->is_valid(), "need temp reg"); 2356 2357 ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2358 if (var_size_in_bytes->is_valid()) { 2359 add(t1, t1, var_size_in_bytes); 2360 } else { 2361 add(t1, t1, con_size_in_bytes); 2362 } 2363 str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2364 } 2365 2366 #ifndef PRODUCT 2367 extern "C" void findpc(intptr_t x); 2368 #endif 2369 2370 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) 2371 { 2372 // In order to get locks to work, we need to fake a in_VM state 2373 if (ShowMessageBoxOnError ) { 2374 JavaThread* thread = JavaThread::current(); 2375 JavaThreadState saved_state = thread->thread_state(); 2376 thread->set_thread_state(_thread_in_vm); 2377 #ifndef PRODUCT 2378 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 2379 ttyLocker ttyl; 2380 BytecodeCounter::print(); 2381 } 2382 #endif 2383 if (os::message_box(msg, "Execution stopped, print registers?")) { 2384 ttyLocker ttyl; 2385 tty->print_cr(" pc = 0x%016lx", pc); 2386 #ifndef PRODUCT 2387 tty->cr(); 2388 findpc(pc); 2389 tty->cr(); 2390 #endif 2391 tty->print_cr(" r0 = 0x%016lx", regs[0]); 2392 tty->print_cr(" r1 = 0x%016lx", regs[1]); 2393 tty->print_cr(" r2 = 0x%016lx", regs[2]); 2394 tty->print_cr(" r3 = 0x%016lx", regs[3]); 2395 tty->print_cr(" r4 = 0x%016lx", regs[4]); 2396 tty->print_cr(" r5 = 0x%016lx", regs[5]); 2397 tty->print_cr(" r6 = 0x%016lx", regs[6]); 2398 tty->print_cr(" r7 = 0x%016lx", regs[7]); 2399 tty->print_cr(" r8 = 0x%016lx", regs[8]); 2400 tty->print_cr(" r9 = 0x%016lx", regs[9]); 2401 tty->print_cr("r10 = 0x%016lx", regs[10]); 2402 tty->print_cr("r11 = 0x%016lx", regs[11]); 2403 tty->print_cr("r12 = 0x%016lx", regs[12]); 2404 tty->print_cr("r13 = 0x%016lx", regs[13]); 2405 tty->print_cr("r14 = 0x%016lx", regs[14]); 2406 tty->print_cr("r15 = 0x%016lx", regs[15]); 2407 tty->print_cr("r16 = 0x%016lx", regs[16]); 2408 tty->print_cr("r17 = 0x%016lx", regs[17]); 2409 tty->print_cr("r18 = 0x%016lx", regs[18]); 2410 tty->print_cr("r19 = 0x%016lx", regs[19]); 2411 tty->print_cr("r20 = 0x%016lx", regs[20]); 2412 tty->print_cr("r21 = 0x%016lx", regs[21]); 2413 tty->print_cr("r22 = 0x%016lx", regs[22]); 2414 tty->print_cr("r23 = 0x%016lx", regs[23]); 2415 tty->print_cr("r24 = 0x%016lx", regs[24]); 2416 tty->print_cr("r25 = 0x%016lx", regs[25]); 2417 tty->print_cr("r26 = 0x%016lx", regs[26]); 2418 tty->print_cr("r27 = 0x%016lx", regs[27]); 2419 tty->print_cr("r28 = 0x%016lx", regs[28]); 2420 tty->print_cr("r30 = 0x%016lx", regs[30]); 2421 tty->print_cr("r31 = 0x%016lx", regs[31]); 2422 BREAKPOINT; 2423 } 2424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 2425 } else { 2426 ttyLocker ttyl; 2427 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 2428 msg); 2429 assert(false, "DEBUG MESSAGE: %s", msg); 2430 } 2431 } 2432 2433 #ifdef BUILTIN_SIM 2434 // routine to generate an x86 prolog for a stub function which 2435 // bootstraps into the generated ARM code which directly follows the 2436 // stub 2437 // 2438 // the argument encodes the number of general and fp registers 2439 // passed by the caller and the callng convention (currently just 2440 // the number of general registers and assumes C argument passing) 2441 2442 extern "C" { 2443 int aarch64_stub_prolog_size(); 2444 void aarch64_stub_prolog(); 2445 void aarch64_prolog(); 2446 } 2447 2448 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, 2449 address *prolog_ptr) 2450 { 2451 int calltype = (((ret_type & 0x3) << 8) | 2452 ((fp_arg_count & 0xf) << 4) | 2453 (gp_arg_count & 0xf)); 2454 2455 // the addresses for the x86 to ARM entry code we need to use 2456 address start = pc(); 2457 // printf("start = %lx\n", start); 2458 int byteCount = aarch64_stub_prolog_size(); 2459 // printf("byteCount = %x\n", byteCount); 2460 int instructionCount = (byteCount + 3)/ 4; 2461 // printf("instructionCount = %x\n", instructionCount); 2462 for (int i = 0; i < instructionCount; i++) { 2463 nop(); 2464 } 2465 2466 memcpy(start, (void*)aarch64_stub_prolog, byteCount); 2467 2468 // write the address of the setup routine and the call format at the 2469 // end of into the copied code 2470 u_int64_t *patch_end = (u_int64_t *)(start + byteCount); 2471 if (prolog_ptr) 2472 patch_end[-2] = (u_int64_t)prolog_ptr; 2473 patch_end[-1] = calltype; 2474 } 2475 #endif 2476 2477 void MacroAssembler::push_call_clobbered_registers() { 2478 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2479 2480 // Push v0-v7, v16-v31. 2481 for (int i = 30; i >= 0; i -= 2) { 2482 if (i <= v7->encoding() || i >= v16->encoding()) { 2483 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2484 Address(pre(sp, -2 * wordSize))); 2485 } 2486 } 2487 } 2488 2489 void MacroAssembler::pop_call_clobbered_registers() { 2490 2491 for (int i = 0; i < 32; i += 2) { 2492 if (i <= v7->encoding() || i >= v16->encoding()) { 2493 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2494 Address(post(sp, 2 * wordSize))); 2495 } 2496 } 2497 2498 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2499 } 2500 2501 void MacroAssembler::push_CPU_state(bool save_vectors) { 2502 push(0x3fffffff, sp); // integer registers except lr & sp 2503 2504 if (!save_vectors) { 2505 for (int i = 30; i >= 0; i -= 2) 2506 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2507 Address(pre(sp, -2 * wordSize))); 2508 } else { 2509 for (int i = 30; i >= 0; i -= 2) 2510 stpq(as_FloatRegister(i), as_FloatRegister(i+1), 2511 Address(pre(sp, -4 * wordSize))); 2512 } 2513 } 2514 2515 void MacroAssembler::pop_CPU_state(bool restore_vectors) { 2516 if (!restore_vectors) { 2517 for (int i = 0; i < 32; i += 2) 2518 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2519 Address(post(sp, 2 * wordSize))); 2520 } else { 2521 for (int i = 0; i < 32; i += 2) 2522 ldpq(as_FloatRegister(i), as_FloatRegister(i+1), 2523 Address(post(sp, 4 * wordSize))); 2524 } 2525 2526 pop(0x3fffffff, sp); // integer registers except lr & sp 2527 } 2528 2529 /** 2530 * Helpers for multiply_to_len(). 2531 */ 2532 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 2533 Register src1, Register src2) { 2534 adds(dest_lo, dest_lo, src1); 2535 adc(dest_hi, dest_hi, zr); 2536 adds(dest_lo, dest_lo, src2); 2537 adc(final_dest_hi, dest_hi, zr); 2538 } 2539 2540 // Generate an address from (r + r1 extend offset). "size" is the 2541 // size of the operand. The result may be in rscratch2. 2542 Address MacroAssembler::offsetted_address(Register r, Register r1, 2543 Address::extend ext, int offset, int size) { 2544 if (offset || (ext.shift() % size != 0)) { 2545 lea(rscratch2, Address(r, r1, ext)); 2546 return Address(rscratch2, offset); 2547 } else { 2548 return Address(r, r1, ext); 2549 } 2550 } 2551 2552 Address MacroAssembler::spill_address(int size, int offset, Register tmp) 2553 { 2554 assert(offset >= 0, "spill to negative address?"); 2555 // Offset reachable ? 2556 // Not aligned - 9 bits signed offset 2557 // Aligned - 12 bits unsigned offset shifted 2558 Register base = sp; 2559 if ((offset & (size-1)) && offset >= (1<<8)) { 2560 add(tmp, base, offset & ((1<<12)-1)); 2561 base = tmp; 2562 offset &= -1<<12; 2563 } 2564 2565 if (offset >= (1<<12) * size) { 2566 add(tmp, base, offset & (((1<<12)-1)<<12)); 2567 base = tmp; 2568 offset &= ~(((1<<12)-1)<<12); 2569 } 2570 2571 return Address(base, offset); 2572 } 2573 2574 /** 2575 * Multiply 64 bit by 64 bit first loop. 2576 */ 2577 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 2578 Register y, Register y_idx, Register z, 2579 Register carry, Register product, 2580 Register idx, Register kdx) { 2581 // 2582 // jlong carry, x[], y[], z[]; 2583 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2584 // huge_128 product = y[idx] * x[xstart] + carry; 2585 // z[kdx] = (jlong)product; 2586 // carry = (jlong)(product >>> 64); 2587 // } 2588 // z[xstart] = carry; 2589 // 2590 2591 Label L_first_loop, L_first_loop_exit; 2592 Label L_one_x, L_one_y, L_multiply; 2593 2594 subsw(xstart, xstart, 1); 2595 br(Assembler::MI, L_one_x); 2596 2597 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt))); 2598 ldr(x_xstart, Address(rscratch1)); 2599 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian 2600 2601 bind(L_first_loop); 2602 subsw(idx, idx, 1); 2603 br(Assembler::MI, L_first_loop_exit); 2604 subsw(idx, idx, 1); 2605 br(Assembler::MI, L_one_y); 2606 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2607 ldr(y_idx, Address(rscratch1)); 2608 ror(y_idx, y_idx, 32); // convert big-endian to little-endian 2609 bind(L_multiply); 2610 2611 // AArch64 has a multiply-accumulate instruction that we can't use 2612 // here because it has no way to process carries, so we have to use 2613 // separate add and adc instructions. Bah. 2614 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product 2615 mul(product, x_xstart, y_idx); 2616 adds(product, product, carry); 2617 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product 2618 2619 subw(kdx, kdx, 2); 2620 ror(product, product, 32); // back to big-endian 2621 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong)); 2622 2623 b(L_first_loop); 2624 2625 bind(L_one_y); 2626 ldrw(y_idx, Address(y, 0)); 2627 b(L_multiply); 2628 2629 bind(L_one_x); 2630 ldrw(x_xstart, Address(x, 0)); 2631 b(L_first_loop); 2632 2633 bind(L_first_loop_exit); 2634 } 2635 2636 /** 2637 * Multiply 128 bit by 128. Unrolled inner loop. 2638 * 2639 */ 2640 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z, 2641 Register carry, Register carry2, 2642 Register idx, Register jdx, 2643 Register yz_idx1, Register yz_idx2, 2644 Register tmp, Register tmp3, Register tmp4, 2645 Register tmp6, Register product_hi) { 2646 2647 // jlong carry, x[], y[], z[]; 2648 // int kdx = ystart+1; 2649 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 2650 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry; 2651 // jlong carry2 = (jlong)(tmp3 >>> 64); 2652 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2; 2653 // carry = (jlong)(tmp4 >>> 64); 2654 // z[kdx+idx+1] = (jlong)tmp3; 2655 // z[kdx+idx] = (jlong)tmp4; 2656 // } 2657 // idx += 2; 2658 // if (idx > 0) { 2659 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry; 2660 // z[kdx+idx] = (jlong)yz_idx1; 2661 // carry = (jlong)(yz_idx1 >>> 64); 2662 // } 2663 // 2664 2665 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 2666 2667 lsrw(jdx, idx, 2); 2668 2669 bind(L_third_loop); 2670 2671 subsw(jdx, jdx, 1); 2672 br(Assembler::MI, L_third_loop_exit); 2673 subw(idx, idx, 4); 2674 2675 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2676 2677 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0)); 2678 2679 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2680 2681 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 2682 ror(yz_idx2, yz_idx2, 32); 2683 2684 ldp(rscratch2, rscratch1, Address(tmp6, 0)); 2685 2686 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2687 umulh(tmp4, product_hi, yz_idx1); 2688 2689 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian 2690 ror(rscratch2, rscratch2, 32); 2691 2692 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp 2693 umulh(carry2, product_hi, yz_idx2); 2694 2695 // propagate sum of both multiplications into carry:tmp4:tmp3 2696 adds(tmp3, tmp3, carry); 2697 adc(tmp4, tmp4, zr); 2698 adds(tmp3, tmp3, rscratch1); 2699 adcs(tmp4, tmp4, tmp); 2700 adc(carry, carry2, zr); 2701 adds(tmp4, tmp4, rscratch2); 2702 adc(carry, carry, zr); 2703 2704 ror(tmp3, tmp3, 32); // convert little-endian to big-endian 2705 ror(tmp4, tmp4, 32); 2706 stp(tmp4, tmp3, Address(tmp6, 0)); 2707 2708 b(L_third_loop); 2709 bind (L_third_loop_exit); 2710 2711 andw (idx, idx, 0x3); 2712 cbz(idx, L_post_third_loop_done); 2713 2714 Label L_check_1; 2715 subsw(idx, idx, 2); 2716 br(Assembler::MI, L_check_1); 2717 2718 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2719 ldr(yz_idx1, Address(rscratch1, 0)); 2720 ror(yz_idx1, yz_idx1, 32); 2721 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2722 umulh(tmp4, product_hi, yz_idx1); 2723 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2724 ldr(yz_idx2, Address(rscratch1, 0)); 2725 ror(yz_idx2, yz_idx2, 32); 2726 2727 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2); 2728 2729 ror(tmp3, tmp3, 32); 2730 str(tmp3, Address(rscratch1, 0)); 2731 2732 bind (L_check_1); 2733 2734 andw (idx, idx, 0x1); 2735 subsw(idx, idx, 1); 2736 br(Assembler::MI, L_post_third_loop_done); 2737 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2738 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3 2739 umulh(carry2, tmp4, product_hi); 2740 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2741 2742 add2_with_carry(carry2, tmp3, tmp4, carry); 2743 2744 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2745 extr(carry, carry2, tmp3, 32); 2746 2747 bind(L_post_third_loop_done); 2748 } 2749 2750 /** 2751 * Code for BigInteger::multiplyToLen() instrinsic. 2752 * 2753 * r0: x 2754 * r1: xlen 2755 * r2: y 2756 * r3: ylen 2757 * r4: z 2758 * r5: zlen 2759 * r10: tmp1 2760 * r11: tmp2 2761 * r12: tmp3 2762 * r13: tmp4 2763 * r14: tmp5 2764 * r15: tmp6 2765 * r16: tmp7 2766 * 2767 */ 2768 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, 2769 Register z, Register zlen, 2770 Register tmp1, Register tmp2, Register tmp3, Register tmp4, 2771 Register tmp5, Register tmp6, Register product_hi) { 2772 2773 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6); 2774 2775 const Register idx = tmp1; 2776 const Register kdx = tmp2; 2777 const Register xstart = tmp3; 2778 2779 const Register y_idx = tmp4; 2780 const Register carry = tmp5; 2781 const Register product = xlen; 2782 const Register x_xstart = zlen; // reuse register 2783 2784 // First Loop. 2785 // 2786 // final static long LONG_MASK = 0xffffffffL; 2787 // int xstart = xlen - 1; 2788 // int ystart = ylen - 1; 2789 // long carry = 0; 2790 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2791 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 2792 // z[kdx] = (int)product; 2793 // carry = product >>> 32; 2794 // } 2795 // z[xstart] = (int)carry; 2796 // 2797 2798 movw(idx, ylen); // idx = ylen; 2799 movw(kdx, zlen); // kdx = xlen+ylen; 2800 mov(carry, zr); // carry = 0; 2801 2802 Label L_done; 2803 2804 movw(xstart, xlen); 2805 subsw(xstart, xstart, 1); 2806 br(Assembler::MI, L_done); 2807 2808 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 2809 2810 Label L_second_loop; 2811 cbzw(kdx, L_second_loop); 2812 2813 Label L_carry; 2814 subw(kdx, kdx, 1); 2815 cbzw(kdx, L_carry); 2816 2817 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2818 lsr(carry, carry, 32); 2819 subw(kdx, kdx, 1); 2820 2821 bind(L_carry); 2822 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2823 2824 // Second and third (nested) loops. 2825 // 2826 // for (int i = xstart-1; i >= 0; i--) { // Second loop 2827 // carry = 0; 2828 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 2829 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 2830 // (z[k] & LONG_MASK) + carry; 2831 // z[k] = (int)product; 2832 // carry = product >>> 32; 2833 // } 2834 // z[i] = (int)carry; 2835 // } 2836 // 2837 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi 2838 2839 const Register jdx = tmp1; 2840 2841 bind(L_second_loop); 2842 mov(carry, zr); // carry = 0; 2843 movw(jdx, ylen); // j = ystart+1 2844 2845 subsw(xstart, xstart, 1); // i = xstart-1; 2846 br(Assembler::MI, L_done); 2847 2848 str(z, Address(pre(sp, -4 * wordSize))); 2849 2850 Label L_last_x; 2851 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j 2852 subsw(xstart, xstart, 1); // i = xstart-1; 2853 br(Assembler::MI, L_last_x); 2854 2855 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt))); 2856 ldr(product_hi, Address(rscratch1)); 2857 ror(product_hi, product_hi, 32); // convert big-endian to little-endian 2858 2859 Label L_third_loop_prologue; 2860 bind(L_third_loop_prologue); 2861 2862 str(ylen, Address(sp, wordSize)); 2863 stp(x, xstart, Address(sp, 2 * wordSize)); 2864 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product, 2865 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi); 2866 ldp(z, ylen, Address(post(sp, 2 * wordSize))); 2867 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen 2868 2869 addw(tmp3, xlen, 1); 2870 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2871 subsw(tmp3, tmp3, 1); 2872 br(Assembler::MI, L_done); 2873 2874 lsr(carry, carry, 32); 2875 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2876 b(L_second_loop); 2877 2878 // Next infrequent code is moved outside loops. 2879 bind(L_last_x); 2880 ldrw(product_hi, Address(x, 0)); 2881 b(L_third_loop_prologue); 2882 2883 bind(L_done); 2884 } 2885 2886 // Code for BigInteger::mulAdd instrinsic 2887 // out = r0 2888 // in = r1 2889 // offset = r2 (already out.length-offset) 2890 // len = r3 2891 // k = r4 2892 // 2893 // pseudo code from java implementation: 2894 // carry = 0; 2895 // offset = out.length-offset - 1; 2896 // for (int j=len-1; j >= 0; j--) { 2897 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry; 2898 // out[offset--] = (int)product; 2899 // carry = product >>> 32; 2900 // } 2901 // return (int)carry; 2902 void MacroAssembler::mul_add(Register out, Register in, Register offset, 2903 Register len, Register k) { 2904 Label LOOP, END; 2905 // pre-loop 2906 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches 2907 csel(out, zr, out, Assembler::EQ); 2908 br(Assembler::EQ, END); 2909 add(in, in, len, LSL, 2); // in[j+1] address 2910 add(offset, out, offset, LSL, 2); // out[offset + 1] address 2911 mov(out, zr); // used to keep carry now 2912 BIND(LOOP); 2913 ldrw(rscratch1, Address(pre(in, -4))); 2914 madd(rscratch1, rscratch1, k, out); 2915 ldrw(rscratch2, Address(pre(offset, -4))); 2916 add(rscratch1, rscratch1, rscratch2); 2917 strw(rscratch1, Address(offset)); 2918 lsr(out, rscratch1, 32); 2919 subs(len, len, 1); 2920 br(Assembler::NE, LOOP); 2921 BIND(END); 2922 } 2923 2924 /** 2925 * Emits code to update CRC-32 with a byte value according to constants in table 2926 * 2927 * @param [in,out]crc Register containing the crc. 2928 * @param [in]val Register containing the byte to fold into the CRC. 2929 * @param [in]table Register containing the table of crc constants. 2930 * 2931 * uint32_t crc; 2932 * val = crc_table[(val ^ crc) & 0xFF]; 2933 * crc = val ^ (crc >> 8); 2934 * 2935 */ 2936 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 2937 eor(val, val, crc); 2938 andr(val, val, 0xff); 2939 ldrw(val, Address(table, val, Address::lsl(2))); 2940 eor(crc, val, crc, Assembler::LSR, 8); 2941 } 2942 2943 /** 2944 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3 2945 * 2946 * @param [in,out]crc Register containing the crc. 2947 * @param [in]v Register containing the 32-bit to fold into the CRC. 2948 * @param [in]table0 Register containing table 0 of crc constants. 2949 * @param [in]table1 Register containing table 1 of crc constants. 2950 * @param [in]table2 Register containing table 2 of crc constants. 2951 * @param [in]table3 Register containing table 3 of crc constants. 2952 * 2953 * uint32_t crc; 2954 * v = crc ^ v 2955 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24] 2956 * 2957 */ 2958 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp, 2959 Register table0, Register table1, Register table2, Register table3, 2960 bool upper) { 2961 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0); 2962 uxtb(tmp, v); 2963 ldrw(crc, Address(table3, tmp, Address::lsl(2))); 2964 ubfx(tmp, v, 8, 8); 2965 ldrw(tmp, Address(table2, tmp, Address::lsl(2))); 2966 eor(crc, crc, tmp); 2967 ubfx(tmp, v, 16, 8); 2968 ldrw(tmp, Address(table1, tmp, Address::lsl(2))); 2969 eor(crc, crc, tmp); 2970 ubfx(tmp, v, 24, 8); 2971 ldrw(tmp, Address(table0, tmp, Address::lsl(2))); 2972 eor(crc, crc, tmp); 2973 } 2974 2975 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf, 2976 Register len, Register tmp0, Register tmp1, Register tmp2, 2977 Register tmp3) { 2978 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit; 2979 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3); 2980 2981 mvnw(crc, crc); 2982 2983 subs(len, len, 128); 2984 br(Assembler::GE, CRC_by64_pre); 2985 BIND(CRC_less64); 2986 adds(len, len, 128-32); 2987 br(Assembler::GE, CRC_by32_loop); 2988 BIND(CRC_less32); 2989 adds(len, len, 32-4); 2990 br(Assembler::GE, CRC_by4_loop); 2991 adds(len, len, 4); 2992 br(Assembler::GT, CRC_by1_loop); 2993 b(L_exit); 2994 2995 BIND(CRC_by32_loop); 2996 ldp(tmp0, tmp1, Address(post(buf, 16))); 2997 subs(len, len, 32); 2998 crc32x(crc, crc, tmp0); 2999 ldr(tmp2, Address(post(buf, 8))); 3000 crc32x(crc, crc, tmp1); 3001 ldr(tmp3, Address(post(buf, 8))); 3002 crc32x(crc, crc, tmp2); 3003 crc32x(crc, crc, tmp3); 3004 br(Assembler::GE, CRC_by32_loop); 3005 cmn(len, 32); 3006 br(Assembler::NE, CRC_less32); 3007 b(L_exit); 3008 3009 BIND(CRC_by4_loop); 3010 ldrw(tmp0, Address(post(buf, 4))); 3011 subs(len, len, 4); 3012 crc32w(crc, crc, tmp0); 3013 br(Assembler::GE, CRC_by4_loop); 3014 adds(len, len, 4); 3015 br(Assembler::LE, L_exit); 3016 BIND(CRC_by1_loop); 3017 ldrb(tmp0, Address(post(buf, 1))); 3018 subs(len, len, 1); 3019 crc32b(crc, crc, tmp0); 3020 br(Assembler::GT, CRC_by1_loop); 3021 b(L_exit); 3022 3023 BIND(CRC_by64_pre); 3024 sub(buf, buf, 8); 3025 ldp(tmp0, tmp1, Address(buf, 8)); 3026 crc32x(crc, crc, tmp0); 3027 ldr(tmp2, Address(buf, 24)); 3028 crc32x(crc, crc, tmp1); 3029 ldr(tmp3, Address(buf, 32)); 3030 crc32x(crc, crc, tmp2); 3031 ldr(tmp0, Address(buf, 40)); 3032 crc32x(crc, crc, tmp3); 3033 ldr(tmp1, Address(buf, 48)); 3034 crc32x(crc, crc, tmp0); 3035 ldr(tmp2, Address(buf, 56)); 3036 crc32x(crc, crc, tmp1); 3037 ldr(tmp3, Address(pre(buf, 64))); 3038 3039 b(CRC_by64_loop); 3040 3041 align(CodeEntryAlignment); 3042 BIND(CRC_by64_loop); 3043 subs(len, len, 64); 3044 crc32x(crc, crc, tmp2); 3045 ldr(tmp0, Address(buf, 8)); 3046 crc32x(crc, crc, tmp3); 3047 ldr(tmp1, Address(buf, 16)); 3048 crc32x(crc, crc, tmp0); 3049 ldr(tmp2, Address(buf, 24)); 3050 crc32x(crc, crc, tmp1); 3051 ldr(tmp3, Address(buf, 32)); 3052 crc32x(crc, crc, tmp2); 3053 ldr(tmp0, Address(buf, 40)); 3054 crc32x(crc, crc, tmp3); 3055 ldr(tmp1, Address(buf, 48)); 3056 crc32x(crc, crc, tmp0); 3057 ldr(tmp2, Address(buf, 56)); 3058 crc32x(crc, crc, tmp1); 3059 ldr(tmp3, Address(pre(buf, 64))); 3060 br(Assembler::GE, CRC_by64_loop); 3061 3062 // post-loop 3063 crc32x(crc, crc, tmp2); 3064 crc32x(crc, crc, tmp3); 3065 3066 sub(len, len, 64); 3067 add(buf, buf, 8); 3068 cmn(len, 128); 3069 br(Assembler::NE, CRC_less64); 3070 BIND(L_exit); 3071 mvnw(crc, crc); 3072 } 3073 3074 /** 3075 * @param crc register containing existing CRC (32-bit) 3076 * @param buf register pointing to input byte buffer (byte*) 3077 * @param len register containing number of bytes 3078 * @param table register that will contain address of CRC table 3079 * @param tmp scratch register 3080 */ 3081 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, 3082 Register table0, Register table1, Register table2, Register table3, 3083 Register tmp, Register tmp2, Register tmp3) { 3084 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit; 3085 unsigned long offset; 3086 3087 if (UseCRC32) { 3088 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3); 3089 return; 3090 } 3091 3092 mvnw(crc, crc); 3093 3094 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset); 3095 if (offset) add(table0, table0, offset); 3096 add(table1, table0, 1*256*sizeof(juint)); 3097 add(table2, table0, 2*256*sizeof(juint)); 3098 add(table3, table0, 3*256*sizeof(juint)); 3099 3100 if (UseNeon) { 3101 cmp(len, 64); 3102 br(Assembler::LT, L_by16); 3103 eor(v16, T16B, v16, v16); 3104 3105 Label L_fold; 3106 3107 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants 3108 3109 ld1(v0, v1, T2D, post(buf, 32)); 3110 ld1r(v4, T2D, post(tmp, 8)); 3111 ld1r(v5, T2D, post(tmp, 8)); 3112 ld1r(v6, T2D, post(tmp, 8)); 3113 ld1r(v7, T2D, post(tmp, 8)); 3114 mov(v16, T4S, 0, crc); 3115 3116 eor(v0, T16B, v0, v16); 3117 sub(len, len, 64); 3118 3119 BIND(L_fold); 3120 pmull(v22, T8H, v0, v5, T8B); 3121 pmull(v20, T8H, v0, v7, T8B); 3122 pmull(v23, T8H, v0, v4, T8B); 3123 pmull(v21, T8H, v0, v6, T8B); 3124 3125 pmull2(v18, T8H, v0, v5, T16B); 3126 pmull2(v16, T8H, v0, v7, T16B); 3127 pmull2(v19, T8H, v0, v4, T16B); 3128 pmull2(v17, T8H, v0, v6, T16B); 3129 3130 uzp1(v24, v20, v22, T8H); 3131 uzp2(v25, v20, v22, T8H); 3132 eor(v20, T16B, v24, v25); 3133 3134 uzp1(v26, v16, v18, T8H); 3135 uzp2(v27, v16, v18, T8H); 3136 eor(v16, T16B, v26, v27); 3137 3138 ushll2(v22, T4S, v20, T8H, 8); 3139 ushll(v20, T4S, v20, T4H, 8); 3140 3141 ushll2(v18, T4S, v16, T8H, 8); 3142 ushll(v16, T4S, v16, T4H, 8); 3143 3144 eor(v22, T16B, v23, v22); 3145 eor(v18, T16B, v19, v18); 3146 eor(v20, T16B, v21, v20); 3147 eor(v16, T16B, v17, v16); 3148 3149 uzp1(v17, v16, v20, T2D); 3150 uzp2(v21, v16, v20, T2D); 3151 eor(v17, T16B, v17, v21); 3152 3153 ushll2(v20, T2D, v17, T4S, 16); 3154 ushll(v16, T2D, v17, T2S, 16); 3155 3156 eor(v20, T16B, v20, v22); 3157 eor(v16, T16B, v16, v18); 3158 3159 uzp1(v17, v20, v16, T2D); 3160 uzp2(v21, v20, v16, T2D); 3161 eor(v28, T16B, v17, v21); 3162 3163 pmull(v22, T8H, v1, v5, T8B); 3164 pmull(v20, T8H, v1, v7, T8B); 3165 pmull(v23, T8H, v1, v4, T8B); 3166 pmull(v21, T8H, v1, v6, T8B); 3167 3168 pmull2(v18, T8H, v1, v5, T16B); 3169 pmull2(v16, T8H, v1, v7, T16B); 3170 pmull2(v19, T8H, v1, v4, T16B); 3171 pmull2(v17, T8H, v1, v6, T16B); 3172 3173 ld1(v0, v1, T2D, post(buf, 32)); 3174 3175 uzp1(v24, v20, v22, T8H); 3176 uzp2(v25, v20, v22, T8H); 3177 eor(v20, T16B, v24, v25); 3178 3179 uzp1(v26, v16, v18, T8H); 3180 uzp2(v27, v16, v18, T8H); 3181 eor(v16, T16B, v26, v27); 3182 3183 ushll2(v22, T4S, v20, T8H, 8); 3184 ushll(v20, T4S, v20, T4H, 8); 3185 3186 ushll2(v18, T4S, v16, T8H, 8); 3187 ushll(v16, T4S, v16, T4H, 8); 3188 3189 eor(v22, T16B, v23, v22); 3190 eor(v18, T16B, v19, v18); 3191 eor(v20, T16B, v21, v20); 3192 eor(v16, T16B, v17, v16); 3193 3194 uzp1(v17, v16, v20, T2D); 3195 uzp2(v21, v16, v20, T2D); 3196 eor(v16, T16B, v17, v21); 3197 3198 ushll2(v20, T2D, v16, T4S, 16); 3199 ushll(v16, T2D, v16, T2S, 16); 3200 3201 eor(v20, T16B, v22, v20); 3202 eor(v16, T16B, v16, v18); 3203 3204 uzp1(v17, v20, v16, T2D); 3205 uzp2(v21, v20, v16, T2D); 3206 eor(v20, T16B, v17, v21); 3207 3208 shl(v16, T2D, v28, 1); 3209 shl(v17, T2D, v20, 1); 3210 3211 eor(v0, T16B, v0, v16); 3212 eor(v1, T16B, v1, v17); 3213 3214 subs(len, len, 32); 3215 br(Assembler::GE, L_fold); 3216 3217 mov(crc, 0); 3218 mov(tmp, v0, T1D, 0); 3219 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3220 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3221 mov(tmp, v0, T1D, 1); 3222 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3223 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3224 mov(tmp, v1, T1D, 0); 3225 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3226 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3227 mov(tmp, v1, T1D, 1); 3228 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3229 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3230 3231 add(len, len, 32); 3232 } 3233 3234 BIND(L_by16); 3235 subs(len, len, 16); 3236 br(Assembler::GE, L_by16_loop); 3237 adds(len, len, 16-4); 3238 br(Assembler::GE, L_by4_loop); 3239 adds(len, len, 4); 3240 br(Assembler::GT, L_by1_loop); 3241 b(L_exit); 3242 3243 BIND(L_by4_loop); 3244 ldrw(tmp, Address(post(buf, 4))); 3245 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3); 3246 subs(len, len, 4); 3247 br(Assembler::GE, L_by4_loop); 3248 adds(len, len, 4); 3249 br(Assembler::LE, L_exit); 3250 BIND(L_by1_loop); 3251 subs(len, len, 1); 3252 ldrb(tmp, Address(post(buf, 1))); 3253 update_byte_crc32(crc, tmp, table0); 3254 br(Assembler::GT, L_by1_loop); 3255 b(L_exit); 3256 3257 align(CodeEntryAlignment); 3258 BIND(L_by16_loop); 3259 subs(len, len, 16); 3260 ldp(tmp, tmp3, Address(post(buf, 16))); 3261 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3262 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3263 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false); 3264 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true); 3265 br(Assembler::GE, L_by16_loop); 3266 adds(len, len, 16-4); 3267 br(Assembler::GE, L_by4_loop); 3268 adds(len, len, 4); 3269 br(Assembler::GT, L_by1_loop); 3270 BIND(L_exit); 3271 mvnw(crc, crc); 3272 } 3273 3274 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf, 3275 Register len, Register tmp0, Register tmp1, Register tmp2, 3276 Register tmp3) { 3277 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit; 3278 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3); 3279 3280 subs(len, len, 128); 3281 br(Assembler::GE, CRC_by64_pre); 3282 BIND(CRC_less64); 3283 adds(len, len, 128-32); 3284 br(Assembler::GE, CRC_by32_loop); 3285 BIND(CRC_less32); 3286 adds(len, len, 32-4); 3287 br(Assembler::GE, CRC_by4_loop); 3288 adds(len, len, 4); 3289 br(Assembler::GT, CRC_by1_loop); 3290 b(L_exit); 3291 3292 BIND(CRC_by32_loop); 3293 ldp(tmp0, tmp1, Address(post(buf, 16))); 3294 subs(len, len, 32); 3295 crc32cx(crc, crc, tmp0); 3296 ldr(tmp2, Address(post(buf, 8))); 3297 crc32cx(crc, crc, tmp1); 3298 ldr(tmp3, Address(post(buf, 8))); 3299 crc32cx(crc, crc, tmp2); 3300 crc32cx(crc, crc, tmp3); 3301 br(Assembler::GE, CRC_by32_loop); 3302 cmn(len, 32); 3303 br(Assembler::NE, CRC_less32); 3304 b(L_exit); 3305 3306 BIND(CRC_by4_loop); 3307 ldrw(tmp0, Address(post(buf, 4))); 3308 subs(len, len, 4); 3309 crc32cw(crc, crc, tmp0); 3310 br(Assembler::GE, CRC_by4_loop); 3311 adds(len, len, 4); 3312 br(Assembler::LE, L_exit); 3313 BIND(CRC_by1_loop); 3314 ldrb(tmp0, Address(post(buf, 1))); 3315 subs(len, len, 1); 3316 crc32cb(crc, crc, tmp0); 3317 br(Assembler::GT, CRC_by1_loop); 3318 b(L_exit); 3319 3320 BIND(CRC_by64_pre); 3321 sub(buf, buf, 8); 3322 ldp(tmp0, tmp1, Address(buf, 8)); 3323 crc32cx(crc, crc, tmp0); 3324 ldr(tmp2, Address(buf, 24)); 3325 crc32cx(crc, crc, tmp1); 3326 ldr(tmp3, Address(buf, 32)); 3327 crc32cx(crc, crc, tmp2); 3328 ldr(tmp0, Address(buf, 40)); 3329 crc32cx(crc, crc, tmp3); 3330 ldr(tmp1, Address(buf, 48)); 3331 crc32cx(crc, crc, tmp0); 3332 ldr(tmp2, Address(buf, 56)); 3333 crc32cx(crc, crc, tmp1); 3334 ldr(tmp3, Address(pre(buf, 64))); 3335 3336 b(CRC_by64_loop); 3337 3338 align(CodeEntryAlignment); 3339 BIND(CRC_by64_loop); 3340 subs(len, len, 64); 3341 crc32cx(crc, crc, tmp2); 3342 ldr(tmp0, Address(buf, 8)); 3343 crc32cx(crc, crc, tmp3); 3344 ldr(tmp1, Address(buf, 16)); 3345 crc32cx(crc, crc, tmp0); 3346 ldr(tmp2, Address(buf, 24)); 3347 crc32cx(crc, crc, tmp1); 3348 ldr(tmp3, Address(buf, 32)); 3349 crc32cx(crc, crc, tmp2); 3350 ldr(tmp0, Address(buf, 40)); 3351 crc32cx(crc, crc, tmp3); 3352 ldr(tmp1, Address(buf, 48)); 3353 crc32cx(crc, crc, tmp0); 3354 ldr(tmp2, Address(buf, 56)); 3355 crc32cx(crc, crc, tmp1); 3356 ldr(tmp3, Address(pre(buf, 64))); 3357 br(Assembler::GE, CRC_by64_loop); 3358 3359 // post-loop 3360 crc32cx(crc, crc, tmp2); 3361 crc32cx(crc, crc, tmp3); 3362 3363 sub(len, len, 64); 3364 add(buf, buf, 8); 3365 cmn(len, 128); 3366 br(Assembler::NE, CRC_less64); 3367 BIND(L_exit); 3368 } 3369 3370 /** 3371 * @param crc register containing existing CRC (32-bit) 3372 * @param buf register pointing to input byte buffer (byte*) 3373 * @param len register containing number of bytes 3374 * @param table register that will contain address of CRC table 3375 * @param tmp scratch register 3376 */ 3377 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len, 3378 Register table0, Register table1, Register table2, Register table3, 3379 Register tmp, Register tmp2, Register tmp3) { 3380 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3); 3381 } 3382 3383 3384 SkipIfEqual::SkipIfEqual( 3385 MacroAssembler* masm, const bool* flag_addr, bool value) { 3386 _masm = masm; 3387 unsigned long offset; 3388 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset); 3389 _masm->ldrb(rscratch1, Address(rscratch1, offset)); 3390 _masm->cbzw(rscratch1, _label); 3391 } 3392 3393 SkipIfEqual::~SkipIfEqual() { 3394 _masm->bind(_label); 3395 } 3396 3397 void MacroAssembler::addptr(const Address &dst, int32_t src) { 3398 Address adr; 3399 switch(dst.getMode()) { 3400 case Address::base_plus_offset: 3401 // This is the expected mode, although we allow all the other 3402 // forms below. 3403 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord); 3404 break; 3405 default: 3406 lea(rscratch2, dst); 3407 adr = Address(rscratch2); 3408 break; 3409 } 3410 ldr(rscratch1, adr); 3411 add(rscratch1, rscratch1, src); 3412 str(rscratch1, adr); 3413 } 3414 3415 void MacroAssembler::cmpptr(Register src1, Address src2) { 3416 unsigned long offset; 3417 adrp(rscratch1, src2, offset); 3418 ldr(rscratch1, Address(rscratch1, offset)); 3419 cmp(src1, rscratch1); 3420 } 3421 3422 void MacroAssembler::store_check(Register obj, Address dst) { 3423 store_check(obj); 3424 } 3425 3426 void MacroAssembler::store_check(Register obj) { 3427 // Does a store check for the oop in register obj. The content of 3428 // register obj is destroyed afterwards. 3429 3430 BarrierSet* bs = Universe::heap()->barrier_set(); 3431 assert(bs->kind() == BarrierSet::CardTableForRS || 3432 bs->kind() == BarrierSet::CardTableExtension, 3433 "Wrong barrier set kind"); 3434 3435 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 3436 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3437 3438 lsr(obj, obj, CardTableModRefBS::card_shift); 3439 3440 assert(CardTableModRefBS::dirty_card_val() == 0, "must be"); 3441 3442 load_byte_map_base(rscratch1); 3443 3444 if (UseCondCardMark) { 3445 Label L_already_dirty; 3446 membar(StoreLoad); 3447 ldrb(rscratch2, Address(obj, rscratch1)); 3448 cbz(rscratch2, L_already_dirty); 3449 strb(zr, Address(obj, rscratch1)); 3450 bind(L_already_dirty); 3451 } else { 3452 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) { 3453 membar(StoreStore); 3454 } 3455 strb(zr, Address(obj, rscratch1)); 3456 } 3457 } 3458 3459 void MacroAssembler::load_klass(Register dst, Register src) { 3460 if (UseCompressedClassPointers) { 3461 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3462 decode_klass_not_null(dst); 3463 } else { 3464 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3465 } 3466 } 3467 3468 // ((OopHandle)result).resolve(); 3469 void MacroAssembler::resolve_oop_handle(Register result) { 3470 // OopHandle::resolve is an indirection. 3471 ldr(result, Address(result, 0)); 3472 } 3473 3474 void MacroAssembler::load_mirror(Register dst, Register method) { 3475 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 3476 ldr(dst, Address(rmethod, Method::const_offset())); 3477 ldr(dst, Address(dst, ConstMethod::constants_offset())); 3478 ldr(dst, Address(dst, ConstantPool::pool_holder_offset_in_bytes())); 3479 ldr(dst, Address(dst, mirror_offset)); 3480 resolve_oop_handle(dst); 3481 } 3482 3483 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) { 3484 if (UseCompressedClassPointers) { 3485 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3486 if (Universe::narrow_klass_base() == NULL) { 3487 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift()); 3488 return; 3489 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3490 && Universe::narrow_klass_shift() == 0) { 3491 // Only the bottom 32 bits matter 3492 cmpw(trial_klass, tmp); 3493 return; 3494 } 3495 decode_klass_not_null(tmp); 3496 } else { 3497 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3498 } 3499 cmp(trial_klass, tmp); 3500 } 3501 3502 void MacroAssembler::load_prototype_header(Register dst, Register src) { 3503 load_klass(dst, src); 3504 ldr(dst, Address(dst, Klass::prototype_header_offset())); 3505 } 3506 3507 void MacroAssembler::store_klass(Register dst, Register src) { 3508 // FIXME: Should this be a store release? concurrent gcs assumes 3509 // klass length is valid if klass field is not null. 3510 if (UseCompressedClassPointers) { 3511 encode_klass_not_null(src); 3512 strw(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3513 } else { 3514 str(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3515 } 3516 } 3517 3518 void MacroAssembler::store_klass_gap(Register dst, Register src) { 3519 if (UseCompressedClassPointers) { 3520 // Store to klass gap in destination 3521 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes())); 3522 } 3523 } 3524 3525 // Algorithm must match oop.inline.hpp encode_heap_oop. 3526 void MacroAssembler::encode_heap_oop(Register d, Register s) { 3527 #ifdef ASSERT 3528 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 3529 #endif 3530 verify_oop(s, "broken oop in encode_heap_oop"); 3531 if (Universe::narrow_oop_base() == NULL) { 3532 if (Universe::narrow_oop_shift() != 0) { 3533 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3534 lsr(d, s, LogMinObjAlignmentInBytes); 3535 } else { 3536 mov(d, s); 3537 } 3538 } else { 3539 subs(d, s, rheapbase); 3540 csel(d, d, zr, Assembler::HS); 3541 lsr(d, d, LogMinObjAlignmentInBytes); 3542 3543 /* Old algorithm: is this any worse? 3544 Label nonnull; 3545 cbnz(r, nonnull); 3546 sub(r, r, rheapbase); 3547 bind(nonnull); 3548 lsr(r, r, LogMinObjAlignmentInBytes); 3549 */ 3550 } 3551 } 3552 3553 void MacroAssembler::encode_heap_oop_not_null(Register r) { 3554 #ifdef ASSERT 3555 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 3556 if (CheckCompressedOops) { 3557 Label ok; 3558 cbnz(r, ok); 3559 stop("null oop passed to encode_heap_oop_not_null"); 3560 bind(ok); 3561 } 3562 #endif 3563 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 3564 if (Universe::narrow_oop_base() != NULL) { 3565 sub(r, r, rheapbase); 3566 } 3567 if (Universe::narrow_oop_shift() != 0) { 3568 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3569 lsr(r, r, LogMinObjAlignmentInBytes); 3570 } 3571 } 3572 3573 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 3574 #ifdef ASSERT 3575 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 3576 if (CheckCompressedOops) { 3577 Label ok; 3578 cbnz(src, ok); 3579 stop("null oop passed to encode_heap_oop_not_null2"); 3580 bind(ok); 3581 } 3582 #endif 3583 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 3584 3585 Register data = src; 3586 if (Universe::narrow_oop_base() != NULL) { 3587 sub(dst, src, rheapbase); 3588 data = dst; 3589 } 3590 if (Universe::narrow_oop_shift() != 0) { 3591 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3592 lsr(dst, data, LogMinObjAlignmentInBytes); 3593 data = dst; 3594 } 3595 if (data == src) 3596 mov(dst, src); 3597 } 3598 3599 void MacroAssembler::decode_heap_oop(Register d, Register s) { 3600 #ifdef ASSERT 3601 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 3602 #endif 3603 if (Universe::narrow_oop_base() == NULL) { 3604 if (Universe::narrow_oop_shift() != 0 || d != s) { 3605 lsl(d, s, Universe::narrow_oop_shift()); 3606 } 3607 } else { 3608 Label done; 3609 if (d != s) 3610 mov(d, s); 3611 cbz(s, done); 3612 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes); 3613 bind(done); 3614 } 3615 verify_oop(d, "broken oop in decode_heap_oop"); 3616 } 3617 3618 void MacroAssembler::decode_heap_oop_not_null(Register r) { 3619 assert (UseCompressedOops, "should only be used for compressed headers"); 3620 assert (Universe::heap() != NULL, "java heap should be initialized"); 3621 // Cannot assert, unverified entry point counts instructions (see .ad file) 3622 // vtableStubs also counts instructions in pd_code_size_limit. 3623 // Also do not verify_oop as this is called by verify_oop. 3624 if (Universe::narrow_oop_shift() != 0) { 3625 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3626 if (Universe::narrow_oop_base() != NULL) { 3627 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3628 } else { 3629 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3630 } 3631 } else { 3632 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3633 } 3634 } 3635 3636 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 3637 assert (UseCompressedOops, "should only be used for compressed headers"); 3638 assert (Universe::heap() != NULL, "java heap should be initialized"); 3639 // Cannot assert, unverified entry point counts instructions (see .ad file) 3640 // vtableStubs also counts instructions in pd_code_size_limit. 3641 // Also do not verify_oop as this is called by verify_oop. 3642 if (Universe::narrow_oop_shift() != 0) { 3643 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3644 if (Universe::narrow_oop_base() != NULL) { 3645 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3646 } else { 3647 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3648 } 3649 } else { 3650 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3651 if (dst != src) { 3652 mov(dst, src); 3653 } 3654 } 3655 } 3656 3657 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 3658 if (Universe::narrow_klass_base() == NULL) { 3659 if (Universe::narrow_klass_shift() != 0) { 3660 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3661 lsr(dst, src, LogKlassAlignmentInBytes); 3662 } else { 3663 if (dst != src) mov(dst, src); 3664 } 3665 return; 3666 } 3667 3668 if (use_XOR_for_compressed_class_base) { 3669 if (Universe::narrow_klass_shift() != 0) { 3670 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3671 lsr(dst, dst, LogKlassAlignmentInBytes); 3672 } else { 3673 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3674 } 3675 return; 3676 } 3677 3678 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3679 && Universe::narrow_klass_shift() == 0) { 3680 movw(dst, src); 3681 return; 3682 } 3683 3684 #ifdef ASSERT 3685 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?"); 3686 #endif 3687 3688 Register rbase = dst; 3689 if (dst == src) rbase = rheapbase; 3690 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3691 sub(dst, src, rbase); 3692 if (Universe::narrow_klass_shift() != 0) { 3693 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3694 lsr(dst, dst, LogKlassAlignmentInBytes); 3695 } 3696 if (dst == src) reinit_heapbase(); 3697 } 3698 3699 void MacroAssembler::encode_klass_not_null(Register r) { 3700 encode_klass_not_null(r, r); 3701 } 3702 3703 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 3704 Register rbase = dst; 3705 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3706 3707 if (Universe::narrow_klass_base() == NULL) { 3708 if (Universe::narrow_klass_shift() != 0) { 3709 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3710 lsl(dst, src, LogKlassAlignmentInBytes); 3711 } else { 3712 if (dst != src) mov(dst, src); 3713 } 3714 return; 3715 } 3716 3717 if (use_XOR_for_compressed_class_base) { 3718 if (Universe::narrow_klass_shift() != 0) { 3719 lsl(dst, src, LogKlassAlignmentInBytes); 3720 eor(dst, dst, (uint64_t)Universe::narrow_klass_base()); 3721 } else { 3722 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3723 } 3724 return; 3725 } 3726 3727 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3728 && Universe::narrow_klass_shift() == 0) { 3729 if (dst != src) 3730 movw(dst, src); 3731 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32); 3732 return; 3733 } 3734 3735 // Cannot assert, unverified entry point counts instructions (see .ad file) 3736 // vtableStubs also counts instructions in pd_code_size_limit. 3737 // Also do not verify_oop as this is called by verify_oop. 3738 if (dst == src) rbase = rheapbase; 3739 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3740 if (Universe::narrow_klass_shift() != 0) { 3741 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3742 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes); 3743 } else { 3744 add(dst, rbase, src); 3745 } 3746 if (dst == src) reinit_heapbase(); 3747 } 3748 3749 void MacroAssembler::decode_klass_not_null(Register r) { 3750 decode_klass_not_null(r, r); 3751 } 3752 3753 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 3754 #ifdef ASSERT 3755 { 3756 ThreadInVMfromUnknown tiv; 3757 assert (UseCompressedOops, "should only be used for compressed oops"); 3758 assert (Universe::heap() != NULL, "java heap should be initialized"); 3759 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3760 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 3761 } 3762 #endif 3763 int oop_index = oop_recorder()->find_index(obj); 3764 InstructionMark im(this); 3765 RelocationHolder rspec = oop_Relocation::spec(oop_index); 3766 code_section()->relocate(inst_mark(), rspec); 3767 movz(dst, 0xDEAD, 16); 3768 movk(dst, 0xBEEF); 3769 } 3770 3771 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 3772 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3773 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3774 int index = oop_recorder()->find_index(k); 3775 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop"); 3776 3777 InstructionMark im(this); 3778 RelocationHolder rspec = metadata_Relocation::spec(index); 3779 code_section()->relocate(inst_mark(), rspec); 3780 narrowKlass nk = Klass::encode_klass(k); 3781 movz(dst, (nk >> 16), 16); 3782 movk(dst, nk & 0xffff); 3783 } 3784 3785 void MacroAssembler::load_heap_oop(Register dst, Address src) 3786 { 3787 if (UseCompressedOops) { 3788 ldrw(dst, src); 3789 decode_heap_oop(dst); 3790 } else { 3791 ldr(dst, src); 3792 } 3793 } 3794 3795 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) 3796 { 3797 if (UseCompressedOops) { 3798 ldrw(dst, src); 3799 decode_heap_oop_not_null(dst); 3800 } else { 3801 ldr(dst, src); 3802 } 3803 } 3804 3805 void MacroAssembler::store_heap_oop(Address dst, Register src) { 3806 if (UseCompressedOops) { 3807 assert(!dst.uses(src), "not enough registers"); 3808 encode_heap_oop(src); 3809 strw(src, dst); 3810 } else 3811 str(src, dst); 3812 } 3813 3814 // Used for storing NULLs. 3815 void MacroAssembler::store_heap_oop_null(Address dst) { 3816 if (UseCompressedOops) { 3817 strw(zr, dst); 3818 } else 3819 str(zr, dst); 3820 } 3821 3822 #if INCLUDE_ALL_GCS 3823 /* 3824 * g1_write_barrier_pre -- G1GC pre-write barrier for store of new_val at 3825 * store_addr. 3826 * 3827 * Allocates rscratch1 3828 */ 3829 void MacroAssembler::g1_write_barrier_pre(Register obj, 3830 Register pre_val, 3831 Register thread, 3832 Register tmp, 3833 bool tosca_live, 3834 bool expand_call) { 3835 // If expand_call is true then we expand the call_VM_leaf macro 3836 // directly to skip generating the check by 3837 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 3838 3839 assert(thread == rthread, "must be"); 3840 3841 Label done; 3842 Label runtime; 3843 3844 assert_different_registers(obj, pre_val, tmp, rscratch1); 3845 assert(pre_val != noreg && tmp != noreg, "expecting a register"); 3846 3847 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3848 SATBMarkQueue::byte_offset_of_active())); 3849 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3850 SATBMarkQueue::byte_offset_of_index())); 3851 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3852 SATBMarkQueue::byte_offset_of_buf())); 3853 3854 3855 // Is marking active? 3856 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 3857 ldrw(tmp, in_progress); 3858 } else { 3859 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 3860 ldrb(tmp, in_progress); 3861 } 3862 cbzw(tmp, done); 3863 3864 // Do we need to load the previous value? 3865 if (obj != noreg) { 3866 load_heap_oop(pre_val, Address(obj, 0)); 3867 } 3868 3869 // Is the previous value null? 3870 cbz(pre_val, done); 3871 3872 // Can we store original value in the thread's buffer? 3873 // Is index == 0? 3874 // (The index field is typed as size_t.) 3875 3876 ldr(tmp, index); // tmp := *index_adr 3877 cbz(tmp, runtime); // tmp == 0? 3878 // If yes, goto runtime 3879 3880 sub(tmp, tmp, wordSize); // tmp := tmp - wordSize 3881 str(tmp, index); // *index_adr := tmp 3882 ldr(rscratch1, buffer); 3883 add(tmp, tmp, rscratch1); // tmp := tmp + *buffer_adr 3884 3885 // Record the previous value 3886 str(pre_val, Address(tmp, 0)); 3887 b(done); 3888 3889 bind(runtime); 3890 // save the live input values 3891 push(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3892 3893 // Calling the runtime using the regular call_VM_leaf mechanism generates 3894 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 3895 // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL. 3896 // 3897 // If we care generating the pre-barrier without a frame (e.g. in the 3898 // intrinsified Reference.get() routine) then ebp might be pointing to 3899 // the caller frame and so this check will most likely fail at runtime. 3900 // 3901 // Expanding the call directly bypasses the generation of the check. 3902 // So when we do not have have a full interpreter frame on the stack 3903 // expand_call should be passed true. 3904 3905 if (expand_call) { 3906 assert(pre_val != c_rarg1, "smashed arg"); 3907 pass_arg1(this, thread); 3908 pass_arg0(this, pre_val); 3909 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 3910 } else { 3911 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 3912 } 3913 3914 pop(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3915 3916 bind(done); 3917 } 3918 3919 /* 3920 * g1_write_barrier_post -- G1GC post-write barrier for store of new_val at 3921 * store_addr 3922 * 3923 * Allocates rscratch1 3924 */ 3925 void MacroAssembler::g1_write_barrier_post(Register store_addr, 3926 Register new_val, 3927 Register thread, 3928 Register tmp, 3929 Register tmp2) { 3930 assert(thread == rthread, "must be"); 3931 assert_different_registers(store_addr, new_val, thread, tmp, tmp2, 3932 rscratch1); 3933 assert(store_addr != noreg && new_val != noreg && tmp != noreg 3934 && tmp2 != noreg, "expecting a register"); 3935 3936 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3937 DirtyCardQueue::byte_offset_of_index())); 3938 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3939 DirtyCardQueue::byte_offset_of_buf())); 3940 3941 BarrierSet* bs = Universe::heap()->barrier_set(); 3942 CardTableModRefBS* ct = (CardTableModRefBS*)bs; 3943 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3944 3945 Label done; 3946 Label runtime; 3947 3948 // Does store cross heap regions? 3949 3950 eor(tmp, store_addr, new_val); 3951 lsr(tmp, tmp, HeapRegion::LogOfHRGrainBytes); 3952 cbz(tmp, done); 3953 3954 // crosses regions, storing NULL? 3955 3956 cbz(new_val, done); 3957 3958 // storing region crossing non-NULL, is card already dirty? 3959 3960 ExternalAddress cardtable((address) ct->byte_map_base); 3961 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3962 const Register card_addr = tmp; 3963 3964 lsr(card_addr, store_addr, CardTableModRefBS::card_shift); 3965 3966 // get the address of the card 3967 load_byte_map_base(tmp2); 3968 add(card_addr, card_addr, tmp2); 3969 ldrb(tmp2, Address(card_addr)); 3970 cmpw(tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val()); 3971 br(Assembler::EQ, done); 3972 3973 assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0"); 3974 3975 membar(Assembler::StoreLoad); 3976 3977 ldrb(tmp2, Address(card_addr)); 3978 cbzw(tmp2, done); 3979 3980 // storing a region crossing, non-NULL oop, card is clean. 3981 // dirty card and log. 3982 3983 strb(zr, Address(card_addr)); 3984 3985 ldr(rscratch1, queue_index); 3986 cbz(rscratch1, runtime); 3987 sub(rscratch1, rscratch1, wordSize); 3988 str(rscratch1, queue_index); 3989 3990 ldr(tmp2, buffer); 3991 str(card_addr, Address(tmp2, rscratch1)); 3992 b(done); 3993 3994 bind(runtime); 3995 // save the live input values 3996 push(store_addr->bit(true) | new_val->bit(true), sp); 3997 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 3998 pop(store_addr->bit(true) | new_val->bit(true), sp); 3999 4000 bind(done); 4001 } 4002 4003 #endif // INCLUDE_ALL_GCS 4004 4005 Address MacroAssembler::allocate_metadata_address(Metadata* obj) { 4006 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); 4007 int index = oop_recorder()->allocate_metadata_index(obj); 4008 RelocationHolder rspec = metadata_Relocation::spec(index); 4009 return Address((address)obj, rspec); 4010 } 4011 4012 // Move an oop into a register. immediate is true if we want 4013 // immediate instrcutions, i.e. we are not going to patch this 4014 // instruction while the code is being executed by another thread. In 4015 // that case we can use move immediates rather than the constant pool. 4016 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) { 4017 int oop_index; 4018 if (obj == NULL) { 4019 oop_index = oop_recorder()->allocate_oop_index(obj); 4020 } else { 4021 #ifdef ASSERT 4022 { 4023 ThreadInVMfromUnknown tiv; 4024 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 4025 } 4026 #endif 4027 oop_index = oop_recorder()->find_index(obj); 4028 } 4029 RelocationHolder rspec = oop_Relocation::spec(oop_index); 4030 if (! immediate) { 4031 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address 4032 ldr_constant(dst, Address(dummy, rspec)); 4033 } else 4034 mov(dst, Address((address)obj, rspec)); 4035 } 4036 4037 // Move a metadata address into a register. 4038 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 4039 int oop_index; 4040 if (obj == NULL) { 4041 oop_index = oop_recorder()->allocate_metadata_index(obj); 4042 } else { 4043 oop_index = oop_recorder()->find_index(obj); 4044 } 4045 RelocationHolder rspec = metadata_Relocation::spec(oop_index); 4046 mov(dst, Address((address)obj, rspec)); 4047 } 4048 4049 Address MacroAssembler::constant_oop_address(jobject obj) { 4050 #ifdef ASSERT 4051 { 4052 ThreadInVMfromUnknown tiv; 4053 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4054 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); 4055 } 4056 #endif 4057 int oop_index = oop_recorder()->find_index(obj); 4058 return Address((address)obj, oop_Relocation::spec(oop_index)); 4059 } 4060 4061 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 4062 void MacroAssembler::tlab_allocate(Register obj, 4063 Register var_size_in_bytes, 4064 int con_size_in_bytes, 4065 Register t1, 4066 Register t2, 4067 Label& slow_case) { 4068 assert_different_registers(obj, t2); 4069 assert_different_registers(obj, var_size_in_bytes); 4070 Register end = t2; 4071 4072 // verify_tlab(); 4073 4074 ldr(obj, Address(rthread, JavaThread::tlab_top_offset())); 4075 if (var_size_in_bytes == noreg) { 4076 lea(end, Address(obj, con_size_in_bytes)); 4077 } else { 4078 lea(end, Address(obj, var_size_in_bytes)); 4079 } 4080 ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset())); 4081 cmp(end, rscratch1); 4082 br(Assembler::HI, slow_case); 4083 4084 // update the tlab top pointer 4085 str(end, Address(rthread, JavaThread::tlab_top_offset())); 4086 4087 // recover var_size_in_bytes if necessary 4088 if (var_size_in_bytes == end) { 4089 sub(var_size_in_bytes, var_size_in_bytes, obj); 4090 } 4091 // verify_tlab(); 4092 } 4093 4094 // Preserves r19, and r3. 4095 Register MacroAssembler::tlab_refill(Label& retry, 4096 Label& try_eden, 4097 Label& slow_case) { 4098 Register top = r0; 4099 Register t1 = r2; 4100 Register t2 = r4; 4101 assert_different_registers(top, rthread, t1, t2, /* preserve: */ r19, r3); 4102 Label do_refill, discard_tlab; 4103 4104 if (!Universe::heap()->supports_inline_contig_alloc()) { 4105 // No allocation in the shared eden. 4106 b(slow_case); 4107 } 4108 4109 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 4110 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 4111 4112 // calculate amount of free space 4113 sub(t1, t1, top); 4114 lsr(t1, t1, LogHeapWordSize); 4115 4116 // Retain tlab and allocate object in shared space if 4117 // the amount free in the tlab is too large to discard. 4118 4119 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 4120 cmp(t1, rscratch1); 4121 br(Assembler::LE, discard_tlab); 4122 4123 // Retain 4124 // ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 4125 mov(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 4126 add(rscratch1, rscratch1, t2); 4127 str(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 4128 4129 if (TLABStats) { 4130 // increment number of slow_allocations 4131 addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())), 4132 1, rscratch1); 4133 } 4134 b(try_eden); 4135 4136 bind(discard_tlab); 4137 if (TLABStats) { 4138 // increment number of refills 4139 addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1, 4140 rscratch1); 4141 // accumulate wastage -- t1 is amount free in tlab 4142 addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1, 4143 rscratch1); 4144 } 4145 4146 // if tlab is currently allocated (top or end != null) then 4147 // fill [top, end + alignment_reserve) with array object 4148 cbz(top, do_refill); 4149 4150 // set up the mark word 4151 mov(rscratch1, (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 4152 str(rscratch1, Address(top, oopDesc::mark_offset_in_bytes())); 4153 // set the length to the remaining space 4154 sub(t1, t1, typeArrayOopDesc::header_size(T_INT)); 4155 add(t1, t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 4156 lsl(t1, t1, log2_intptr(HeapWordSize/sizeof(jint))); 4157 strw(t1, Address(top, arrayOopDesc::length_offset_in_bytes())); 4158 // set klass to intArrayKlass 4159 { 4160 unsigned long offset; 4161 // dubious reloc why not an oop reloc? 4162 adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()), 4163 offset); 4164 ldr(t1, Address(rscratch1, offset)); 4165 } 4166 // store klass last. concurrent gcs assumes klass length is valid if 4167 // klass field is not null. 4168 store_klass(top, t1); 4169 4170 mov(t1, top); 4171 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 4172 sub(t1, t1, rscratch1); 4173 incr_allocated_bytes(rthread, t1, 0, rscratch1); 4174 4175 // refill the tlab with an eden allocation 4176 bind(do_refill); 4177 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 4178 lsl(t1, t1, LogHeapWordSize); 4179 // allocate new tlab, address returned in top 4180 eden_allocate(top, t1, 0, t2, slow_case); 4181 4182 // Check that t1 was preserved in eden_allocate. 4183 #ifdef ASSERT 4184 if (UseTLAB) { 4185 Label ok; 4186 Register tsize = r4; 4187 assert_different_registers(tsize, rthread, t1); 4188 str(tsize, Address(pre(sp, -16))); 4189 ldr(tsize, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 4190 lsl(tsize, tsize, LogHeapWordSize); 4191 cmp(t1, tsize); 4192 br(Assembler::EQ, ok); 4193 STOP("assert(t1 != tlab size)"); 4194 should_not_reach_here(); 4195 4196 bind(ok); 4197 ldr(tsize, Address(post(sp, 16))); 4198 } 4199 #endif 4200 str(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 4201 str(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 4202 add(top, top, t1); 4203 sub(top, top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 4204 str(top, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 4205 4206 if (ZeroTLAB) { 4207 // This is a fast TLAB refill, therefore the GC is not notified of it. 4208 // So compiled code must fill the new TLAB with zeroes. 4209 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 4210 zero_memory(top,t1,t2); 4211 } 4212 4213 verify_tlab(); 4214 b(retry); 4215 4216 return rthread; // for use by caller 4217 } 4218 4219 // Zero words; len is in bytes 4220 // Destroys all registers except addr 4221 // len must be a nonzero multiple of wordSize 4222 void MacroAssembler::zero_memory(Register addr, Register len, Register t1) { 4223 assert_different_registers(addr, len, t1, rscratch1, rscratch2); 4224 4225 #ifdef ASSERT 4226 { Label L; 4227 tst(len, BytesPerWord - 1); 4228 br(Assembler::EQ, L); 4229 stop("len is not a multiple of BytesPerWord"); 4230 bind(L); 4231 } 4232 #endif 4233 4234 #ifndef PRODUCT 4235 block_comment("zero memory"); 4236 #endif 4237 4238 Label loop; 4239 Label entry; 4240 4241 // Algorithm: 4242 // 4243 // scratch1 = cnt & 7; 4244 // cnt -= scratch1; 4245 // p += scratch1; 4246 // switch (scratch1) { 4247 // do { 4248 // cnt -= 8; 4249 // p[-8] = 0; 4250 // case 7: 4251 // p[-7] = 0; 4252 // case 6: 4253 // p[-6] = 0; 4254 // // ... 4255 // case 1: 4256 // p[-1] = 0; 4257 // case 0: 4258 // p += 8; 4259 // } while (cnt); 4260 // } 4261 4262 const int unroll = 8; // Number of str(zr) instructions we'll unroll 4263 4264 lsr(len, len, LogBytesPerWord); 4265 andr(rscratch1, len, unroll - 1); // tmp1 = cnt % unroll 4266 sub(len, len, rscratch1); // cnt -= unroll 4267 // t1 always points to the end of the region we're about to zero 4268 add(t1, addr, rscratch1, Assembler::LSL, LogBytesPerWord); 4269 adr(rscratch2, entry); 4270 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 2); 4271 br(rscratch2); 4272 bind(loop); 4273 sub(len, len, unroll); 4274 for (int i = -unroll; i < 0; i++) 4275 str(zr, Address(t1, i * wordSize)); 4276 bind(entry); 4277 add(t1, t1, unroll * wordSize); 4278 cbnz(len, loop); 4279 } 4280 4281 // Defines obj, preserves var_size_in_bytes 4282 void MacroAssembler::eden_allocate(Register obj, 4283 Register var_size_in_bytes, 4284 int con_size_in_bytes, 4285 Register t1, 4286 Label& slow_case) { 4287 assert_different_registers(obj, var_size_in_bytes, t1); 4288 if (!Universe::heap()->supports_inline_contig_alloc()) { 4289 b(slow_case); 4290 } else { 4291 Register end = t1; 4292 Register heap_end = rscratch2; 4293 Label retry; 4294 bind(retry); 4295 { 4296 unsigned long offset; 4297 adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset); 4298 ldr(heap_end, Address(rscratch1, offset)); 4299 } 4300 4301 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 4302 4303 // Get the current top of the heap 4304 { 4305 unsigned long offset; 4306 adrp(rscratch1, heap_top, offset); 4307 // Use add() here after ARDP, rather than lea(). 4308 // lea() does not generate anything if its offset is zero. 4309 // However, relocs expect to find either an ADD or a load/store 4310 // insn after an ADRP. add() always generates an ADD insn, even 4311 // for add(Rn, Rn, 0). 4312 add(rscratch1, rscratch1, offset); 4313 ldaxr(obj, rscratch1); 4314 } 4315 4316 // Adjust it my the size of our new object 4317 if (var_size_in_bytes == noreg) { 4318 lea(end, Address(obj, con_size_in_bytes)); 4319 } else { 4320 lea(end, Address(obj, var_size_in_bytes)); 4321 } 4322 4323 // if end < obj then we wrapped around high memory 4324 cmp(end, obj); 4325 br(Assembler::LO, slow_case); 4326 4327 cmp(end, heap_end); 4328 br(Assembler::HI, slow_case); 4329 4330 // If heap_top hasn't been changed by some other thread, update it. 4331 stlxr(rscratch2, end, rscratch1); 4332 cbnzw(rscratch2, retry); 4333 } 4334 } 4335 4336 void MacroAssembler::verify_tlab() { 4337 #ifdef ASSERT 4338 if (UseTLAB && VerifyOops) { 4339 Label next, ok; 4340 4341 stp(rscratch2, rscratch1, Address(pre(sp, -16))); 4342 4343 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 4344 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 4345 cmp(rscratch2, rscratch1); 4346 br(Assembler::HS, next); 4347 STOP("assert(top >= start)"); 4348 should_not_reach_here(); 4349 4350 bind(next); 4351 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 4352 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 4353 cmp(rscratch2, rscratch1); 4354 br(Assembler::HS, ok); 4355 STOP("assert(top <= end)"); 4356 should_not_reach_here(); 4357 4358 bind(ok); 4359 ldp(rscratch2, rscratch1, Address(post(sp, 16))); 4360 } 4361 #endif 4362 } 4363 4364 // Writes to stack successive pages until offset reached to check for 4365 // stack overflow + shadow pages. This clobbers tmp. 4366 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 4367 assert_different_registers(tmp, size, rscratch1); 4368 mov(tmp, sp); 4369 // Bang stack for total size given plus shadow page size. 4370 // Bang one page at a time because large size can bang beyond yellow and 4371 // red zones. 4372 Label loop; 4373 mov(rscratch1, os::vm_page_size()); 4374 bind(loop); 4375 lea(tmp, Address(tmp, -os::vm_page_size())); 4376 subsw(size, size, rscratch1); 4377 str(size, Address(tmp)); 4378 br(Assembler::GT, loop); 4379 4380 // Bang down shadow pages too. 4381 // At this point, (tmp-0) is the last address touched, so don't 4382 // touch it again. (It was touched as (tmp-pagesize) but then tmp 4383 // was post-decremented.) Skip this address by starting at i=1, and 4384 // touch a few more pages below. N.B. It is important to touch all 4385 // the way down to and including i=StackShadowPages. 4386 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) { 4387 // this could be any sized move but this is can be a debugging crumb 4388 // so the bigger the better. 4389 lea(tmp, Address(tmp, -os::vm_page_size())); 4390 str(size, Address(tmp)); 4391 } 4392 } 4393 4394 4395 // Move the address of the polling page into dest. 4396 void MacroAssembler::get_polling_page(Register dest, address page, relocInfo::relocType rtype) { 4397 if (SafepointMechanism::uses_thread_local_poll()) { 4398 ldr(dest, Address(rthread, Thread::polling_page_offset())); 4399 } else { 4400 unsigned long off; 4401 adrp(dest, Address(page, rtype), off); 4402 assert(off == 0, "polling page must be page aligned"); 4403 } 4404 } 4405 4406 // Move the address of the polling page into r, then read the polling 4407 // page. 4408 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) { 4409 get_polling_page(r, page, rtype); 4410 return read_polling_page(r, rtype); 4411 } 4412 4413 // Read the polling page. The address of the polling page must 4414 // already be in r. 4415 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) { 4416 InstructionMark im(this); 4417 code_section()->relocate(inst_mark(), rtype); 4418 ldrw(zr, Address(r, 0)); 4419 return inst_mark(); 4420 } 4421 4422 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) { 4423 relocInfo::relocType rtype = dest.rspec().reloc()->type(); 4424 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12; 4425 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12; 4426 unsigned long dest_page = (unsigned long)dest.target() >> 12; 4427 long offset_low = dest_page - low_page; 4428 long offset_high = dest_page - high_page; 4429 4430 assert(is_valid_AArch64_address(dest.target()), "bad address"); 4431 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address"); 4432 4433 InstructionMark im(this); 4434 code_section()->relocate(inst_mark(), dest.rspec()); 4435 // 8143067: Ensure that the adrp can reach the dest from anywhere within 4436 // the code cache so that if it is relocated we know it will still reach 4437 if (offset_high >= -(1<<20) && offset_low < (1<<20)) { 4438 _adrp(reg1, dest.target()); 4439 } else { 4440 unsigned long target = (unsigned long)dest.target(); 4441 unsigned long adrp_target 4442 = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL); 4443 4444 _adrp(reg1, (address)adrp_target); 4445 movk(reg1, target >> 32, 32); 4446 } 4447 byte_offset = (unsigned long)dest.target() & 0xfff; 4448 } 4449 4450 void MacroAssembler::load_byte_map_base(Register reg) { 4451 jbyte *byte_map_base = 4452 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base; 4453 4454 if (is_valid_AArch64_address((address)byte_map_base)) { 4455 // Strictly speaking the byte_map_base isn't an address at all, 4456 // and it might even be negative. 4457 unsigned long offset; 4458 adrp(reg, ExternalAddress((address)byte_map_base), offset); 4459 // We expect offset to be zero with most collectors. 4460 if (offset != 0) { 4461 add(reg, reg, offset); 4462 } 4463 } else { 4464 mov(reg, (uint64_t)byte_map_base); 4465 } 4466 } 4467 4468 void MacroAssembler::build_frame(int framesize) { 4469 assert(framesize > 0, "framesize must be > 0"); 4470 if (framesize < ((1 << 9) + 2 * wordSize)) { 4471 sub(sp, sp, framesize); 4472 stp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4473 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize); 4474 } else { 4475 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 4476 if (PreserveFramePointer) mov(rfp, sp); 4477 if (framesize < ((1 << 12) + 2 * wordSize)) 4478 sub(sp, sp, framesize - 2 * wordSize); 4479 else { 4480 mov(rscratch1, framesize - 2 * wordSize); 4481 sub(sp, sp, rscratch1); 4482 } 4483 } 4484 } 4485 4486 void MacroAssembler::remove_frame(int framesize) { 4487 assert(framesize > 0, "framesize must be > 0"); 4488 if (framesize < ((1 << 9) + 2 * wordSize)) { 4489 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4490 add(sp, sp, framesize); 4491 } else { 4492 if (framesize < ((1 << 12) + 2 * wordSize)) 4493 add(sp, sp, framesize - 2 * wordSize); 4494 else { 4495 mov(rscratch1, framesize - 2 * wordSize); 4496 add(sp, sp, rscratch1); 4497 } 4498 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 4499 } 4500 } 4501 4502 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr); 4503 4504 // Search for str1 in str2 and return index or -1 4505 void MacroAssembler::string_indexof(Register str2, Register str1, 4506 Register cnt2, Register cnt1, 4507 Register tmp1, Register tmp2, 4508 Register tmp3, Register tmp4, 4509 int icnt1, Register result, int ae) { 4510 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH; 4511 4512 Register ch1 = rscratch1; 4513 Register ch2 = rscratch2; 4514 Register cnt1tmp = tmp1; 4515 Register cnt2tmp = tmp2; 4516 Register cnt1_neg = cnt1; 4517 Register cnt2_neg = cnt2; 4518 Register result_tmp = tmp4; 4519 4520 bool isL = ae == StrIntrinsicNode::LL; 4521 4522 bool str1_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL; 4523 bool str2_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::LU; 4524 int str1_chr_shift = str1_isL ? 0:1; 4525 int str2_chr_shift = str2_isL ? 0:1; 4526 int str1_chr_size = str1_isL ? 1:2; 4527 int str2_chr_size = str2_isL ? 1:2; 4528 chr_insn str1_load_1chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb : 4529 (chr_insn)&MacroAssembler::ldrh; 4530 chr_insn str2_load_1chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb : 4531 (chr_insn)&MacroAssembler::ldrh; 4532 chr_insn load_2chr = isL ? (chr_insn)&MacroAssembler::ldrh : (chr_insn)&MacroAssembler::ldrw; 4533 chr_insn load_4chr = isL ? (chr_insn)&MacroAssembler::ldrw : (chr_insn)&MacroAssembler::ldr; 4534 4535 // Note, inline_string_indexOf() generates checks: 4536 // if (substr.count > string.count) return -1; 4537 // if (substr.count == 0) return 0; 4538 4539 // We have two strings, a source string in str2, cnt2 and a pattern string 4540 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1. 4541 4542 // For larger pattern and source we use a simplified Boyer Moore algorithm. 4543 // With a small pattern and source we use linear scan. 4544 4545 if (icnt1 == -1) { 4546 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256 4547 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use 4548 br(LO, LINEARSEARCH); // a byte array. 4549 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM 4550 br(HS, LINEARSEARCH); 4551 } 4552 4553 // The Boyer Moore alogorithm is based on the description here:- 4554 // 4555 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm 4556 // 4557 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule 4558 // and the 'Good Suffix' rule. 4559 // 4560 // These rules are essentially heuristics for how far we can shift the 4561 // pattern along the search string. 4562 // 4563 // The implementation here uses the 'Bad Character' rule only because of the 4564 // complexity of initialisation for the 'Good Suffix' rule. 4565 // 4566 // This is also known as the Boyer-Moore-Horspool algorithm:- 4567 // 4568 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm 4569 // 4570 // #define ASIZE 128 4571 // 4572 // int bm(unsigned char *x, int m, unsigned char *y, int n) { 4573 // int i, j; 4574 // unsigned c; 4575 // unsigned char bc[ASIZE]; 4576 // 4577 // /* Preprocessing */ 4578 // for (i = 0; i < ASIZE; ++i) 4579 // bc[i] = 0; 4580 // for (i = 0; i < m - 1; ) { 4581 // c = x[i]; 4582 // ++i; 4583 // if (c < ASIZE) bc[c] = i; 4584 // } 4585 // 4586 // /* Searching */ 4587 // j = 0; 4588 // while (j <= n - m) { 4589 // c = y[i+j]; 4590 // if (x[m-1] == c) 4591 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i); 4592 // if (i < 0) return j; 4593 // if (c < ASIZE) 4594 // j = j - bc[y[j+m-1]] + m; 4595 // else 4596 // j += 1; // Advance by 1 only if char >= ASIZE 4597 // } 4598 // } 4599 4600 if (icnt1 == -1) { 4601 BIND(BM); 4602 4603 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP; 4604 Label BMADV, BMMATCH, BMCHECKEND; 4605 4606 Register cnt1end = tmp2; 4607 Register str2end = cnt2; 4608 Register skipch = tmp2; 4609 4610 // Restrict ASIZE to 128 to reduce stack space/initialisation. 4611 // The presence of chars >= ASIZE in the target string does not affect 4612 // performance, but we must be careful not to initialise them in the stack 4613 // array. 4614 // The presence of chars >= ASIZE in the source string may adversely affect 4615 // performance since we can only advance by one when we encounter one. 4616 4617 stp(zr, zr, pre(sp, -128)); 4618 for (int i = 1; i < 8; i++) 4619 stp(zr, zr, Address(sp, i*16)); 4620 4621 mov(cnt1tmp, 0); 4622 sub(cnt1end, cnt1, 1); 4623 BIND(BCLOOP); 4624 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift))); 4625 cmp(ch1, 128); 4626 add(cnt1tmp, cnt1tmp, 1); 4627 br(HS, BCSKIP); 4628 strb(cnt1tmp, Address(sp, ch1)); 4629 BIND(BCSKIP); 4630 cmp(cnt1tmp, cnt1end); 4631 br(LT, BCLOOP); 4632 4633 mov(result_tmp, str2); 4634 4635 sub(cnt2, cnt2, cnt1); 4636 add(str2end, str2, cnt2, LSL, str2_chr_shift); 4637 BIND(BMLOOPSTR2); 4638 sub(cnt1tmp, cnt1, 1); 4639 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift))); 4640 (this->*str2_load_1chr)(skipch, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift))); 4641 cmp(ch1, skipch); 4642 br(NE, BMSKIP); 4643 subs(cnt1tmp, cnt1tmp, 1); 4644 br(LT, BMMATCH); 4645 BIND(BMLOOPSTR1); 4646 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift))); 4647 (this->*str2_load_1chr)(ch2, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift))); 4648 cmp(ch1, ch2); 4649 br(NE, BMSKIP); 4650 subs(cnt1tmp, cnt1tmp, 1); 4651 br(GE, BMLOOPSTR1); 4652 BIND(BMMATCH); 4653 sub(result, str2, result_tmp); 4654 if (!str2_isL) lsr(result, result, 1); 4655 add(sp, sp, 128); 4656 b(DONE); 4657 BIND(BMADV); 4658 add(str2, str2, str2_chr_size); 4659 b(BMCHECKEND); 4660 BIND(BMSKIP); 4661 cmp(skipch, 128); 4662 br(HS, BMADV); 4663 ldrb(ch2, Address(sp, skipch)); 4664 add(str2, str2, cnt1, LSL, str2_chr_shift); 4665 sub(str2, str2, ch2, LSL, str2_chr_shift); 4666 BIND(BMCHECKEND); 4667 cmp(str2, str2end); 4668 br(LE, BMLOOPSTR2); 4669 add(sp, sp, 128); 4670 b(NOMATCH); 4671 } 4672 4673 BIND(LINEARSEARCH); 4674 { 4675 Label DO1, DO2, DO3; 4676 4677 Register str2tmp = tmp2; 4678 Register first = tmp3; 4679 4680 if (icnt1 == -1) 4681 { 4682 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT; 4683 4684 cmp(cnt1, str1_isL == str2_isL ? 4 : 2); 4685 br(LT, DOSHORT); 4686 4687 sub(cnt2, cnt2, cnt1); 4688 mov(result_tmp, cnt2); 4689 4690 lea(str1, Address(str1, cnt1, Address::lsl(str1_chr_shift))); 4691 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4692 sub(cnt1_neg, zr, cnt1, LSL, str1_chr_shift); 4693 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4694 (this->*str1_load_1chr)(first, Address(str1, cnt1_neg)); 4695 4696 BIND(FIRST_LOOP); 4697 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg)); 4698 cmp(first, ch2); 4699 br(EQ, STR1_LOOP); 4700 BIND(STR2_NEXT); 4701 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4702 br(LE, FIRST_LOOP); 4703 b(NOMATCH); 4704 4705 BIND(STR1_LOOP); 4706 adds(cnt1tmp, cnt1_neg, str1_chr_size); 4707 add(cnt2tmp, cnt2_neg, str2_chr_size); 4708 br(GE, MATCH); 4709 4710 BIND(STR1_NEXT); 4711 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp)); 4712 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp)); 4713 cmp(ch1, ch2); 4714 br(NE, STR2_NEXT); 4715 adds(cnt1tmp, cnt1tmp, str1_chr_size); 4716 add(cnt2tmp, cnt2tmp, str2_chr_size); 4717 br(LT, STR1_NEXT); 4718 b(MATCH); 4719 4720 BIND(DOSHORT); 4721 if (str1_isL == str2_isL) { 4722 cmp(cnt1, 2); 4723 br(LT, DO1); 4724 br(GT, DO3); 4725 } 4726 } 4727 4728 if (icnt1 == 4) { 4729 Label CH1_LOOP; 4730 4731 (this->*load_4chr)(ch1, str1); 4732 sub(cnt2, cnt2, 4); 4733 mov(result_tmp, cnt2); 4734 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4735 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4736 4737 BIND(CH1_LOOP); 4738 (this->*load_4chr)(ch2, Address(str2, cnt2_neg)); 4739 cmp(ch1, ch2); 4740 br(EQ, MATCH); 4741 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4742 br(LE, CH1_LOOP); 4743 b(NOMATCH); 4744 } 4745 4746 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 2) { 4747 Label CH1_LOOP; 4748 4749 BIND(DO2); 4750 (this->*load_2chr)(ch1, str1); 4751 sub(cnt2, cnt2, 2); 4752 mov(result_tmp, cnt2); 4753 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4754 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4755 4756 BIND(CH1_LOOP); 4757 (this->*load_2chr)(ch2, Address(str2, cnt2_neg)); 4758 cmp(ch1, ch2); 4759 br(EQ, MATCH); 4760 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4761 br(LE, CH1_LOOP); 4762 b(NOMATCH); 4763 } 4764 4765 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 3) { 4766 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP; 4767 4768 BIND(DO3); 4769 (this->*load_2chr)(first, str1); 4770 (this->*str1_load_1chr)(ch1, Address(str1, 2*str1_chr_size)); 4771 4772 sub(cnt2, cnt2, 3); 4773 mov(result_tmp, cnt2); 4774 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4775 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4776 4777 BIND(FIRST_LOOP); 4778 (this->*load_2chr)(ch2, Address(str2, cnt2_neg)); 4779 cmpw(first, ch2); 4780 br(EQ, STR1_LOOP); 4781 BIND(STR2_NEXT); 4782 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4783 br(LE, FIRST_LOOP); 4784 b(NOMATCH); 4785 4786 BIND(STR1_LOOP); 4787 add(cnt2tmp, cnt2_neg, 2*str2_chr_size); 4788 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp)); 4789 cmp(ch1, ch2); 4790 br(NE, STR2_NEXT); 4791 b(MATCH); 4792 } 4793 4794 if (icnt1 == -1 || icnt1 == 1) { 4795 Label CH1_LOOP, HAS_ZERO; 4796 Label DO1_SHORT, DO1_LOOP; 4797 4798 BIND(DO1); 4799 (this->*str1_load_1chr)(ch1, str1); 4800 cmp(cnt2, 8); 4801 br(LT, DO1_SHORT); 4802 4803 if (str2_isL) { 4804 if (!str1_isL) { 4805 tst(ch1, 0xff00); 4806 br(NE, NOMATCH); 4807 } 4808 orr(ch1, ch1, ch1, LSL, 8); 4809 } 4810 orr(ch1, ch1, ch1, LSL, 16); 4811 orr(ch1, ch1, ch1, LSL, 32); 4812 4813 sub(cnt2, cnt2, 8/str2_chr_size); 4814 mov(result_tmp, cnt2); 4815 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4816 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4817 4818 mov(tmp3, str2_isL ? 0x0101010101010101 : 0x0001000100010001); 4819 BIND(CH1_LOOP); 4820 ldr(ch2, Address(str2, cnt2_neg)); 4821 eor(ch2, ch1, ch2); 4822 sub(tmp1, ch2, tmp3); 4823 orr(tmp2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff); 4824 bics(tmp1, tmp1, tmp2); 4825 br(NE, HAS_ZERO); 4826 adds(cnt2_neg, cnt2_neg, 8); 4827 br(LT, CH1_LOOP); 4828 4829 cmp(cnt2_neg, 8); 4830 mov(cnt2_neg, 0); 4831 br(LT, CH1_LOOP); 4832 b(NOMATCH); 4833 4834 BIND(HAS_ZERO); 4835 rev(tmp1, tmp1); 4836 clz(tmp1, tmp1); 4837 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3); 4838 b(MATCH); 4839 4840 BIND(DO1_SHORT); 4841 mov(result_tmp, cnt2); 4842 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); 4843 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); 4844 BIND(DO1_LOOP); 4845 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg)); 4846 cmpw(ch1, ch2); 4847 br(EQ, MATCH); 4848 adds(cnt2_neg, cnt2_neg, str2_chr_size); 4849 br(LT, DO1_LOOP); 4850 } 4851 } 4852 BIND(NOMATCH); 4853 mov(result, -1); 4854 b(DONE); 4855 BIND(MATCH); 4856 add(result, result_tmp, cnt2_neg, ASR, str2_chr_shift); 4857 BIND(DONE); 4858 } 4859 4860 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr); 4861 typedef void (MacroAssembler::* uxt_insn)(Register Rd, Register Rn); 4862 4863 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, 4864 Register ch, Register result, 4865 Register tmp1, Register tmp2, Register tmp3) 4866 { 4867 Label CH1_LOOP, HAS_ZERO, DO1_SHORT, DO1_LOOP, MATCH, NOMATCH, DONE; 4868 Register cnt1_neg = cnt1; 4869 Register ch1 = rscratch1; 4870 Register result_tmp = rscratch2; 4871 4872 cmp(cnt1, 4); 4873 br(LT, DO1_SHORT); 4874 4875 orr(ch, ch, ch, LSL, 16); 4876 orr(ch, ch, ch, LSL, 32); 4877 4878 sub(cnt1, cnt1, 4); 4879 mov(result_tmp, cnt1); 4880 lea(str1, Address(str1, cnt1, Address::uxtw(1))); 4881 sub(cnt1_neg, zr, cnt1, LSL, 1); 4882 4883 mov(tmp3, 0x0001000100010001); 4884 4885 BIND(CH1_LOOP); 4886 ldr(ch1, Address(str1, cnt1_neg)); 4887 eor(ch1, ch, ch1); 4888 sub(tmp1, ch1, tmp3); 4889 orr(tmp2, ch1, 0x7fff7fff7fff7fff); 4890 bics(tmp1, tmp1, tmp2); 4891 br(NE, HAS_ZERO); 4892 adds(cnt1_neg, cnt1_neg, 8); 4893 br(LT, CH1_LOOP); 4894 4895 cmp(cnt1_neg, 8); 4896 mov(cnt1_neg, 0); 4897 br(LT, CH1_LOOP); 4898 b(NOMATCH); 4899 4900 BIND(HAS_ZERO); 4901 rev(tmp1, tmp1); 4902 clz(tmp1, tmp1); 4903 add(cnt1_neg, cnt1_neg, tmp1, LSR, 3); 4904 b(MATCH); 4905 4906 BIND(DO1_SHORT); 4907 mov(result_tmp, cnt1); 4908 lea(str1, Address(str1, cnt1, Address::uxtw(1))); 4909 sub(cnt1_neg, zr, cnt1, LSL, 1); 4910 BIND(DO1_LOOP); 4911 ldrh(ch1, Address(str1, cnt1_neg)); 4912 cmpw(ch, ch1); 4913 br(EQ, MATCH); 4914 adds(cnt1_neg, cnt1_neg, 2); 4915 br(LT, DO1_LOOP); 4916 BIND(NOMATCH); 4917 mov(result, -1); 4918 b(DONE); 4919 BIND(MATCH); 4920 add(result, result_tmp, cnt1_neg, ASR, 1); 4921 BIND(DONE); 4922 } 4923 4924 // Compare strings. 4925 void MacroAssembler::string_compare(Register str1, Register str2, 4926 Register cnt1, Register cnt2, Register result, 4927 Register tmp1, 4928 FloatRegister vtmp, FloatRegister vtmpZ, int ae) { 4929 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING, 4930 NEXT_WORD, DIFFERENCE; 4931 4932 bool isLL = ae == StrIntrinsicNode::LL; 4933 bool isLU = ae == StrIntrinsicNode::LU; 4934 bool isUL = ae == StrIntrinsicNode::UL; 4935 4936 bool str1_isL = isLL || isLU; 4937 bool str2_isL = isLL || isUL; 4938 4939 int str1_chr_shift = str1_isL ? 0 : 1; 4940 int str2_chr_shift = str2_isL ? 0 : 1; 4941 int str1_chr_size = str1_isL ? 1 : 2; 4942 int str2_chr_size = str2_isL ? 1 : 2; 4943 4944 chr_insn str1_load_chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb : 4945 (chr_insn)&MacroAssembler::ldrh; 4946 chr_insn str2_load_chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb : 4947 (chr_insn)&MacroAssembler::ldrh; 4948 uxt_insn ext_chr = isLL ? (uxt_insn)&MacroAssembler::uxtbw : 4949 (uxt_insn)&MacroAssembler::uxthw; 4950 4951 BLOCK_COMMENT("string_compare {"); 4952 4953 // Bizzarely, the counts are passed in bytes, regardless of whether they 4954 // are L or U strings, however the result is always in characters. 4955 if (!str1_isL) asrw(cnt1, cnt1, 1); 4956 if (!str2_isL) asrw(cnt2, cnt2, 1); 4957 4958 // Compute the minimum of the string lengths and save the difference. 4959 subsw(tmp1, cnt1, cnt2); 4960 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min 4961 4962 // A very short string 4963 cmpw(cnt2, isLL ? 8:4); 4964 br(Assembler::LT, SHORT_STRING); 4965 4966 // Check if the strings start at the same location. 4967 cmp(str1, str2); 4968 br(Assembler::EQ, LENGTH_DIFF); 4969 4970 // Compare longwords 4971 { 4972 subw(cnt2, cnt2, isLL ? 8:4); // The last longword is a special case 4973 4974 // Move both string pointers to the last longword of their 4975 // strings, negate the remaining count, and convert it to bytes. 4976 lea(str1, Address(str1, cnt2, Address::uxtw(str1_chr_shift))); 4977 lea(str2, Address(str2, cnt2, Address::uxtw(str2_chr_shift))); 4978 if (isLU || isUL) { 4979 sub(cnt1, zr, cnt2, LSL, str1_chr_shift); 4980 eor(vtmpZ, T16B, vtmpZ, vtmpZ); 4981 } 4982 sub(cnt2, zr, cnt2, LSL, str2_chr_shift); 4983 4984 // Loop, loading longwords and comparing them into rscratch2. 4985 bind(NEXT_WORD); 4986 if (isLU) { 4987 ldrs(vtmp, Address(str1, cnt1)); 4988 zip1(vtmp, T8B, vtmp, vtmpZ); 4989 umov(result, vtmp, D, 0); 4990 } else { 4991 ldr(result, Address(str1, isUL ? cnt1:cnt2)); 4992 } 4993 if (isUL) { 4994 ldrs(vtmp, Address(str2, cnt2)); 4995 zip1(vtmp, T8B, vtmp, vtmpZ); 4996 umov(rscratch1, vtmp, D, 0); 4997 } else { 4998 ldr(rscratch1, Address(str2, cnt2)); 4999 } 5000 adds(cnt2, cnt2, isUL ? 4:8); 5001 if (isLU || isUL) add(cnt1, cnt1, isLU ? 4:8); 5002 eor(rscratch2, result, rscratch1); 5003 cbnz(rscratch2, DIFFERENCE); 5004 br(Assembler::LT, NEXT_WORD); 5005 5006 // Last longword. In the case where length == 4 we compare the 5007 // same longword twice, but that's still faster than another 5008 // conditional branch. 5009 5010 if (isLU) { 5011 ldrs(vtmp, Address(str1)); 5012 zip1(vtmp, T8B, vtmp, vtmpZ); 5013 umov(result, vtmp, D, 0); 5014 } else { 5015 ldr(result, Address(str1)); 5016 } 5017 if (isUL) { 5018 ldrs(vtmp, Address(str2)); 5019 zip1(vtmp, T8B, vtmp, vtmpZ); 5020 umov(rscratch1, vtmp, D, 0); 5021 } else { 5022 ldr(rscratch1, Address(str2)); 5023 } 5024 eor(rscratch2, result, rscratch1); 5025 cbz(rscratch2, LENGTH_DIFF); 5026 5027 // Find the first different characters in the longwords and 5028 // compute their difference. 5029 bind(DIFFERENCE); 5030 rev(rscratch2, rscratch2); 5031 clz(rscratch2, rscratch2); 5032 andr(rscratch2, rscratch2, isLL ? -8 : -16); 5033 lsrv(result, result, rscratch2); 5034 (this->*ext_chr)(result, result); 5035 lsrv(rscratch1, rscratch1, rscratch2); 5036 (this->*ext_chr)(rscratch1, rscratch1); 5037 subw(result, result, rscratch1); 5038 b(DONE); 5039 } 5040 5041 bind(SHORT_STRING); 5042 // Is the minimum length zero? 5043 cbz(cnt2, LENGTH_DIFF); 5044 5045 bind(SHORT_LOOP); 5046 (this->*str1_load_chr)(result, Address(post(str1, str1_chr_size))); 5047 (this->*str2_load_chr)(cnt1, Address(post(str2, str2_chr_size))); 5048 subw(result, result, cnt1); 5049 cbnz(result, DONE); 5050 sub(cnt2, cnt2, 1); 5051 cbnz(cnt2, SHORT_LOOP); 5052 5053 // Strings are equal up to min length. Return the length difference. 5054 bind(LENGTH_DIFF); 5055 mov(result, tmp1); 5056 5057 // That's it 5058 bind(DONE); 5059 5060 BLOCK_COMMENT("} string_compare"); 5061 } 5062 5063 // This method checks if provided byte array contains byte with highest bit set. 5064 void MacroAssembler::has_negatives(Register ary1, Register len, Register result) { 5065 // Simple and most common case of aligned small array which is not at the 5066 // end of memory page is placed here. All other cases are in stub. 5067 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE; 5068 const uint64_t UPPER_BIT_MASK=0x8080808080808080; 5069 assert_different_registers(ary1, len, result); 5070 5071 cmpw(len, 0); 5072 br(LE, SET_RESULT); 5073 cmpw(len, 4 * wordSize); 5074 br(GE, STUB_LONG); // size > 32 then go to stub 5075 5076 int shift = 64 - exact_log2(os::vm_page_size()); 5077 lsl(rscratch1, ary1, shift); 5078 mov(rscratch2, (size_t)(4 * wordSize) << shift); 5079 adds(rscratch2, rscratch1, rscratch2); // At end of page? 5080 br(CS, STUB); // at the end of page then go to stub 5081 subs(len, len, wordSize); 5082 br(LT, END); 5083 5084 BIND(LOOP); 5085 ldr(rscratch1, Address(post(ary1, wordSize))); 5086 tst(rscratch1, UPPER_BIT_MASK); 5087 br(NE, SET_RESULT); 5088 subs(len, len, wordSize); 5089 br(GE, LOOP); 5090 cmpw(len, -wordSize); 5091 br(EQ, SET_RESULT); 5092 5093 BIND(END); 5094 ldr(result, Address(ary1)); 5095 sub(len, zr, len, LSL, 3); // LSL 3 is to get bits from bytes 5096 lslv(result, result, len); 5097 tst(result, UPPER_BIT_MASK); 5098 b(SET_RESULT); 5099 5100 BIND(STUB); 5101 RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives()); 5102 assert(has_neg.target() != NULL, "has_negatives stub has not been generated"); 5103 trampoline_call(has_neg); 5104 b(DONE); 5105 5106 BIND(STUB_LONG); 5107 RuntimeAddress has_neg_long = RuntimeAddress( 5108 StubRoutines::aarch64::has_negatives_long()); 5109 assert(has_neg_long.target() != NULL, "has_negatives stub has not been generated"); 5110 trampoline_call(has_neg_long); 5111 b(DONE); 5112 5113 BIND(SET_RESULT); 5114 cset(result, NE); // set true or false 5115 5116 BIND(DONE); 5117 } 5118 5119 // Compare Strings or char/byte arrays. 5120 5121 // is_string is true iff this is a string comparison. 5122 5123 // For Strings we're passed the address of the first characters in a1 5124 // and a2 and the length in cnt1. 5125 5126 // For byte and char arrays we're passed the arrays themselves and we 5127 // have to extract length fields and do null checks here. 5128 5129 // elem_size is the element size in bytes: either 1 or 2. 5130 5131 // There are two implementations. For arrays >= 8 bytes, all 5132 // comparisons (including the final one, which may overlap) are 5133 // performed 8 bytes at a time. For arrays < 8 bytes, we compare a 5134 // halfword, then a short, and then a byte. 5135 5136 void MacroAssembler::arrays_equals(Register a1, Register a2, 5137 Register result, Register cnt1, 5138 int elem_size, bool is_string) 5139 { 5140 Label SAME, DONE, SHORT, NEXT_WORD, ONE; 5141 Register tmp1 = rscratch1; 5142 Register tmp2 = rscratch2; 5143 Register cnt2 = tmp2; // cnt2 only used in array length compare 5144 int elem_per_word = wordSize/elem_size; 5145 int log_elem_size = exact_log2(elem_size); 5146 int length_offset = arrayOopDesc::length_offset_in_bytes(); 5147 int base_offset 5148 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE); 5149 5150 assert(elem_size == 1 || elem_size == 2, "must be char or byte"); 5151 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2); 5152 5153 #ifndef PRODUCT 5154 { 5155 const char kind = (elem_size == 2) ? 'U' : 'L'; 5156 char comment[64]; 5157 snprintf(comment, sizeof comment, "%s%c%s {", 5158 is_string ? "string_equals" : "array_equals", 5159 kind, "{"); 5160 BLOCK_COMMENT(comment); 5161 } 5162 #endif 5163 5164 mov(result, false); 5165 5166 if (!is_string) { 5167 // if (a==a2) 5168 // return true; 5169 eor(rscratch1, a1, a2); 5170 cbz(rscratch1, SAME); 5171 // if (a==null || a2==null) 5172 // return false; 5173 cbz(a1, DONE); 5174 cbz(a2, DONE); 5175 // if (a1.length != a2.length) 5176 // return false; 5177 ldrw(cnt1, Address(a1, length_offset)); 5178 ldrw(cnt2, Address(a2, length_offset)); 5179 eorw(tmp1, cnt1, cnt2); 5180 cbnzw(tmp1, DONE); 5181 5182 lea(a1, Address(a1, base_offset)); 5183 lea(a2, Address(a2, base_offset)); 5184 } 5185 5186 // Check for short strings, i.e. smaller than wordSize. 5187 subs(cnt1, cnt1, elem_per_word); 5188 br(Assembler::LT, SHORT); 5189 // Main 8 byte comparison loop. 5190 bind(NEXT_WORD); { 5191 ldr(tmp1, Address(post(a1, wordSize))); 5192 ldr(tmp2, Address(post(a2, wordSize))); 5193 subs(cnt1, cnt1, elem_per_word); 5194 eor(tmp1, tmp1, tmp2); 5195 cbnz(tmp1, DONE); 5196 } br(GT, NEXT_WORD); 5197 // Last longword. In the case where length == 4 we compare the 5198 // same longword twice, but that's still faster than another 5199 // conditional branch. 5200 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when 5201 // length == 4. 5202 if (log_elem_size > 0) 5203 lsl(cnt1, cnt1, log_elem_size); 5204 ldr(tmp1, Address(a1, cnt1)); 5205 ldr(tmp2, Address(a2, cnt1)); 5206 eor(tmp1, tmp1, tmp2); 5207 cbnz(tmp1, DONE); 5208 b(SAME); 5209 5210 bind(SHORT); 5211 Label TAIL03, TAIL01; 5212 5213 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left. 5214 { 5215 ldrw(tmp1, Address(post(a1, 4))); 5216 ldrw(tmp2, Address(post(a2, 4))); 5217 eorw(tmp1, tmp1, tmp2); 5218 cbnzw(tmp1, DONE); 5219 } 5220 bind(TAIL03); 5221 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left. 5222 { 5223 ldrh(tmp1, Address(post(a1, 2))); 5224 ldrh(tmp2, Address(post(a2, 2))); 5225 eorw(tmp1, tmp1, tmp2); 5226 cbnzw(tmp1, DONE); 5227 } 5228 bind(TAIL01); 5229 if (elem_size == 1) { // Only needed when comparing byte arrays. 5230 tbz(cnt1, 0, SAME); // 0-1 bytes left. 5231 { 5232 ldrb(tmp1, a1); 5233 ldrb(tmp2, a2); 5234 eorw(tmp1, tmp1, tmp2); 5235 cbnzw(tmp1, DONE); 5236 } 5237 } 5238 // Arrays are equal. 5239 bind(SAME); 5240 mov(result, true); 5241 5242 // That's it. 5243 bind(DONE); 5244 BLOCK_COMMENT(is_string ? "} string_equals" : "} array_equals"); 5245 } 5246 5247 5248 // The size of the blocks erased by the zero_blocks stub. We must 5249 // handle anything smaller than this ourselves in zero_words(). 5250 const int MacroAssembler::zero_words_block_size = 8; 5251 5252 // zero_words() is used by C2 ClearArray patterns. It is as small as 5253 // possible, handling small word counts locally and delegating 5254 // anything larger to the zero_blocks stub. It is expanded many times 5255 // in compiled code, so it is important to keep it short. 5256 5257 // ptr: Address of a buffer to be zeroed. 5258 // cnt: Count in HeapWords. 5259 // 5260 // ptr, cnt, rscratch1, and rscratch2 are clobbered. 5261 void MacroAssembler::zero_words(Register ptr, Register cnt) 5262 { 5263 assert(is_power_of_2(zero_words_block_size), "adjust this"); 5264 assert(ptr == r10 && cnt == r11, "mismatch in register usage"); 5265 5266 BLOCK_COMMENT("zero_words {"); 5267 cmp(cnt, zero_words_block_size); 5268 Label around, done, done16; 5269 br(LO, around); 5270 { 5271 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks()); 5272 assert(zero_blocks.target() != NULL, "zero_blocks stub has not been generated"); 5273 if (StubRoutines::aarch64::complete()) { 5274 trampoline_call(zero_blocks); 5275 } else { 5276 bl(zero_blocks); 5277 } 5278 } 5279 bind(around); 5280 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) { 5281 Label l; 5282 tbz(cnt, exact_log2(i), l); 5283 for (int j = 0; j < i; j += 2) { 5284 stp(zr, zr, post(ptr, 16)); 5285 } 5286 bind(l); 5287 } 5288 { 5289 Label l; 5290 tbz(cnt, 0, l); 5291 str(zr, Address(ptr)); 5292 bind(l); 5293 } 5294 BLOCK_COMMENT("} zero_words"); 5295 } 5296 5297 // base: Address of a buffer to be zeroed, 8 bytes aligned. 5298 // cnt: Immediate count in HeapWords. 5299 #define SmallArraySize (18 * BytesPerLong) 5300 void MacroAssembler::zero_words(Register base, u_int64_t cnt) 5301 { 5302 BLOCK_COMMENT("zero_words {"); 5303 int i = cnt & 1; // store any odd word to start 5304 if (i) str(zr, Address(base)); 5305 5306 if (cnt <= SmallArraySize / BytesPerLong) { 5307 for (; i < (int)cnt; i += 2) 5308 stp(zr, zr, Address(base, i * wordSize)); 5309 } else { 5310 const int unroll = 4; // Number of stp(zr, zr) instructions we'll unroll 5311 int remainder = cnt % (2 * unroll); 5312 for (; i < remainder; i += 2) 5313 stp(zr, zr, Address(base, i * wordSize)); 5314 5315 Label loop; 5316 Register cnt_reg = rscratch1; 5317 Register loop_base = rscratch2; 5318 cnt = cnt - remainder; 5319 mov(cnt_reg, cnt); 5320 // adjust base and prebias by -2 * wordSize so we can pre-increment 5321 add(loop_base, base, (remainder - 2) * wordSize); 5322 bind(loop); 5323 sub(cnt_reg, cnt_reg, 2 * unroll); 5324 for (i = 1; i < unroll; i++) 5325 stp(zr, zr, Address(loop_base, 2 * i * wordSize)); 5326 stp(zr, zr, Address(pre(loop_base, 2 * unroll * wordSize))); 5327 cbnz(cnt_reg, loop); 5328 } 5329 BLOCK_COMMENT("} zero_words"); 5330 } 5331 5332 // Zero blocks of memory by using DC ZVA. 5333 // 5334 // Aligns the base address first sufficently for DC ZVA, then uses 5335 // DC ZVA repeatedly for every full block. cnt is the size to be 5336 // zeroed in HeapWords. Returns the count of words left to be zeroed 5337 // in cnt. 5338 // 5339 // NOTE: This is intended to be used in the zero_blocks() stub. If 5340 // you want to use it elsewhere, note that cnt must be >= 2*zva_length. 5341 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) { 5342 Register tmp = rscratch1; 5343 Register tmp2 = rscratch2; 5344 int zva_length = VM_Version::zva_length(); 5345 Label initial_table_end, loop_zva; 5346 Label fini; 5347 5348 // Base must be 16 byte aligned. If not just return and let caller handle it 5349 tst(base, 0x0f); 5350 br(Assembler::NE, fini); 5351 // Align base with ZVA length. 5352 neg(tmp, base); 5353 andr(tmp, tmp, zva_length - 1); 5354 5355 // tmp: the number of bytes to be filled to align the base with ZVA length. 5356 add(base, base, tmp); 5357 sub(cnt, cnt, tmp, Assembler::ASR, 3); 5358 adr(tmp2, initial_table_end); 5359 sub(tmp2, tmp2, tmp, Assembler::LSR, 2); 5360 br(tmp2); 5361 5362 for (int i = -zva_length + 16; i < 0; i += 16) 5363 stp(zr, zr, Address(base, i)); 5364 bind(initial_table_end); 5365 5366 sub(cnt, cnt, zva_length >> 3); 5367 bind(loop_zva); 5368 dc(Assembler::ZVA, base); 5369 subs(cnt, cnt, zva_length >> 3); 5370 add(base, base, zva_length); 5371 br(Assembler::GE, loop_zva); 5372 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA 5373 bind(fini); 5374 } 5375 5376 // base: Address of a buffer to be filled, 8 bytes aligned. 5377 // cnt: Count in 8-byte unit. 5378 // value: Value to be filled with. 5379 // base will point to the end of the buffer after filling. 5380 void MacroAssembler::fill_words(Register base, Register cnt, Register value) 5381 { 5382 // Algorithm: 5383 // 5384 // scratch1 = cnt & 7; 5385 // cnt -= scratch1; 5386 // p += scratch1; 5387 // switch (scratch1) { 5388 // do { 5389 // cnt -= 8; 5390 // p[-8] = v; 5391 // case 7: 5392 // p[-7] = v; 5393 // case 6: 5394 // p[-6] = v; 5395 // // ... 5396 // case 1: 5397 // p[-1] = v; 5398 // case 0: 5399 // p += 8; 5400 // } while (cnt); 5401 // } 5402 5403 assert_different_registers(base, cnt, value, rscratch1, rscratch2); 5404 5405 Label fini, skip, entry, loop; 5406 const int unroll = 8; // Number of stp instructions we'll unroll 5407 5408 cbz(cnt, fini); 5409 tbz(base, 3, skip); 5410 str(value, Address(post(base, 8))); 5411 sub(cnt, cnt, 1); 5412 bind(skip); 5413 5414 andr(rscratch1, cnt, (unroll-1) * 2); 5415 sub(cnt, cnt, rscratch1); 5416 add(base, base, rscratch1, Assembler::LSL, 3); 5417 adr(rscratch2, entry); 5418 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1); 5419 br(rscratch2); 5420 5421 bind(loop); 5422 add(base, base, unroll * 16); 5423 for (int i = -unroll; i < 0; i++) 5424 stp(value, value, Address(base, i * 16)); 5425 bind(entry); 5426 subs(cnt, cnt, unroll * 2); 5427 br(Assembler::GE, loop); 5428 5429 tbz(cnt, 0, fini); 5430 str(value, Address(post(base, 8))); 5431 bind(fini); 5432 } 5433 5434 // Intrinsic for sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray and 5435 // java/lang/StringUTF16.compress. 5436 void MacroAssembler::encode_iso_array(Register src, Register dst, 5437 Register len, Register result, 5438 FloatRegister Vtmp1, FloatRegister Vtmp2, 5439 FloatRegister Vtmp3, FloatRegister Vtmp4) 5440 { 5441 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1; 5442 Register tmp1 = rscratch1; 5443 5444 mov(result, len); // Save initial len 5445 5446 #ifndef BUILTIN_SIM 5447 subs(len, len, 32); 5448 br(LT, LOOP_8); 5449 5450 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions 5451 // to convert chars to bytes. These set the 'QC' bit in the FPSR if 5452 // any char could not fit in a byte, so clear the FPSR so we can test it. 5453 clear_fpsr(); 5454 5455 BIND(NEXT_32); 5456 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); 5457 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half 5458 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half 5459 uqxtn(Vtmp2, T8B, Vtmp3, T8H); 5460 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2 5461 get_fpsr(tmp1); 5462 cbnzw(tmp1, LOOP_8); 5463 st1(Vtmp1, Vtmp2, T16B, post(dst, 32)); 5464 subs(len, len, 32); 5465 add(src, src, 64); 5466 br(GE, NEXT_32); 5467 5468 BIND(LOOP_8); 5469 adds(len, len, 32-8); 5470 br(LT, LOOP_1); 5471 clear_fpsr(); // QC may be set from loop above, clear again 5472 BIND(NEXT_8); 5473 ld1(Vtmp1, T8H, src); 5474 uqxtn(Vtmp1, T8B, Vtmp1, T8H); 5475 get_fpsr(tmp1); 5476 cbnzw(tmp1, LOOP_1); 5477 st1(Vtmp1, T8B, post(dst, 8)); 5478 subs(len, len, 8); 5479 add(src, src, 16); 5480 br(GE, NEXT_8); 5481 5482 BIND(LOOP_1); 5483 adds(len, len, 8); 5484 br(LE, DONE); 5485 #else 5486 cbz(len, DONE); 5487 #endif 5488 BIND(NEXT_1); 5489 ldrh(tmp1, Address(post(src, 2))); 5490 tst(tmp1, 0xff00); 5491 br(NE, DONE); 5492 strb(tmp1, Address(post(dst, 1))); 5493 subs(len, len, 1); 5494 br(GT, NEXT_1); 5495 5496 BIND(DONE); 5497 sub(result, result, len); // Return index where we stopped 5498 // Return len == 0 if we processed all 5499 // characters 5500 } 5501 5502 5503 // Inflate byte[] array to char[]. 5504 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 5505 FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3, 5506 Register tmp4) { 5507 Label big, done; 5508 5509 assert_different_registers(src, dst, len, tmp4, rscratch1); 5510 5511 fmovd(vtmp1 , zr); 5512 lsrw(rscratch1, len, 3); 5513 5514 cbnzw(rscratch1, big); 5515 5516 // Short string: less than 8 bytes. 5517 { 5518 Label loop, around, tiny; 5519 5520 subsw(len, len, 4); 5521 andw(len, len, 3); 5522 br(LO, tiny); 5523 5524 // Use SIMD to do 4 bytes. 5525 ldrs(vtmp2, post(src, 4)); 5526 zip1(vtmp3, T8B, vtmp2, vtmp1); 5527 strd(vtmp3, post(dst, 8)); 5528 5529 cbzw(len, done); 5530 5531 // Do the remaining bytes by steam. 5532 bind(loop); 5533 ldrb(tmp4, post(src, 1)); 5534 strh(tmp4, post(dst, 2)); 5535 subw(len, len, 1); 5536 5537 bind(tiny); 5538 cbnz(len, loop); 5539 5540 bind(around); 5541 b(done); 5542 } 5543 5544 // Unpack the bytes 8 at a time. 5545 bind(big); 5546 andw(len, len, 7); 5547 5548 { 5549 Label loop, around; 5550 5551 bind(loop); 5552 ldrd(vtmp2, post(src, 8)); 5553 sub(rscratch1, rscratch1, 1); 5554 zip1(vtmp3, T16B, vtmp2, vtmp1); 5555 st1(vtmp3, T8H, post(dst, 16)); 5556 cbnz(rscratch1, loop); 5557 5558 bind(around); 5559 } 5560 5561 // Do the tail of up to 8 bytes. 5562 sub(src, src, 8); 5563 add(src, src, len, ext::uxtw, 0); 5564 ldrd(vtmp2, Address(src)); 5565 sub(dst, dst, 16); 5566 add(dst, dst, len, ext::uxtw, 1); 5567 zip1(vtmp3, T16B, vtmp2, vtmp1); 5568 st1(vtmp3, T8H, Address(dst)); 5569 5570 bind(done); 5571 } 5572 5573 // Compress char[] array to byte[]. 5574 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 5575 FloatRegister tmp1Reg, FloatRegister tmp2Reg, 5576 FloatRegister tmp3Reg, FloatRegister tmp4Reg, 5577 Register result) { 5578 encode_iso_array(src, dst, len, result, 5579 tmp1Reg, tmp2Reg, tmp3Reg, tmp4Reg); 5580 cmp(len, zr); 5581 csel(result, result, zr, EQ); 5582 } 5583 5584 // get_thread() can be called anywhere inside generated code so we 5585 // need to save whatever non-callee save context might get clobbered 5586 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed, 5587 // the call setup code. 5588 // 5589 // aarch64_get_thread_helper() clobbers only r0, r1, and flags. 5590 // 5591 void MacroAssembler::get_thread(Register dst) { 5592 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst; 5593 push(saved_regs, sp); 5594 5595 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)); 5596 blrt(lr, 1, 0, 1); 5597 if (dst != c_rarg0) { 5598 mov(dst, c_rarg0); 5599 } 5600 5601 pop(saved_regs, sp); 5602 }