1 /*
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   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
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  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
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  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
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  25 
  26 #ifndef CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
  27 #define CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
  28 
  29 #include "asm/assembler.hpp"
  30 #include "memory/allocation.hpp"
  31 #include "runtime/icache.hpp"
  32 #include "runtime/os.hpp"
  33 
  34 // We have interfaces for the following instructions:
  35 // - NativeInstruction
  36 // - - NativeCall
  37 // - - NativeMovConstReg
  38 // - - NativeMovConstRegPatching
  39 // - - NativeMovRegMem
  40 // - - NativeMovRegMemPatching
  41 // - - NativeJump
  42 // - - NativeIllegalOpCode
  43 // - - NativeGeneralJump
  44 // - - NativeReturn
  45 // - - NativeReturnX (return with argument)
  46 // - - NativePushConst
  47 // - - NativeTstRegMem
  48 
  49 // The base class for different kinds of native instruction abstractions.
  50 // Provides the primitive operations to manipulate code relative to this.
  51 
  52 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
  53   friend class Relocation;
  54   friend bool is_NativeCallTrampolineStub_at(address);
  55  public:
  56   enum {
  57     instruction_size = 4
  58   };
  59 
  60   juint encoding() const {
  61     return uint_at(0);
  62   }
  63 
  64   bool is_blr()                      const { return (encoding() & 0xff9ffc1f) == 0xd61f0000; } // blr(register) or br(register)
  65   bool is_adr_aligned()              const { return (encoding() & 0xff000000) == 0x10000000; } // adr Xn, <label>, where label is aligned to 4 bytes (address of instruction).
  66 
  67   inline bool is_nop();
  68   inline bool is_illegal();
  69   inline bool is_return();
  70   bool is_jump();
  71   bool is_general_jump();
  72   inline bool is_jump_or_nop();
  73   inline bool is_cond_jump();
  74   bool is_safepoint_poll();
  75   bool is_movz();
  76   bool is_movk();
  77   bool is_sigill_zombie_not_entrant();
  78 
  79  protected:
  80   address addr_at(int offset) const    { return address(this) + offset; }
  81 
  82   s_char sbyte_at(int offset) const    { return *(s_char*) addr_at(offset); }
  83   u_char ubyte_at(int offset) const    { return *(u_char*) addr_at(offset); }
  84 
  85   jint int_at(int offset) const        { return *(jint*) addr_at(offset); }
  86   juint uint_at(int offset) const      { return *(juint*) addr_at(offset); }
  87 
  88   address ptr_at(int offset) const     { return *(address*) addr_at(offset); }
  89 
  90   oop  oop_at (int offset) const       { return *(oop*) addr_at(offset); }
  91 
  92 
  93   void set_char_at(int offset, char c)        { *addr_at(offset) = (u_char)c; }
  94   void set_int_at(int offset, jint  i)        { *(jint*)addr_at(offset) = i; }
  95   void set_uint_at(int offset, jint  i)       { *(juint*)addr_at(offset) = i; }
  96   void set_ptr_at (int offset, address  ptr)  { *(address*) addr_at(offset) = ptr; }
  97   void set_oop_at (int offset, oop  o)        { *(oop*) addr_at(offset) = o; }
  98 
  99  public:
 100 
 101   // unit test stuff
 102   static void test() {}                 // override for testing
 103 
 104   inline friend NativeInstruction* nativeInstruction_at(address address);
 105 
 106   static bool is_adrp_at(address instr);
 107 
 108   static bool is_ldr_literal_at(address instr);
 109 
 110   bool is_ldr_literal() {
 111     return is_ldr_literal_at(addr_at(0));
 112   }
 113 
 114   static bool is_ldrw_to_zr(address instr);
 115 
 116   static bool is_call_at(address instr) {
 117     const uint32_t insn = (*(uint32_t*)instr);
 118     return (insn >> 26) == 0b100101;
 119   }
 120 
 121   bool is_call() {
 122     return is_call_at(addr_at(0));
 123   }
 124 
 125   static bool maybe_cpool_ref(address instr) {
 126     return is_adrp_at(instr) || is_ldr_literal_at(instr);
 127   }
 128 
 129   bool is_Membar() {
 130     unsigned int insn = uint_at(0);
 131     return Instruction_aarch64::extract(insn, 31, 12) == 0b11010101000000110011 &&
 132       Instruction_aarch64::extract(insn, 7, 0) == 0b10111111;
 133   }
 134 };
 135 
 136 inline NativeInstruction* nativeInstruction_at(address address) {
 137   return (NativeInstruction*)address;
 138 }
 139 
 140 // The natural type of an AArch64 instruction is uint32_t
 141 inline NativeInstruction* nativeInstruction_at(uint32_t *address) {
 142   return (NativeInstruction*)address;
 143 }
 144 
 145 inline NativeCall* nativeCall_at(address address);
 146 // The NativeCall is an abstraction for accessing/manipulating native
 147 // call instructions (used to manipulate inline caches, primitive &
 148 // DSO calls, etc.).
 149 
 150 class NativeCall: public NativeInstruction {
 151  public:
 152   enum Aarch64_specific_constants {
 153     instruction_size            =    4,
 154     instruction_offset          =    0,
 155     displacement_offset         =    0,
 156     return_address_offset       =    4
 157   };
 158 
 159   address instruction_address() const       { return addr_at(instruction_offset); }
 160   address next_instruction_address() const  { return addr_at(return_address_offset); }
 161   int   displacement() const                { return (int_at(displacement_offset) << 6) >> 4; }
 162   address displacement_address() const      { return addr_at(displacement_offset); }
 163   address return_address() const            { return addr_at(return_address_offset); }
 164   address destination() const;
 165 
 166   void  set_destination(address dest)       {
 167     int offset = dest - instruction_address();
 168     unsigned int insn = 0b100101 << 26;
 169     assert((offset & 3) == 0, "should be");
 170     offset >>= 2;
 171     offset &= (1 << 26) - 1; // mask off insn part
 172     insn |= offset;
 173     set_int_at(displacement_offset, insn);
 174   }
 175 
 176   void  verify_alignment()                       { ; }
 177   void  verify();
 178   void  print();
 179 
 180   // Creation
 181   inline friend NativeCall* nativeCall_at(address address);
 182   inline friend NativeCall* nativeCall_before(address return_address);
 183 
 184   static bool is_call_before(address return_address) {
 185     return is_call_at(return_address - NativeCall::return_address_offset);
 186   }
 187 
 188   // MT-safe patching of a call instruction.
 189   static void insert(address code_pos, address entry);
 190 
 191   static void replace_mt_safe(address instr_addr, address code_buffer);
 192 
 193   // Similar to replace_mt_safe, but just changes the destination.  The
 194   // important thing is that free-running threads are able to execute
 195   // this call instruction at all times.  If the call is an immediate BL
 196   // instruction we can simply rely on atomicity of 32-bit writes to
 197   // make sure other threads will see no intermediate states.
 198 
 199   // We cannot rely on locks here, since the free-running threads must run at
 200   // full speed.
 201   //
 202   // Used in the runtime linkage of calls; see class CompiledIC.
 203   // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
 204 
 205   // The parameter assert_lock disables the assertion during code generation.
 206   void set_destination_mt_safe(address dest, bool assert_lock = true);
 207 
 208   address get_trampoline();
 209   address trampoline_jump(CodeBuffer &cbuf, address dest);
 210 };
 211 
 212 inline NativeCall* nativeCall_at(address address) {
 213   NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
 214 #ifdef ASSERT
 215   call->verify();
 216 #endif
 217   return call;
 218 }
 219 
 220 inline NativeCall* nativeCall_before(address return_address) {
 221   NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
 222 #ifdef ASSERT
 223   call->verify();
 224 #endif
 225   return call;
 226 }
 227 
 228 // An interface for accessing/manipulating native mov reg, imm instructions.
 229 // (used to manipulate inlined 64-bit data calls, etc.)
 230 class NativeMovConstReg: public NativeInstruction {
 231  public:
 232   enum Aarch64_specific_constants {
 233     instruction_size            =    3 * 4, // movz, movk, movk.  See movptr().
 234     instruction_offset          =    0,
 235     displacement_offset         =    0,
 236   };
 237 
 238   address instruction_address() const       { return addr_at(instruction_offset); }
 239   address next_instruction_address() const  {
 240     if (nativeInstruction_at(instruction_address())->is_movz())
 241       // Assume movz, movk, movk
 242       return addr_at(instruction_size);
 243     else if (is_adrp_at(instruction_address()))
 244       return addr_at(2*4);
 245     else if (is_ldr_literal_at(instruction_address()))
 246       return(addr_at(4));
 247     assert(false, "Unknown instruction in NativeMovConstReg");
 248     return NULL;
 249   }
 250 
 251   intptr_t data() const;
 252   void  set_data(intptr_t x);
 253 
 254   void flush() {
 255     if (! maybe_cpool_ref(instruction_address())) {
 256       ICache::invalidate_range(instruction_address(), instruction_size);
 257     }
 258   }
 259 
 260   void  verify();
 261   void  print();
 262 
 263   // unit test stuff
 264   static void test() {}
 265 
 266   // Creation
 267   inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
 268   inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
 269 };
 270 
 271 inline NativeMovConstReg* nativeMovConstReg_at(address address) {
 272   NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
 273 #ifdef ASSERT
 274   test->verify();
 275 #endif
 276   return test;
 277 }
 278 
 279 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
 280   NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
 281 #ifdef ASSERT
 282   test->verify();
 283 #endif
 284   return test;
 285 }
 286 
 287 class NativeMovConstRegPatching: public NativeMovConstReg {
 288  private:
 289     friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
 290     NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
 291     #ifdef ASSERT
 292       test->verify();
 293     #endif
 294     return test;
 295     }
 296 };
 297 
 298 // An interface for accessing/manipulating native moves of the form:
 299 //      mov[b/w/l/q] [reg + offset], reg   (instruction_code_reg2mem)
 300 //      mov[b/w/l/q] reg, [reg+offset]     (instruction_code_mem2reg
 301 //      mov[s/z]x[w/b/q] [reg + offset], reg
 302 //      fld_s  [reg+offset]
 303 //      fld_d  [reg+offset]
 304 //      fstp_s [reg + offset]
 305 //      fstp_d [reg + offset]
 306 //      mov_literal64  scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
 307 //
 308 // Warning: These routines must be able to handle any instruction sequences
 309 // that are generated as a result of the load/store byte,word,long
 310 // macros.  For example: The load_unsigned_byte instruction generates
 311 // an xor reg,reg inst prior to generating the movb instruction.  This
 312 // class must skip the xor instruction.
 313 
 314 class NativeMovRegMem: public NativeInstruction {
 315   enum AArch64_specific_constants {
 316     instruction_size            =    4,
 317     instruction_offset          =    0,
 318     data_offset                 =    0,
 319     next_instruction_offset     =    4
 320   };
 321 
 322  public:
 323   // helper
 324   int instruction_start() const;
 325 
 326   address instruction_address() const;
 327 
 328   address next_instruction_address() const;
 329 
 330   int   offset() const;
 331 
 332   void  set_offset(int x);
 333 
 334   void  add_offset_in_bytes(int add_offset)     { set_offset ( ( offset() + add_offset ) ); }
 335 
 336   void verify();
 337   void print ();
 338 
 339   // unit test stuff
 340   static void test() {}
 341 
 342  private:
 343   inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
 344 };
 345 
 346 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
 347   NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
 348 #ifdef ASSERT
 349   test->verify();
 350 #endif
 351   return test;
 352 }
 353 
 354 class NativeMovRegMemPatching: public NativeMovRegMem {
 355  private:
 356   friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {Unimplemented(); return 0;  }
 357 };
 358 
 359 // An interface for accessing/manipulating native leal instruction of form:
 360 //        leal reg, [reg + offset]
 361 
 362 class NativeLoadAddress: public NativeInstruction {
 363   enum AArch64_specific_constants {
 364     instruction_size            =    4,
 365     instruction_offset          =    0,
 366     data_offset                 =    0,
 367     next_instruction_offset     =    4
 368   };
 369 
 370  public:
 371   void verify();
 372   void print ();
 373 
 374   // unit test stuff
 375   static void test() {}
 376 };
 377 
 378 class NativeJump: public NativeInstruction {
 379  public:
 380   enum AArch64_specific_constants {
 381     instruction_size            =    4,
 382     instruction_offset          =    0,
 383     data_offset                 =    0,
 384     next_instruction_offset     =    4
 385   };
 386 
 387   address instruction_address() const       { return addr_at(instruction_offset); }
 388   address next_instruction_address() const  { return addr_at(instruction_size); }
 389   address jump_destination() const;
 390   void set_jump_destination(address dest);
 391 
 392   // Creation
 393   inline friend NativeJump* nativeJump_at(address address);
 394 
 395   void verify();
 396 
 397   // Unit testing stuff
 398   static void test() {}
 399 
 400   // Insertion of native jump instruction
 401   static void insert(address code_pos, address entry);
 402   // MT-safe insertion of native jump at verified method entry
 403   static void check_verified_entry_alignment(address entry, address verified_entry);
 404   static void patch_verified_entry(address entry, address verified_entry, address dest);
 405 };
 406 
 407 inline NativeJump* nativeJump_at(address address) {
 408   NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
 409 #ifdef ASSERT
 410   jump->verify();
 411 #endif
 412   return jump;
 413 }
 414 
 415 class NativeGeneralJump: public NativeJump {
 416 public:
 417   enum AArch64_specific_constants {
 418     instruction_size            =    4 * 4,
 419     instruction_offset          =    0,
 420     data_offset                 =    0,
 421     next_instruction_offset     =    4 * 4
 422   };
 423 
 424   address jump_destination() const;
 425   void set_jump_destination(address dest);
 426 
 427   static void insert_unconditional(address code_pos, address entry);
 428   static void replace_mt_safe(address instr_addr, address code_buffer);
 429   static void verify();
 430 };
 431 
 432 inline NativeGeneralJump* nativeGeneralJump_at(address address) {
 433   NativeGeneralJump* jump = (NativeGeneralJump*)(address);
 434   debug_only(jump->verify();)
 435   return jump;
 436 }
 437 
 438 class NativePopReg : public NativeInstruction {
 439  public:
 440   // Insert a pop instruction
 441   static void insert(address code_pos, Register reg);
 442 };
 443 
 444 
 445 class NativeIllegalInstruction: public NativeInstruction {
 446  public:
 447   // Insert illegal opcode as specific address
 448   static void insert(address code_pos);
 449 };
 450 
 451 // return instruction that does not pop values of the stack
 452 class NativeReturn: public NativeInstruction {
 453  public:
 454 };
 455 
 456 // return instruction that does pop values of the stack
 457 class NativeReturnX: public NativeInstruction {
 458  public:
 459 };
 460 
 461 // Simple test vs memory
 462 class NativeTstRegMem: public NativeInstruction {
 463  public:
 464 };
 465 
 466 inline bool NativeInstruction::is_nop()         {
 467   uint32_t insn = *(uint32_t*)addr_at(0);
 468   return insn == 0xd503201f;
 469 }
 470 
 471 inline bool NativeInstruction::is_jump() {
 472   uint32_t insn = *(uint32_t*)addr_at(0);
 473 
 474   if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
 475     // Unconditional branch (immediate)
 476     return true;
 477   } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
 478     // Conditional branch (immediate)
 479     return true;
 480   } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
 481     // Compare & branch (immediate)
 482     return true;
 483   } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
 484     // Test & branch (immediate)
 485     return true;
 486   } else
 487     return false;
 488 }
 489 
 490 inline bool NativeInstruction::is_jump_or_nop() {
 491   return is_nop() || is_jump();
 492 }
 493 
 494 // Call trampoline stubs.
 495 class NativeCallTrampolineStub : public NativeInstruction {
 496  public:
 497 
 498   enum AArch64_specific_constants {
 499     instruction_size            =    4 * 4,
 500     instruction_offset          =    0,
 501     data_offset                 =    2 * 4,
 502     next_instruction_offset     =    4 * 4
 503   };
 504 
 505   address destination(nmethod *nm = NULL) const;
 506   void set_destination(address new_destination);
 507   ptrdiff_t destination_offset() const;
 508 };
 509 
 510 inline bool is_NativeCallTrampolineStub_at(address addr) {
 511   // Ensure that the stub is exactly
 512   //      ldr   xscratch1, L
 513   //      br    xscratch1
 514   // L:
 515   uint32_t *i = (uint32_t *)addr;
 516   return i[0] == 0x58000048 && i[1] == 0xd61f0100;
 517 }
 518 
 519 inline NativeCallTrampolineStub* nativeCallTrampolineStub_at(address addr) {
 520   assert(is_NativeCallTrampolineStub_at(addr), "no call trampoline found");
 521   return (NativeCallTrampolineStub*)addr;
 522 }
 523 
 524 class NativeMembar : public NativeInstruction {
 525 public:
 526   unsigned int get_kind() { return Instruction_aarch64::extract(uint_at(0), 11, 8); }
 527   void set_kind(int order_kind) { Instruction_aarch64::patch(addr_at(0), 11, 8, order_kind); }
 528 };
 529 
 530 inline NativeMembar *NativeMembar_at(address addr) {
 531   assert(nativeInstruction_at(addr)->is_Membar(), "no membar found");
 532   return (NativeMembar*)addr;
 533 }
 534 
 535 #endif // CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP