3078 }
3079 
3080 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3081   assert(isByte(mode), "invalid value");
3082   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3083   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3084   if (VM_Version::supports_evex()) {
3085     tuple_type = EVEX_FVM;
3086   }
3087   InstructionMark im(this);
3088   simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, false, VEX_OPCODE_0F,
3089               false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3090   emit_int8(0x70);
3091   emit_operand(dst, src);
3092   emit_int8(mode & 0xFF);
3093 }
3094 
3095 void Assembler::psrldq(XMMRegister dst, int shift) {
3096   // Shift 128 bit value in xmm register by number of bytes.
3097   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3098   int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F,
3099                                       false, AVX_128bit, (VM_Version::supports_avx512bw() == false));








3100   emit_int8(0x73);
3101   emit_int8((unsigned char)(0xC0 | encode));
3102   emit_int8(shift);
3103 }
3104 
3105 void Assembler::ptest(XMMRegister dst, Address src) {
3106   assert(VM_Version::supports_sse4_1(), "");
3107   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3108   InstructionMark im(this);
3109   simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
3110   emit_int8(0x17);
3111   emit_operand(dst, src);
3112 }
3113 
3114 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3115   assert(VM_Version::supports_sse4_1(), "");
3116   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3117                                       false, VEX_OPCODE_0F_38);
3118   emit_int8(0x17);
3119   emit_int8((unsigned char)(0xC0 | encode));

3078 }
3079 
3080 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3081   assert(isByte(mode), "invalid value");
3082   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3083   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3084   if (VM_Version::supports_evex()) {
3085     tuple_type = EVEX_FVM;
3086   }
3087   InstructionMark im(this);
3088   simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, false, VEX_OPCODE_0F,
3089               false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3090   emit_int8(0x70);
3091   emit_operand(dst, src);
3092   emit_int8(mode & 0xFF);
3093 }
3094 
3095 void Assembler::psrldq(XMMRegister dst, int shift) {
3096   // Shift 128 bit value in xmm register by number of bytes.
3097   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3098   int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3099   emit_int8(0x73);
3100   emit_int8((unsigned char)(0xC0 | encode));
3101   emit_int8(shift);
3102 }
3103 
3104 void Assembler::pslldq(XMMRegister dst, int shift) {
3105   // Shift left 128 bit value in xmm register by number of bytes.
3106   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3107   int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3108   emit_int8(0x73);
3109   emit_int8((unsigned char)(0xC0 | encode));
3110   emit_int8(shift);
3111 }
3112 
3113 void Assembler::ptest(XMMRegister dst, Address src) {
3114   assert(VM_Version::supports_sse4_1(), "");
3115   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3116   InstructionMark im(this);
3117   simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
3118   emit_int8(0x17);
3119   emit_operand(dst, src);
3120 }
3121 
3122 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3123   assert(VM_Version::supports_sse4_1(), "");
3124   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3125                                       false, VEX_OPCODE_0F_38);
3126   emit_int8(0x17);
3127   emit_int8((unsigned char)(0xC0 | encode));