src/cpu/x86/vm/vm_version_x86.cpp

*** 1107,1121 ****
          FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
        }
      }
  
  #ifdef COMPILER2
!     if (MaxVectorSize > 16) {
!       // Limit vectors size to 16 bytes on current AMD cpus.
        FLAG_SET_DEFAULT(MaxVectorSize, 16);
      }
  #endif // COMPILER2
    }
  
    if( is_intel() ) { // Intel cpus specific settings
      if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
        UseStoreImmI16 = false; // don't use it on Intel cpus
--- 1107,1137 ----
          FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
        }
      }
  
  #ifdef COMPILER2
!     if (cpu_family() < 0x17 && MaxVectorSize > 16) {
!       // Limit vectors size to 16 bytes on AMD cpus < 17h.
        FLAG_SET_DEFAULT(MaxVectorSize, 16);
      }
  #endif // COMPILER2
+ 
+     // Some defaults for AMD family 17h
+     if ( cpu_family() == 0x17 ) {
+       // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
+       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
+         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
+       }
+       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
+         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
+       }
+ #ifdef COMPILER2
+       if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
+         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
+       }
+ #endif
+     }
    }
  
    if( is_intel() ) { // Intel cpus specific settings
      if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
        UseStoreImmI16 = false; // don't use it on Intel cpus