src/cpu/x86/vm/vm_version_x86.hpp

*** 503,535 ****
        result |= CPU_ERMS;
      if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
        result |= CPU_CLMUL;
      if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
        result |= CPU_RTM;
  
      // AMD features.
      if (is_amd()) {
        if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
            (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
          result |= CPU_3DNOW_PREFETCH;
        if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
          result |= CPU_LZCNT;
        if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
          result |= CPU_SSE4A;
      }
      // Intel features.
      if(is_intel()) {
-       if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
-          result |= CPU_ADX;
-       if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
-         result |= CPU_BMI2;
-       if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
-         result |= CPU_SHA;
        if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
          result |= CPU_LZCNT;
-       if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
-         result |= CPU_FMA;
        // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
        if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
          result |= CPU_3DNOW_PREFETCH;
        }
      }
--- 503,537 ----
        result |= CPU_ERMS;
      if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
        result |= CPU_CLMUL;
      if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
        result |= CPU_RTM;
+     if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
+        result |= CPU_ADX;
+     if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
+       result |= CPU_BMI2;
+     if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
+       result |= CPU_SHA;
+     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
+       result |= CPU_FMA;
  
      // AMD features.
      if (is_amd()) {
        if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
            (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
          result |= CPU_3DNOW_PREFETCH;
        if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
          result |= CPU_LZCNT;
        if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
          result |= CPU_SSE4A;
+       if(_cpuid_info.std_cpuid1_edx.bits.ht != 0)
+         result |= CPU_HT;
      }
      // Intel features.
      if(is_intel()) {
        if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
          result |= CPU_LZCNT;
        // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
        if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
          result |= CPU_3DNOW_PREFETCH;
        }
      }