1092 // some defaults for AMD family 15h
1093 if ( cpu_family() == 0x15 ) {
1094 // On family 15h processors default is no sw prefetch
1095 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1096 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1097 }
1098 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1099 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1100 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1101 }
1102 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1103 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1104 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1105 }
1106 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1107 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1108 }
1109 }
1110
1111 #ifdef COMPILER2
1112 if (MaxVectorSize > 16) {
1113 // Limit vectors size to 16 bytes on current AMD cpus.
1114 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1115 }
1116 #endif // COMPILER2
1117 }
1118
1119 if( is_intel() ) { // Intel cpus specific settings
1120 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1121 UseStoreImmI16 = false; // don't use it on Intel cpus
1122 }
1123 if( cpu_family() == 6 || cpu_family() == 15 ) {
1124 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1125 // Use it on all Intel cpus starting from PentiumPro
1126 UseAddressNop = true;
1127 }
1128 }
1129 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1130 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1131 }
1132 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1133 if( supports_sse3() ) {
1134 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1135 } else {
1136 UseXmmRegToRegMoveAll = false;
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1092 // some defaults for AMD family 15h
1093 if ( cpu_family() == 0x15 ) {
1094 // On family 15h processors default is no sw prefetch
1095 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1096 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1097 }
1098 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1099 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1100 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1101 }
1102 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1103 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1104 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1105 }
1106 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1107 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1108 }
1109 }
1110
1111 #ifdef COMPILER2
1112 if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1113 // Limit vectors size to 16 bytes on AMD cpus < 17h.
1114 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1115 }
1116 #endif // COMPILER2
1117
1118 // Some defaults for AMD family 17h
1119 if ( cpu_family() == 0x17 ) {
1120 // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1121 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1122 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1123 }
1124 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1125 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1126 }
1127 #ifdef COMPILER2
1128 if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1129 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1130 }
1131 #endif
1132 }
1133 }
1134
1135 if( is_intel() ) { // Intel cpus specific settings
1136 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1137 UseStoreImmI16 = false; // don't use it on Intel cpus
1138 }
1139 if( cpu_family() == 6 || cpu_family() == 15 ) {
1140 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1141 // Use it on all Intel cpus starting from PentiumPro
1142 UseAddressNop = true;
1143 }
1144 }
1145 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1146 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1147 }
1148 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1149 if( supports_sse3() ) {
1150 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1151 } else {
1152 UseXmmRegToRegMoveAll = false;
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