488         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
 489           result |= CPU_AVX512BW;
 490         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
 491           result |= CPU_AVX512VL;
 492       }
 493     }
 494     if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 495       result |= CPU_BMI1;
 496     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 497       result |= CPU_TSC;
 498     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 499       result |= CPU_TSCINV;
 500     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 501       result |= CPU_AES;
 502     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 503       result |= CPU_ERMS;
 504     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 505       result |= CPU_CLMUL;
 506     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 507       result |= CPU_RTM;








 508 
 509     // AMD features.
 510     if (is_amd()) {
 511       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 512           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 513         result |= CPU_3DNOW_PREFETCH;
 514       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 515         result |= CPU_LZCNT;
 516       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 517         result |= CPU_SSE4A;


 518     }
 519     // Intel features.
 520     if(is_intel()) {
 521       if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 522          result |= CPU_ADX;
 523       if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 524         result |= CPU_BMI2;
 525       if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
 526         result |= CPU_SHA;
 527       if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 528         result |= CPU_LZCNT;
 529       if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
 530         result |= CPU_FMA;
 531       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 532       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 533         result |= CPU_3DNOW_PREFETCH;
 534       }
 535     }
 536 
 537     return result;
 538   }
 539 
 540   static bool os_supports_avx_vectors() {
 541     bool retVal = false;
 542     if (supports_evex()) {
 543       // Verify that OS save/restore all bits of EVEX registers
 544       // during signal processing.
 545       int nreg = 2 LP64_ONLY(+2);
 546       retVal = true;
 547       for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 548         if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 549           retVal = false;
 550           break;

 488         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
 489           result |= CPU_AVX512BW;
 490         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
 491           result |= CPU_AVX512VL;
 492       }
 493     }
 494     if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 495       result |= CPU_BMI1;
 496     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 497       result |= CPU_TSC;
 498     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 499       result |= CPU_TSCINV;
 500     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 501       result |= CPU_AES;
 502     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 503       result |= CPU_ERMS;
 504     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 505       result |= CPU_CLMUL;
 506     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 507       result |= CPU_RTM;
 508     if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 509        result |= CPU_ADX;
 510     if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 511       result |= CPU_BMI2;
 512     if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
 513       result |= CPU_SHA;
 514     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
 515       result |= CPU_FMA;
 516 
 517     // AMD features.
 518     if (is_amd()) {
 519       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 520           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 521         result |= CPU_3DNOW_PREFETCH;
 522       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 523         result |= CPU_LZCNT;
 524       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 525         result |= CPU_SSE4A;
 526       if(_cpuid_info.std_cpuid1_edx.bits.ht != 0)
 527         result |= CPU_HT;
 528     }
 529     // Intel features.
 530     if(is_intel()) {






 531       if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 532         result |= CPU_LZCNT;


 533       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 534       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 535         result |= CPU_3DNOW_PREFETCH;
 536       }
 537     }
 538 
 539     return result;
 540   }
 541 
 542   static bool os_supports_avx_vectors() {
 543     bool retVal = false;
 544     if (supports_evex()) {
 545       // Verify that OS save/restore all bits of EVEX registers
 546       // during signal processing.
 547       int nreg = 2 LP64_ONLY(+2);
 548       retVal = true;
 549       for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 550         if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 551           retVal = false;
 552           break;