37 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADR;
38 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADRP;
39 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.AND;
40 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ANDS;
41 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ASRV;
42 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BFM;
43 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BIC;
44 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BICS;
45 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BLR;
46 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BR;
47 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BRK;
48 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CAS;
49 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CCMP;
50 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLREX;
51 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLS;
52 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLZ;
53 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CNT;
54 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSEL;
55 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSINC;
56 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSNEG;
57 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.DMB;
58 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EON;
59 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EOR;
60 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EXTR;
61 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FABS;
62 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FADD;
63 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCCMP;
64 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCMP;
65 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCMPZERO;
66 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCSEL;
67 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTDS;
68 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTSD;
69 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTZS;
70 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FDIV;
71 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMADD;
72 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMOV;
73 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMSUB;
74 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMUL;
75 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FNEG;
76 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FRINTM;
656 FCMP(0x00000000),
657 FCMPZERO(0x00000008),
658 FCCMP(0x1E200400),
659 FCSEL(0x1E200C00),
660
661 INS(0x4e081c00),
662 UMOV(0x0e003c00),
663
664 CNT(0xe205800),
665 USRA(0x6f001400),
666
667 HLT(0x00400000),
668 BRK(0x00200000),
669
670 CLREX(0xd5033f5f),
671 HINT(0xD503201F),
672 DMB(0x000000A0),
673
674 MRS(0xD5300000),
675 MSR(0xD5100000),
676
677 BLR_NATIVE(0xc0000000),
678
679 ADDV(0x0e31b800);
680
681 public final int encoding;
682
683 Instruction(int encoding) {
684 this.encoding = encoding;
685 }
686
687 }
688
689 public enum SystemRegister {
690 FPCR(0b11, 0b011, 0b0100, 0b0100, 0b000),
691 FPSR(0b11, 0b011, 0b0100, 0b0100, 0b001);
692
693 SystemRegister(int op0, int op1, int crn, int crm, int op2) {
694 this.op0 = op0;
695 this.op1 = op1;
696 this.crn = crn;
697 this.crm = crm;
698 this.op2 = op2;
699 }
700
701 public int encoding() {
702 return op0 << 19 | op1 << 16 | crn << 12 | crm << 8 | op2 << 5;
703 }
704
705 private final int op0;
706 private final int op1;
707 private final int crn;
708 private final int crm;
709 private final int op2;
710 }
711
712 public enum ShiftType {
713 LSL(0),
714 LSR(1),
715 ASR(2),
716 ROR(3);
717
718 public final int encoding;
719
720 ShiftType(int encoding) {
721 this.encoding = encoding;
722 }
723 }
724
725 public enum ExtendType {
726 UXTB(0),
727 UXTH(1),
728 UXTW(2),
729 UXTX(3),
730 SXTB(4),
731 SXTH(5),
998 InstructionType type = generalFromSize(size);
999 int encoding = type.encoding | TBZ.encoding | (uimm5 << 19) | (imm14 << 5) | rd(reg);
1000 if (pos == -1) {
1001 emitInt(encoding);
1002 } else {
1003 emitInt(encoding, pos);
1004 }
1005 }
1006
1007 private void conditionalBranchInstruction(Register reg, int imm21, InstructionType type, Instruction instr, int pos) {
1008 assert reg.getRegisterCategory().equals(CPU);
1009 int instrEncoding = instr.encoding | CompareBranchOp;
1010 if (pos == -1) {
1011 emitInt(type.encoding | instrEncoding | getConditionalBranchImm(imm21) | rd(reg));
1012 } else {
1013 emitInt(type.encoding | instrEncoding | getConditionalBranchImm(imm21) | rd(reg), pos);
1014 }
1015 }
1016
1017 private static int getConditionalBranchImm(int imm21) {
1018 assert NumUtil.isSignedNbit(21, imm21) && (imm21 & 0x3) == 0 : "Immediate has to be 21bit signed number and word aligned";
1019 int imm = (imm21 & NumUtil.getNbitNumberInt(21)) >> 2;
1020 return imm << ConditionalBranchImmOffset;
1021 }
1022
1023 /* Unconditional Branch (immediate) (5.2.2) */
1024
1025 /**
1026 * @param imm28 Signed 28-bit offset, has to be word aligned.
1027 */
1028 protected void b(int imm28) {
1029 unconditionalBranchImmInstruction(imm28, Instruction.B, -1);
1030 }
1031
1032 /**
1033 *
1034 * @param imm28 Signed 28-bit offset, has to be word aligned.
1035 * @param pos Position where instruction is inserted into code buffer.
1036 */
1037 protected void b(int imm28, int pos) {
1038 unconditionalBranchImmInstruction(imm28, Instruction.B, pos);
1214 final Register rt = mode.toRegister();
1215 // this looks weird but that's because loadStoreInstruction is weird
1216 // instruction select fields are size [31:30], v [26] and opc [25:24]
1217 // prfm requires size == 0b11, v == 0b0 and opc == 0b11
1218 // passing LDRS ensures opc[1] == 0b1
1219 // (n.b. passing LDR/STR makes no difference to opc[1:0]!!)
1220 // passing General64 ensures opc[0] == 0b1 and v = 0b0
1221 // (n.b. passing General32 ensures opc[0] == 0b0 and v = 0b0)
1222 // srcSize 64 ensures size == 0b11
1223 loadStoreInstruction(LDRS, rt, address, General64, transferSize);
1224 }
1225
1226 /**
1227 * Stores register rt into memory pointed by address.
1228 *
1229 * @param destSize number of bits written to memory. Must be 8, 16, 32 or 64.
1230 * @param rt general purpose register. May not be null or stackpointer.
1231 * @param address all addressing modes allowed. May not be null.
1232 */
1233 public void str(int destSize, Register rt, AArch64Address address) {
1234 assert rt.getRegisterCategory().equals(CPU);
1235 assert destSize == 8 || destSize == 16 || destSize == 32 || destSize == 64;
1236 int transferSize = NumUtil.log2Ceil(destSize / 8);
1237 loadStoreInstruction(STR, rt, address, General64, transferSize);
1238 }
1239
1240 private void loadStoreInstruction(Instruction instr, Register reg, AArch64Address address, InstructionType type, int log2TransferSize) {
1241 assert log2TransferSize >= 0 && log2TransferSize < 4;
1242 int transferSizeEncoding = log2TransferSize << LoadStoreTransferSizeOffset;
1243 int is32Bit = type.width == 32 ? 1 << ImmediateSizeOffset : 0;
1244 int isFloat = !type.isGeneral ? 1 << LoadStoreFpFlagOffset : 0;
1245 int memop = instr.encoding | transferSizeEncoding | is32Bit | isFloat | rt(reg);
1246 switch (address.getAddressingMode()) {
1247 case IMMEDIATE_SCALED:
1248 annotatePatchingImmediate(position(), instr, 12, LoadStoreScaledImmOffset, log2TransferSize);
1249 emitInt(memop | LoadStoreScaledOp | address.getImmediate() << LoadStoreScaledImmOffset | rs1(address.getBase()));
1250 break;
1251 case IMMEDIATE_UNSCALED:
1252 annotatePatchingImmediate(position(), instr, 9, LoadStoreUnscaledImmOffset, 0);
1253 emitInt(memop | LoadStoreUnscaledOp | address.getImmediate() << LoadStoreUnscaledImmOffset | rs1(address.getBase()));
1254 break;
2942 this.encoding = encoding;
2943 this.optionName = optionName;
2944 }
2945 }
2946
2947 /**
2948 * Data Memory Barrier.
2949 *
2950 * @param barrierKind barrier that is issued. May not be null.
2951 */
2952 public void dmb(BarrierKind barrierKind) {
2953 emitInt(DMB.encoding | BarrierOp | barrierKind.encoding << BarrierKindOffset);
2954 }
2955
2956 public void mrs(Register dst, SystemRegister systemRegister) {
2957 emitInt(MRS.encoding | systemRegister.encoding() | rt(dst));
2958 }
2959
2960 public void msr(SystemRegister systemRegister, Register src) {
2961 emitInt(MRS.encoding | systemRegister.encoding() | rt(src));
2962 }
2963
2964 public void annotatePatchingImmediate(int pos, Instruction instruction, int operandSizeBits, int offsetBits, int shift) {
2965 if (codePatchingAnnotationConsumer != null) {
2966 codePatchingAnnotationConsumer.accept(new SingleInstructionAnnotation(pos, instruction, operandSizeBits, offsetBits, shift));
2967 }
2968 }
2969
2970 void annotateImmediateMovSequence(int pos, int numInstrs) {
2971 if (codePatchingAnnotationConsumer != null) {
2972 codePatchingAnnotationConsumer.accept(new MovSequenceAnnotation(pos, numInstrs));
2973 }
2974 }
2975
2976 public static class SingleInstructionAnnotation extends CodeAnnotation {
2977
2978 /**
2979 * The size of the operand, in bytes.
2980 */
2981 public final int operandSizeBits;
|
37 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADR;
38 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADRP;
39 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.AND;
40 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ANDS;
41 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ASRV;
42 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BFM;
43 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BIC;
44 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BICS;
45 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BLR;
46 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BR;
47 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BRK;
48 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CAS;
49 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CCMP;
50 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLREX;
51 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLS;
52 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLZ;
53 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CNT;
54 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSEL;
55 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSINC;
56 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSNEG;
57 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.DC;
58 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.DMB;
59 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EON;
60 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EOR;
61 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EXTR;
62 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FABS;
63 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FADD;
64 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCCMP;
65 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCMP;
66 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCMPZERO;
67 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCSEL;
68 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTDS;
69 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTSD;
70 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTZS;
71 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FDIV;
72 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMADD;
73 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMOV;
74 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMSUB;
75 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMUL;
76 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FNEG;
77 import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FRINTM;
657 FCMP(0x00000000),
658 FCMPZERO(0x00000008),
659 FCCMP(0x1E200400),
660 FCSEL(0x1E200C00),
661
662 INS(0x4e081c00),
663 UMOV(0x0e003c00),
664
665 CNT(0xe205800),
666 USRA(0x6f001400),
667
668 HLT(0x00400000),
669 BRK(0x00200000),
670
671 CLREX(0xd5033f5f),
672 HINT(0xD503201F),
673 DMB(0x000000A0),
674
675 MRS(0xD5300000),
676 MSR(0xD5100000),
677 DC(0xD5087000),
678
679 BLR_NATIVE(0xc0000000),
680
681 ADDV(0x0e31b800);
682
683 public final int encoding;
684
685 Instruction(int encoding) {
686 this.encoding = encoding;
687 }
688
689 }
690
691 public enum SystemRegister {
692 FPCR(0b11, 0b011, 0b0100, 0b0100, 0b000),
693 FPSR(0b11, 0b011, 0b0100, 0b0100, 0b001);
694
695 SystemRegister(int op0, int op1, int crn, int crm, int op2) {
696 this.op0 = op0;
697 this.op1 = op1;
698 this.crn = crn;
699 this.crm = crm;
700 this.op2 = op2;
701 }
702
703 public int encoding() {
704 return op0 << 19 | op1 << 16 | crn << 12 | crm << 8 | op2 << 5;
705 }
706
707 private final int op0;
708 private final int op1;
709 private final int crn;
710 private final int crm;
711 private final int op2;
712 }
713
714 public enum DataCacheOperationType {
715 ZVA(0b011, 0b0100, 0b001);
716
717 DataCacheOperationType(int op1, int crm, int op2) {
718 this.op1 = op1;
719 this.crm = crm;
720 this.op2 = op2;
721 }
722
723 public int encoding() {
724 return op1 << 16 | crm << 8 | op2 << 5;
725 }
726
727 private final int op1;
728 private final int crm;
729 private final int op2;
730 }
731
732 public enum ShiftType {
733 LSL(0),
734 LSR(1),
735 ASR(2),
736 ROR(3);
737
738 public final int encoding;
739
740 ShiftType(int encoding) {
741 this.encoding = encoding;
742 }
743 }
744
745 public enum ExtendType {
746 UXTB(0),
747 UXTH(1),
748 UXTW(2),
749 UXTX(3),
750 SXTB(4),
751 SXTH(5),
1018 InstructionType type = generalFromSize(size);
1019 int encoding = type.encoding | TBZ.encoding | (uimm5 << 19) | (imm14 << 5) | rd(reg);
1020 if (pos == -1) {
1021 emitInt(encoding);
1022 } else {
1023 emitInt(encoding, pos);
1024 }
1025 }
1026
1027 private void conditionalBranchInstruction(Register reg, int imm21, InstructionType type, Instruction instr, int pos) {
1028 assert reg.getRegisterCategory().equals(CPU);
1029 int instrEncoding = instr.encoding | CompareBranchOp;
1030 if (pos == -1) {
1031 emitInt(type.encoding | instrEncoding | getConditionalBranchImm(imm21) | rd(reg));
1032 } else {
1033 emitInt(type.encoding | instrEncoding | getConditionalBranchImm(imm21) | rd(reg), pos);
1034 }
1035 }
1036
1037 private static int getConditionalBranchImm(int imm21) {
1038 assert NumUtil.isSignedNbit(21, imm21) && (imm21 & 0x3) == 0 : String.format("Immediate has to be 21bit signed number and word aligned got value 0x%x", imm21);
1039 int imm = (imm21 & NumUtil.getNbitNumberInt(21)) >> 2;
1040 return imm << ConditionalBranchImmOffset;
1041 }
1042
1043 /* Unconditional Branch (immediate) (5.2.2) */
1044
1045 /**
1046 * @param imm28 Signed 28-bit offset, has to be word aligned.
1047 */
1048 protected void b(int imm28) {
1049 unconditionalBranchImmInstruction(imm28, Instruction.B, -1);
1050 }
1051
1052 /**
1053 *
1054 * @param imm28 Signed 28-bit offset, has to be word aligned.
1055 * @param pos Position where instruction is inserted into code buffer.
1056 */
1057 protected void b(int imm28, int pos) {
1058 unconditionalBranchImmInstruction(imm28, Instruction.B, pos);
1234 final Register rt = mode.toRegister();
1235 // this looks weird but that's because loadStoreInstruction is weird
1236 // instruction select fields are size [31:30], v [26] and opc [25:24]
1237 // prfm requires size == 0b11, v == 0b0 and opc == 0b11
1238 // passing LDRS ensures opc[1] == 0b1
1239 // (n.b. passing LDR/STR makes no difference to opc[1:0]!!)
1240 // passing General64 ensures opc[0] == 0b1 and v = 0b0
1241 // (n.b. passing General32 ensures opc[0] == 0b0 and v = 0b0)
1242 // srcSize 64 ensures size == 0b11
1243 loadStoreInstruction(LDRS, rt, address, General64, transferSize);
1244 }
1245
1246 /**
1247 * Stores register rt into memory pointed by address.
1248 *
1249 * @param destSize number of bits written to memory. Must be 8, 16, 32 or 64.
1250 * @param rt general purpose register. May not be null or stackpointer.
1251 * @param address all addressing modes allowed. May not be null.
1252 */
1253 public void str(int destSize, Register rt, AArch64Address address) {
1254 assert rt.getRegisterCategory().equals(CPU) : rt;
1255 assert destSize == 8 || destSize == 16 || destSize == 32 || destSize == 64;
1256 int transferSize = NumUtil.log2Ceil(destSize / 8);
1257 loadStoreInstruction(STR, rt, address, General64, transferSize);
1258 }
1259
1260 private void loadStoreInstruction(Instruction instr, Register reg, AArch64Address address, InstructionType type, int log2TransferSize) {
1261 assert log2TransferSize >= 0 && log2TransferSize < 4;
1262 int transferSizeEncoding = log2TransferSize << LoadStoreTransferSizeOffset;
1263 int is32Bit = type.width == 32 ? 1 << ImmediateSizeOffset : 0;
1264 int isFloat = !type.isGeneral ? 1 << LoadStoreFpFlagOffset : 0;
1265 int memop = instr.encoding | transferSizeEncoding | is32Bit | isFloat | rt(reg);
1266 switch (address.getAddressingMode()) {
1267 case IMMEDIATE_SCALED:
1268 annotatePatchingImmediate(position(), instr, 12, LoadStoreScaledImmOffset, log2TransferSize);
1269 emitInt(memop | LoadStoreScaledOp | address.getImmediate() << LoadStoreScaledImmOffset | rs1(address.getBase()));
1270 break;
1271 case IMMEDIATE_UNSCALED:
1272 annotatePatchingImmediate(position(), instr, 9, LoadStoreUnscaledImmOffset, 0);
1273 emitInt(memop | LoadStoreUnscaledOp | address.getImmediate() << LoadStoreUnscaledImmOffset | rs1(address.getBase()));
1274 break;
2962 this.encoding = encoding;
2963 this.optionName = optionName;
2964 }
2965 }
2966
2967 /**
2968 * Data Memory Barrier.
2969 *
2970 * @param barrierKind barrier that is issued. May not be null.
2971 */
2972 public void dmb(BarrierKind barrierKind) {
2973 emitInt(DMB.encoding | BarrierOp | barrierKind.encoding << BarrierKindOffset);
2974 }
2975
2976 public void mrs(Register dst, SystemRegister systemRegister) {
2977 emitInt(MRS.encoding | systemRegister.encoding() | rt(dst));
2978 }
2979
2980 public void msr(SystemRegister systemRegister, Register src) {
2981 emitInt(MRS.encoding | systemRegister.encoding() | rt(src));
2982 }
2983
2984 public void dc(DataCacheOperationType type, Register src) {
2985 emitInt(DC.encoding | type.encoding() | rt(src));
2986 }
2987
2988 public void annotatePatchingImmediate(int pos, Instruction instruction, int operandSizeBits, int offsetBits, int shift) {
2989 if (codePatchingAnnotationConsumer != null) {
2990 codePatchingAnnotationConsumer.accept(new SingleInstructionAnnotation(pos, instruction, operandSizeBits, offsetBits, shift));
2991 }
2992 }
2993
2994 void annotateImmediateMovSequence(int pos, int numInstrs) {
2995 if (codePatchingAnnotationConsumer != null) {
2996 codePatchingAnnotationConsumer.accept(new MovSequenceAnnotation(pos, numInstrs));
2997 }
2998 }
2999
3000 public static class SingleInstructionAnnotation extends CodeAnnotation {
3001
3002 /**
3003 * The size of the operand, in bytes.
3004 */
3005 public final int operandSizeBits;
|