1689 switch (type) {
1690 case BRANCH_CONDITIONALLY:
1691 ConditionFlag cf = ConditionFlag.fromEncoding(instruction >>> PatchLabelKind.INFORMATION_OFFSET);
1692 super.b(cf, branchOffset, branch);
1693 break;
1694 case BRANCH_UNCONDITIONALLY:
1695 super.b(branchOffset, branch);
1696 break;
1697 case JUMP_ADDRESS:
1698 int offset = instruction >>> PatchLabelKind.INFORMATION_OFFSET;
1699 emitInt(jumpTarget - offset, branch);
1700 break;
1701 case BRANCH_NONZERO:
1702 case BRANCH_ZERO: {
1703 int information = instruction >>> PatchLabelKind.INFORMATION_OFFSET;
1704 int sizeEncoding = information & 1;
1705 int regEncoding = information >>> 1;
1706 Register reg = AArch64.cpuRegisters.get(regEncoding);
1707 // 1 => 64; 0 => 32
1708 int size = sizeEncoding * 32 + 32;
1709 switch (type) {
1710 case BRANCH_NONZERO:
1711 super.cbnz(size, reg, branchOffset, branch);
1712 break;
1713 case BRANCH_ZERO:
1714 super.cbz(size, reg, branchOffset, branch);
1715 break;
1716 }
1717 break;
1718 }
1719 case BRANCH_BIT_NONZERO:
1720 case BRANCH_BIT_ZERO: {
1721 int information = instruction >>> PatchLabelKind.INFORMATION_OFFSET;
1722 int sizeEncoding = information & NumUtil.getNbitNumberInt(6);
1723 int regEncoding = information >>> 6;
1724 Register reg = AArch64.cpuRegisters.get(regEncoding);
1725 if (!NumUtil.isSignedNbit(16, branchOffset)) {
1726 throw new BranchTargetOutOfBoundsException(true, "Branch target %d out of bounds", branchOffset);
1727 }
1728 switch (type) {
|
1689 switch (type) {
1690 case BRANCH_CONDITIONALLY:
1691 ConditionFlag cf = ConditionFlag.fromEncoding(instruction >>> PatchLabelKind.INFORMATION_OFFSET);
1692 super.b(cf, branchOffset, branch);
1693 break;
1694 case BRANCH_UNCONDITIONALLY:
1695 super.b(branchOffset, branch);
1696 break;
1697 case JUMP_ADDRESS:
1698 int offset = instruction >>> PatchLabelKind.INFORMATION_OFFSET;
1699 emitInt(jumpTarget - offset, branch);
1700 break;
1701 case BRANCH_NONZERO:
1702 case BRANCH_ZERO: {
1703 int information = instruction >>> PatchLabelKind.INFORMATION_OFFSET;
1704 int sizeEncoding = information & 1;
1705 int regEncoding = information >>> 1;
1706 Register reg = AArch64.cpuRegisters.get(regEncoding);
1707 // 1 => 64; 0 => 32
1708 int size = sizeEncoding * 32 + 32;
1709 if (!NumUtil.isSignedNbit(21, branchOffset)) {
1710 throw new BranchTargetOutOfBoundsException(true, "Branch target %d out of bounds", branchOffset);
1711 }
1712 switch (type) {
1713 case BRANCH_NONZERO:
1714 super.cbnz(size, reg, branchOffset, branch);
1715 break;
1716 case BRANCH_ZERO:
1717 super.cbz(size, reg, branchOffset, branch);
1718 break;
1719 }
1720 break;
1721 }
1722 case BRANCH_BIT_NONZERO:
1723 case BRANCH_BIT_ZERO: {
1724 int information = instruction >>> PatchLabelKind.INFORMATION_OFFSET;
1725 int sizeEncoding = information & NumUtil.getNbitNumberInt(6);
1726 int regEncoding = information >>> 6;
1727 Register reg = AArch64.cpuRegisters.get(regEncoding);
1728 if (!NumUtil.isSignedNbit(16, branchOffset)) {
1729 throw new BranchTargetOutOfBoundsException(true, "Branch target %d out of bounds", branchOffset);
1730 }
1731 switch (type) {
|