15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 */
23 package jdk.vm.ci.sparc;
24
25 import static java.nio.ByteOrder.BIG_ENDIAN;
26 import static jdk.vm.ci.code.MemoryBarriers.LOAD_LOAD;
27 import static jdk.vm.ci.code.MemoryBarriers.LOAD_STORE;
28 import static jdk.vm.ci.code.MemoryBarriers.STORE_STORE;
29
30 import java.util.Set;
31
32 import jdk.vm.ci.code.Architecture;
33 import jdk.vm.ci.code.Register;
34 import jdk.vm.ci.code.Register.RegisterCategory;
35 import jdk.vm.ci.meta.JavaKind;
36 import jdk.vm.ci.meta.PlatformKind;
37
38 /**
39 * Represents the SPARC architecture.
40 */
41 public class SPARC extends Architecture {
42
43 public static final RegisterCategory CPU = new RegisterCategory("CPU");
44 public static final RegisterCategory FPUs = new RegisterCategory("FPUs");
45 public static final RegisterCategory FPUd = new RegisterCategory("FPUd");
46 public static final RegisterCategory FPUq = new RegisterCategory("FPUq");
47
48 // General purpose registers
49 public static final Register g0 = new Register(0, 0, "g0", CPU);
50 public static final Register g1 = new Register(1, 1, "g1", CPU);
51 public static final Register g2 = new Register(2, 2, "g2", CPU);
52 public static final Register g3 = new Register(3, 3, "g3", CPU);
53 public static final Register g4 = new Register(4, 4, "g4", CPU);
54 public static final Register g5 = new Register(5, 5, "g5", CPU);
162 // Quad precision registers
163 public static final Register q0 = new Register(96, getQuadncoding(0), "q0", FPUq);
164 public static final Register q4 = new Register(97, getQuadncoding(4), "q4", FPUq);
165 public static final Register q8 = new Register(98, getQuadncoding(8), "q8", FPUq);
166 public static final Register q12 = new Register(99, getQuadncoding(12), "q12", FPUq);
167 public static final Register q16 = new Register(100, getQuadncoding(16), "q16", FPUq);
168 public static final Register q20 = new Register(101, getQuadncoding(20), "q20", FPUq);
169 public static final Register q24 = new Register(102, getQuadncoding(24), "q24", FPUq);
170 public static final Register q28 = new Register(103, getQuadncoding(28), "q28", FPUq);
171
172 public static final Register q32 = new Register(104, getQuadncoding(32), "q32", FPUq);
173 public static final Register q36 = new Register(105, getQuadncoding(36), "q36", FPUq);
174 public static final Register q40 = new Register(106, getQuadncoding(40), "q40", FPUq);
175 public static final Register q44 = new Register(107, getQuadncoding(44), "q44", FPUq);
176 public static final Register q48 = new Register(108, getQuadncoding(48), "q48", FPUq);
177 public static final Register q52 = new Register(109, getQuadncoding(52), "q52", FPUq);
178 public static final Register q56 = new Register(110, getQuadncoding(56), "q56", FPUq);
179 public static final Register q60 = new Register(111, getQuadncoding(60), "q60", FPUq);
180
181 // @formatter:off
182 public static final Register[] cpuRegisters = {
183 g0, g1, g2, g3, g4, g5, g6, g7,
184 o0, o1, o2, o3, o4, o5, o6, o7,
185 l0, l1, l2, l3, l4, l5, l6, l7,
186 i0, i1, i2, i3, i4, i5, i6, i7
187 };
188
189 public static final Register[] fpusRegisters = {
190 f0, f1, f2, f3, f4, f5, f6, f7,
191 f8, f9, f10, f11, f12, f13, f14, f15,
192 f16, f17, f18, f19, f20, f21, f22, f23,
193 f24, f25, f26, f27, f28, f29, f30, f31
194 };
195
196 public static final Register[] fpudRegisters = {
197 d0, d2, d4, d6, d8, d10, d12, d14,
198 d16, d18, d20, d22, d24, d26, d28, d30,
199 d32, d34, d36, d38, d40, d42, d44, d46,
200 d48, d50, d52, d54, d56, d58, d60, d62
201 };
202
203 public static final Register[] fpuqRegisters = {
204 q0, q4, q8, q12,
205 q16, q20, q24, q28,
206 q32, q36, q40, q44,
207 q48, q52, q56, q60,
208 };
209
210 public static final Register[] allRegisters = {
211 g0, g1, g2, g3, g4, g5, g6, g7,
212 o0, o1, o2, o3, o4, o5, o6, o7,
213 l0, l1, l2, l3, l4, l5, l6, l7,
214 i0, i1, i2, i3, i4, i5, i6, i7,
215
216 f0, f1, f2, f3, f4, f5, f6, f7,
217 f8, f9, f10, f11, f12, f13, f14, f15,
218 f16, f17, f18, f19, f20, f21, f22, f23,
219 f24, f25, f26, f27, f28, f29, f30, f31,
220
221 d0, d2, d4, d6, d8, d10, d12, d14,
222 d16, d18, d20, d22, d24, d26, d28, d30,
223 d32, d34, d36, d38, d40, d42, d44, d46,
224 d48, d50, d52, d54, d56, d58, d60, d62,
225
226 q0, q4, q8, q12,
227 q16, q20, q24, q28,
228 q32, q36, q40, q44,
229 q48, q52, q56, q60,
230 };
231 // @formatter:on
232
233 /**
234 * Stack bias for stack and frame pointer loads.
235 */
236 public static final int STACK_BIAS = 0x7ff;
237
238 /**
239 * Size to keep free for flushing the register-window to stack.
240 */
241 public static final int REGISTER_SAFE_AREA_SIZE = 128;
242
243 public final Set<CPUFeature> features;
244
245 public SPARC(Set<CPUFeature> features) {
246 super("SPARC", SPARCKind.XWORD, BIG_ENDIAN, false, allRegisters, LOAD_LOAD | LOAD_STORE | STORE_STORE, 1, 8);
247 this.features = features;
248 }
249
250 @Override
251 public Register[] getAvailableValueRegisters() {
252 return allRegisters;
253 }
254
255 @Override
256 public boolean canStoreValue(RegisterCategory category, PlatformKind kind) {
257 SPARCKind sparcKind = (SPARCKind) kind;
258 switch (sparcKind) {
259 case BYTE:
260 case HWORD:
261 case WORD:
262 case XWORD:
263 return CPU.equals(category);
264 case SINGLE:
265 case V32_BYTE:
266 case V32_HWORD:
267 return FPUs.equals(category);
268 case DOUBLE:
269 case V64_BYTE:
270 case V64_HWORD:
271 case V64_WORD:
|
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 */
23 package jdk.vm.ci.sparc;
24
25 import static java.nio.ByteOrder.BIG_ENDIAN;
26 import static jdk.vm.ci.code.MemoryBarriers.LOAD_LOAD;
27 import static jdk.vm.ci.code.MemoryBarriers.LOAD_STORE;
28 import static jdk.vm.ci.code.MemoryBarriers.STORE_STORE;
29
30 import java.util.Set;
31
32 import jdk.vm.ci.code.Architecture;
33 import jdk.vm.ci.code.Register;
34 import jdk.vm.ci.code.Register.RegisterCategory;
35 import jdk.vm.ci.code.RegisterArray;
36 import jdk.vm.ci.meta.JavaKind;
37 import jdk.vm.ci.meta.PlatformKind;
38
39 /**
40 * Represents the SPARC architecture.
41 */
42 public class SPARC extends Architecture {
43
44 public static final RegisterCategory CPU = new RegisterCategory("CPU");
45 public static final RegisterCategory FPUs = new RegisterCategory("FPUs");
46 public static final RegisterCategory FPUd = new RegisterCategory("FPUd");
47 public static final RegisterCategory FPUq = new RegisterCategory("FPUq");
48
49 // General purpose registers
50 public static final Register g0 = new Register(0, 0, "g0", CPU);
51 public static final Register g1 = new Register(1, 1, "g1", CPU);
52 public static final Register g2 = new Register(2, 2, "g2", CPU);
53 public static final Register g3 = new Register(3, 3, "g3", CPU);
54 public static final Register g4 = new Register(4, 4, "g4", CPU);
55 public static final Register g5 = new Register(5, 5, "g5", CPU);
163 // Quad precision registers
164 public static final Register q0 = new Register(96, getQuadncoding(0), "q0", FPUq);
165 public static final Register q4 = new Register(97, getQuadncoding(4), "q4", FPUq);
166 public static final Register q8 = new Register(98, getQuadncoding(8), "q8", FPUq);
167 public static final Register q12 = new Register(99, getQuadncoding(12), "q12", FPUq);
168 public static final Register q16 = new Register(100, getQuadncoding(16), "q16", FPUq);
169 public static final Register q20 = new Register(101, getQuadncoding(20), "q20", FPUq);
170 public static final Register q24 = new Register(102, getQuadncoding(24), "q24", FPUq);
171 public static final Register q28 = new Register(103, getQuadncoding(28), "q28", FPUq);
172
173 public static final Register q32 = new Register(104, getQuadncoding(32), "q32", FPUq);
174 public static final Register q36 = new Register(105, getQuadncoding(36), "q36", FPUq);
175 public static final Register q40 = new Register(106, getQuadncoding(40), "q40", FPUq);
176 public static final Register q44 = new Register(107, getQuadncoding(44), "q44", FPUq);
177 public static final Register q48 = new Register(108, getQuadncoding(48), "q48", FPUq);
178 public static final Register q52 = new Register(109, getQuadncoding(52), "q52", FPUq);
179 public static final Register q56 = new Register(110, getQuadncoding(56), "q56", FPUq);
180 public static final Register q60 = new Register(111, getQuadncoding(60), "q60", FPUq);
181
182 // @formatter:off
183 public static final RegisterArray cpuRegisters = new RegisterArray(
184 g0, g1, g2, g3, g4, g5, g6, g7,
185 o0, o1, o2, o3, o4, o5, o6, o7,
186 l0, l1, l2, l3, l4, l5, l6, l7,
187 i0, i1, i2, i3, i4, i5, i6, i7
188 );
189
190 public static final RegisterArray fpusRegisters = new RegisterArray(
191 f0, f1, f2, f3, f4, f5, f6, f7,
192 f8, f9, f10, f11, f12, f13, f14, f15,
193 f16, f17, f18, f19, f20, f21, f22, f23,
194 f24, f25, f26, f27, f28, f29, f30, f31
195 );
196
197 public static final RegisterArray fpudRegisters = new RegisterArray(
198 d0, d2, d4, d6, d8, d10, d12, d14,
199 d16, d18, d20, d22, d24, d26, d28, d30,
200 d32, d34, d36, d38, d40, d42, d44, d46,
201 d48, d50, d52, d54, d56, d58, d60, d62
202 );
203
204 public static final RegisterArray fpuqRegisters = new RegisterArray(
205 q0, q4, q8, q12,
206 q16, q20, q24, q28,
207 q32, q36, q40, q44,
208 q48, q52, q56, q60
209 );
210
211 public static final RegisterArray allRegisters = new RegisterArray(
212 g0, g1, g2, g3, g4, g5, g6, g7,
213 o0, o1, o2, o3, o4, o5, o6, o7,
214 l0, l1, l2, l3, l4, l5, l6, l7,
215 i0, i1, i2, i3, i4, i5, i6, i7,
216
217 f0, f1, f2, f3, f4, f5, f6, f7,
218 f8, f9, f10, f11, f12, f13, f14, f15,
219 f16, f17, f18, f19, f20, f21, f22, f23,
220 f24, f25, f26, f27, f28, f29, f30, f31,
221
222 d0, d2, d4, d6, d8, d10, d12, d14,
223 d16, d18, d20, d22, d24, d26, d28, d30,
224 d32, d34, d36, d38, d40, d42, d44, d46,
225 d48, d50, d52, d54, d56, d58, d60, d62,
226
227 q0, q4, q8, q12,
228 q16, q20, q24, q28,
229 q32, q36, q40, q44,
230 q48, q52, q56, q60
231 );
232 // @formatter:on
233
234 /**
235 * Stack bias for stack and frame pointer loads.
236 */
237 public static final int STACK_BIAS = 0x7ff;
238
239 /**
240 * Size to keep free for flushing the register-window to stack.
241 */
242 public static final int REGISTER_SAFE_AREA_SIZE = 128;
243
244 public final Set<CPUFeature> features;
245
246 public SPARC(Set<CPUFeature> features) {
247 super("SPARC", SPARCKind.XWORD, BIG_ENDIAN, false, allRegisters, LOAD_LOAD | LOAD_STORE | STORE_STORE, 1, 8);
248 this.features = features;
249 }
250
251 @Override
252 public RegisterArray getAvailableValueRegisters() {
253 return allRegisters;
254 }
255
256 @Override
257 public boolean canStoreValue(RegisterCategory category, PlatformKind kind) {
258 SPARCKind sparcKind = (SPARCKind) kind;
259 switch (sparcKind) {
260 case BYTE:
261 case HWORD:
262 case WORD:
263 case XWORD:
264 return CPU.equals(category);
265 case SINGLE:
266 case V32_BYTE:
267 case V32_HWORD:
268 return FPUs.equals(category);
269 case DOUBLE:
270 case V64_BYTE:
271 case V64_HWORD:
272 case V64_WORD:
|