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src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
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rev 8079 : 8079203: AARCH64: Need to cater for different partner implementations
Summary: Parse /proc/cpuinfo to derive implementation specific info
Reviewed-by: aph
@@ -404,10 +404,22 @@
}
inline void umull(Register Rd, Register Rn, Register Rm) {
umaddl(Rd, Rn, Rm, zr);
}
+#define WRAP(INSN) \
+ void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
+ if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \
+ nop(); \
+ Assembler::INSN(Rd, Rn, Rm, Ra); \
+ }
+
+ WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
+ WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
+#undef WRAP
+
+
// macro assembly operations needed for aarch64
// first two private routines for loading 32 bit or 64 bit constants
private:
@@ -1093,13 +1105,10 @@
}
address read_polling_page(Register r, address page, relocInfo::relocType rtype);
address read_polling_page(Register r, relocInfo::relocType rtype);
- // Used by aarch64.ad to control code generation
- static bool use_acq_rel_for_volatile_fields();
-
// CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
void update_byte_crc32(Register crc, Register val, Register table);
void update_word_crc32(Register crc, Register v, Register tmp,
Register table0, Register table1, Register table2, Register table3,
bool upper = false);
@@ -1124,14 +1133,10 @@
// ISB may be needed because of a safepoint
void maybe_isb() { isb(); }
};
-// Used by aarch64.ad to control code generation
-#define treat_as_volatile(MEM_NODE) \
- (MacroAssembler::use_acq_rel_for_volatile_fields() ? (MEM_NODE)->is_volatile() : false)
-
#ifdef ASSERT
inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
#endif
/**
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