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src/cpu/aarch64/vm/aarch64.ad

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rev 9026 : 8138583: aarch64: add support for vectorizing fabs/fneg
Reviewed-by: aph


15206             as_FloatRegister($src1$$reg),
15207             as_FloatRegister($src2$$reg));
15208   %}
15209   ins_pipe(pipe_class_default);
15210 %}
15211 
15212 // --------------------------------- SQRT -------------------------------------
15213 
15214 instruct vsqrt2D(vecX dst, vecX src)
15215 %{
15216   predicate(n->as_Vector()->length() == 2);
15217   match(Set dst (SqrtVD src));
15218   format %{ "fsqrt  $dst, $src\t# vector (2D)" %}
15219   ins_encode %{
15220     __ fsqrt(as_FloatRegister($dst$$reg), __ T2D,
15221              as_FloatRegister($src$$reg));
15222   %}
15223   ins_pipe(pipe_class_default);
15224 %}
15225 


















































































15226 // --------------------------------- AND --------------------------------------
15227 
15228 instruct vand8B(vecD dst, vecD src1, vecD src2)
15229 %{
15230   predicate(n->as_Vector()->length_in_bytes() == 4 ||
15231             n->as_Vector()->length_in_bytes() == 8);
15232   match(Set dst (AndV src1 src2));
15233   ins_cost(INSN_COST);
15234   format %{ "and  $dst,$src1,$src2\t# vector (8B)" %}
15235   ins_encode %{
15236     __ andr(as_FloatRegister($dst$$reg), __ T8B,
15237             as_FloatRegister($src1$$reg),
15238             as_FloatRegister($src2$$reg));
15239   %}
15240   ins_pipe(pipe_class_default);
15241 %}
15242 
15243 instruct vand16B(vecX dst, vecX src1, vecX src2)
15244 %{
15245   predicate(n->as_Vector()->length_in_bytes() == 16);




15206             as_FloatRegister($src1$$reg),
15207             as_FloatRegister($src2$$reg));
15208   %}
15209   ins_pipe(pipe_class_default);
15210 %}
15211 
15212 // --------------------------------- SQRT -------------------------------------
15213 
15214 instruct vsqrt2D(vecX dst, vecX src)
15215 %{
15216   predicate(n->as_Vector()->length() == 2);
15217   match(Set dst (SqrtVD src));
15218   format %{ "fsqrt  $dst, $src\t# vector (2D)" %}
15219   ins_encode %{
15220     __ fsqrt(as_FloatRegister($dst$$reg), __ T2D,
15221              as_FloatRegister($src$$reg));
15222   %}
15223   ins_pipe(pipe_class_default);
15224 %}
15225 
15226 // --------------------------------- ABS --------------------------------------
15227 
15228 instruct vabs2F(vecD dst, vecD src)
15229 %{
15230   predicate(n->as_Vector()->length() == 2);
15231   match(Set dst (AbsVF src));
15232   ins_cost(INSN_COST * 3);
15233   format %{ "fabs  $dst,$src\t# vector (2S)" %}
15234   ins_encode %{
15235     __ fabs(as_FloatRegister($dst$$reg), __ T2S,
15236             as_FloatRegister($src$$reg));
15237   %}
15238   ins_pipe(pipe_class_default);
15239 %}
15240 
15241 instruct vabs4F(vecX dst, vecX src)
15242 %{
15243   predicate(n->as_Vector()->length() == 4);
15244   match(Set dst (AbsVF src));
15245   ins_cost(INSN_COST * 3);
15246   format %{ "fabs  $dst,$src\t# vector (4S)" %}
15247   ins_encode %{
15248     __ fabs(as_FloatRegister($dst$$reg), __ T4S,
15249             as_FloatRegister($src$$reg));
15250   %}
15251   ins_pipe(pipe_class_default);
15252 %}
15253 
15254 instruct vabs2D(vecX dst, vecX src)
15255 %{
15256   predicate(n->as_Vector()->length() == 2);
15257   match(Set dst (AbsVD src));
15258   ins_cost(INSN_COST * 3);
15259   format %{ "fabs  $dst,$src\t# vector (2D)" %}
15260   ins_encode %{
15261     __ fabs(as_FloatRegister($dst$$reg), __ T2D,
15262             as_FloatRegister($src$$reg));
15263   %}
15264   ins_pipe(pipe_class_default);
15265 %}
15266 
15267 // --------------------------------- NEG --------------------------------------
15268 
15269 instruct vneg2F(vecD dst, vecD src)
15270 %{
15271   predicate(n->as_Vector()->length() == 2);
15272   match(Set dst (NegVF src));
15273   ins_cost(INSN_COST * 3);
15274   format %{ "fneg  $dst,$src\t# vector (2S)" %}
15275   ins_encode %{
15276     __ fneg(as_FloatRegister($dst$$reg), __ T2S,
15277             as_FloatRegister($src$$reg));
15278   %}
15279   ins_pipe(pipe_class_default);
15280 %}
15281 
15282 instruct vneg4F(vecX dst, vecX src)
15283 %{
15284   predicate(n->as_Vector()->length() == 4);
15285   match(Set dst (NegVF src));
15286   ins_cost(INSN_COST * 3);
15287   format %{ "fneg  $dst,$src\t# vector (4S)" %}
15288   ins_encode %{
15289     __ fneg(as_FloatRegister($dst$$reg), __ T4S,
15290             as_FloatRegister($src$$reg));
15291   %}
15292   ins_pipe(pipe_class_default);
15293 %}
15294 
15295 instruct vneg2D(vecX dst, vecX src)
15296 %{
15297   predicate(n->as_Vector()->length() == 2);
15298   match(Set dst (NegVD src));
15299   ins_cost(INSN_COST * 3);
15300   format %{ "fneg  $dst,$src\t# vector (2D)" %}
15301   ins_encode %{
15302     __ fneg(as_FloatRegister($dst$$reg), __ T2D,
15303             as_FloatRegister($src$$reg));
15304   %}
15305   ins_pipe(pipe_class_default);
15306 %}
15307 
15308 // --------------------------------- AND --------------------------------------
15309 
15310 instruct vand8B(vecD dst, vecD src1, vecD src2)
15311 %{
15312   predicate(n->as_Vector()->length_in_bytes() == 4 ||
15313             n->as_Vector()->length_in_bytes() == 8);
15314   match(Set dst (AndV src1 src2));
15315   ins_cost(INSN_COST);
15316   format %{ "and  $dst,$src1,$src2\t# vector (8B)" %}
15317   ins_encode %{
15318     __ andr(as_FloatRegister($dst$$reg), __ T8B,
15319             as_FloatRegister($src1$$reg),
15320             as_FloatRegister($src2$$reg));
15321   %}
15322   ins_pipe(pipe_class_default);
15323 %}
15324 
15325 instruct vand16B(vecX dst, vecX src1, vecX src2)
15326 %{
15327   predicate(n->as_Vector()->length_in_bytes() == 16);


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