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src/cpu/aarch64/vm/assembler_aarch64.hpp

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rev 9026 : 8138583: aarch64: add support for vectorizing fabs/fneg
Reviewed-by: aph


2296 
2297   INSN(tbl, 0);
2298   INSN(tbx, 1);
2299 
2300 #undef INSN
2301 
2302   // AdvSIMD two-reg misc
2303 #define INSN(NAME, U, opcode)                                                       \
2304   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {               \
2305        starti;                                                                      \
2306        assert((ASSERTION), MSG);                                                    \
2307        f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24);                   \
2308        f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12);             \
2309        f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0);                                       \
2310  }
2311 
2312 #define MSG "invalid arrangement"
2313 
2314 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2315   INSN(fsqrt, 1, 0b11111);


2316 #undef ASSERTION
2317 
2318 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2319   INSN(rev64, 0, 0b00000);
2320 #undef ASSERTION
2321 
2322 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2323   INSN(rev32, 1, 0b00000);
2324 private:
2325   INSN(_rbit, 1, 0b00101);
2326 public:
2327 
2328 #undef ASSERTION
2329 
2330 #define ASSERTION (T == T8B || T == T16B)
2331   INSN(rev16, 0, 0b00001);
2332   // RBIT only allows T8B and T16B but encodes them oddly.  Argh...
2333   void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
2334     assert((ASSERTION), MSG);
2335     _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn);




2296 
2297   INSN(tbl, 0);
2298   INSN(tbx, 1);
2299 
2300 #undef INSN
2301 
2302   // AdvSIMD two-reg misc
2303 #define INSN(NAME, U, opcode)                                                       \
2304   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {               \
2305        starti;                                                                      \
2306        assert((ASSERTION), MSG);                                                    \
2307        f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24);                   \
2308        f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12);             \
2309        f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0);                                       \
2310  }
2311 
2312 #define MSG "invalid arrangement"
2313 
2314 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2315   INSN(fsqrt, 1, 0b11111);
2316   INSN(fabs,  0, 0b01111);
2317   INSN(fneg,  1, 0b01111);
2318 #undef ASSERTION
2319 
2320 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2321   INSN(rev64, 0, 0b00000);
2322 #undef ASSERTION
2323 
2324 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2325   INSN(rev32, 1, 0b00000);
2326 private:
2327   INSN(_rbit, 1, 0b00101);
2328 public:
2329 
2330 #undef ASSERTION
2331 
2332 #define ASSERTION (T == T8B || T == T16B)
2333   INSN(rev16, 0, 0b00001);
2334   // RBIT only allows T8B and T16B but encodes them oddly.  Argh...
2335   void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
2336     assert((ASSERTION), MSG);
2337     _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn);


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