src/cpu/aarch64/vm/macroAssembler_aarch64.hpp

rev 12409 : 8169177: aarch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
Summary: Add zero-initialization to C1 for fast TLAB refills
Reviewed-by: aph, drwhite
Contributed-by: kavitha.natarajan@linaro.org

*** 855,864 ****
--- 855,865 ----
      Register t1,                       // temp register
      Register t2,                       // temp register
      Label&   slow_case                 // continuation point if fast allocation fails
    );
    Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
+   void zero_memory(Register addr, Register len, Register t1);
    void verify_tlab();
  
    void incr_allocated_bytes(Register thread,
                              Register var_size_in_bytes, int con_size_in_bytes,
                              Register t1 = noreg);