6753 effect(KILL cr); // R1 is killed, too.
6754 ins_cost(3 * DEFAULT_COST);
6755 size(14);
6756 format %{ "SLL $dst,$src,[$nbits] & 31\t# use RISC-like SLLG also for int" %}
6757 ins_encode %{
6758 __ z_lgr(Z_R1_scratch, $nbits$$Register);
6759 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6760 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
6761 %}
6762 ins_pipe(pipe_class_dummy);
6763 %}
6764
6765 // Register Shift Left Immediate
6766 // Constant shift count is masked in ideal graph already.
6767 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
6768 match(Set dst (LShiftI src nbits));
6769 size(6);
6770 format %{ "SLL $dst,$src,$nbits\t# use RISC-like SLLG also for int" %}
6771 ins_encode %{
6772 int Nbit = $nbits$$constant;
6773 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6774 %}
6775 ins_pipe(pipe_class_dummy);
6776 %}
6777
6778 // Register Shift Left Immediate by 1bit
6779 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
6780 match(Set dst (LShiftI src nbits));
6781 predicate(PreferLAoverADD);
6782 ins_cost(DEFAULT_COST_LOW);
6783 size(4);
6784 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
6785 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
6786 ins_pipe(pipe_class_dummy);
6787 %}
6788
6789 // Register Shift Left Long
6790 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
6791 match(Set dst (LShiftL src1 nbits));
6792 size(6);
6826 ins_cost(3 * DEFAULT_COST);
6827 size(12);
6828 format %{ "SRA $dst,[$src] & 31" %}
6829 ins_encode %{
6830 __ z_lgr(Z_R1_scratch, $src$$Register);
6831 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6832 __ z_sra($dst$$Register, 0, Z_R1_scratch);
6833 %}
6834 ins_pipe(pipe_class_dummy);
6835 %}
6836
6837 // Register Arithmetic Shift Right Immediate
6838 // Constant shift count is masked in ideal graph already.
6839 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
6840 match(Set dst (RShiftI dst src));
6841 effect(KILL cr);
6842 size(4);
6843 format %{ "SRA $dst,$src" %}
6844 ins_encode %{
6845 int Nbit = $src$$constant;
6846 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6847 %}
6848 ins_pipe(pipe_class_dummy);
6849 %}
6850
6851 // Register Arithmetic Shift Right Long
6852 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
6853 match(Set dst (RShiftL src1 src2));
6854 effect(KILL cr);
6855 size(6);
6856 format %{ "SRAG $dst,$src1,[$src2]" %}
6857 opcode(SRAG_ZOPC);
6858 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6859 ins_pipe(pipe_class_dummy);
6860 %}
6861
6862 // Register Arithmetic Shift Right Long Immediate
6863 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
6864 match(Set dst (RShiftL src1 src2));
6865 effect(KILL cr);
6878 effect(KILL cr); // R1 is killed, too.
6879 ins_cost(3 * DEFAULT_COST);
6880 size(12);
6881 format %{ "SRL $dst,[$src] & 31" %}
6882 ins_encode %{
6883 __ z_lgr(Z_R1_scratch, $src$$Register);
6884 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6885 __ z_srl($dst$$Register, 0, Z_R1_scratch);
6886 %}
6887 ins_pipe(pipe_class_dummy);
6888 %}
6889
6890 // Register Shift Right Immediate
6891 // Constant shift count is masked in ideal graph already.
6892 instruct srlI_reg_imm(iRegI dst, immI src) %{
6893 match(Set dst (URShiftI dst src));
6894 size(4);
6895 format %{ "SRL $dst,$src" %}
6896 ins_encode %{
6897 int Nbit = $src$$constant;
6898 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6899 %}
6900 ins_pipe(pipe_class_dummy);
6901 %}
6902
6903 // Register Shift Right Long
6904 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
6905 match(Set dst (URShiftL src1 src2));
6906 size(6);
6907 format %{ "SRLG $dst,$src1,[$src2]" %}
6908 opcode(SRLG_ZOPC);
6909 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6910 ins_pipe(pipe_class_dummy);
6911 %}
6912
6913 // Register Shift Right Long Immediate
6914 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
6915 match(Set dst (URShiftL src1 src2));
6916 size(6);
6917 format %{ "SRLG $dst,$src1,$src2" %}
|
6753 effect(KILL cr); // R1 is killed, too.
6754 ins_cost(3 * DEFAULT_COST);
6755 size(14);
6756 format %{ "SLL $dst,$src,[$nbits] & 31\t# use RISC-like SLLG also for int" %}
6757 ins_encode %{
6758 __ z_lgr(Z_R1_scratch, $nbits$$Register);
6759 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6760 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
6761 %}
6762 ins_pipe(pipe_class_dummy);
6763 %}
6764
6765 // Register Shift Left Immediate
6766 // Constant shift count is masked in ideal graph already.
6767 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
6768 match(Set dst (LShiftI src nbits));
6769 size(6);
6770 format %{ "SLL $dst,$src,$nbits\t# use RISC-like SLLG also for int" %}
6771 ins_encode %{
6772 int Nbit = $nbits$$constant;
6773 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6774 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6775 %}
6776 ins_pipe(pipe_class_dummy);
6777 %}
6778
6779 // Register Shift Left Immediate by 1bit
6780 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
6781 match(Set dst (LShiftI src nbits));
6782 predicate(PreferLAoverADD);
6783 ins_cost(DEFAULT_COST_LOW);
6784 size(4);
6785 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
6786 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
6787 ins_pipe(pipe_class_dummy);
6788 %}
6789
6790 // Register Shift Left Long
6791 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
6792 match(Set dst (LShiftL src1 nbits));
6793 size(6);
6827 ins_cost(3 * DEFAULT_COST);
6828 size(12);
6829 format %{ "SRA $dst,[$src] & 31" %}
6830 ins_encode %{
6831 __ z_lgr(Z_R1_scratch, $src$$Register);
6832 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6833 __ z_sra($dst$$Register, 0, Z_R1_scratch);
6834 %}
6835 ins_pipe(pipe_class_dummy);
6836 %}
6837
6838 // Register Arithmetic Shift Right Immediate
6839 // Constant shift count is masked in ideal graph already.
6840 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
6841 match(Set dst (RShiftI dst src));
6842 effect(KILL cr);
6843 size(4);
6844 format %{ "SRA $dst,$src" %}
6845 ins_encode %{
6846 int Nbit = $src$$constant;
6847 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6848 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6849 %}
6850 ins_pipe(pipe_class_dummy);
6851 %}
6852
6853 // Register Arithmetic Shift Right Long
6854 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
6855 match(Set dst (RShiftL src1 src2));
6856 effect(KILL cr);
6857 size(6);
6858 format %{ "SRAG $dst,$src1,[$src2]" %}
6859 opcode(SRAG_ZOPC);
6860 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6861 ins_pipe(pipe_class_dummy);
6862 %}
6863
6864 // Register Arithmetic Shift Right Long Immediate
6865 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
6866 match(Set dst (RShiftL src1 src2));
6867 effect(KILL cr);
6880 effect(KILL cr); // R1 is killed, too.
6881 ins_cost(3 * DEFAULT_COST);
6882 size(12);
6883 format %{ "SRL $dst,[$src] & 31" %}
6884 ins_encode %{
6885 __ z_lgr(Z_R1_scratch, $src$$Register);
6886 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6887 __ z_srl($dst$$Register, 0, Z_R1_scratch);
6888 %}
6889 ins_pipe(pipe_class_dummy);
6890 %}
6891
6892 // Register Shift Right Immediate
6893 // Constant shift count is masked in ideal graph already.
6894 instruct srlI_reg_imm(iRegI dst, immI src) %{
6895 match(Set dst (URShiftI dst src));
6896 size(4);
6897 format %{ "SRL $dst,$src" %}
6898 ins_encode %{
6899 int Nbit = $src$$constant;
6900 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6901 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6902 %}
6903 ins_pipe(pipe_class_dummy);
6904 %}
6905
6906 // Register Shift Right Long
6907 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
6908 match(Set dst (URShiftL src1 src2));
6909 size(6);
6910 format %{ "SRLG $dst,$src1,[$src2]" %}
6911 opcode(SRLG_ZOPC);
6912 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6913 ins_pipe(pipe_class_dummy);
6914 %}
6915
6916 // Register Shift Right Long Immediate
6917 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
6918 match(Set dst (URShiftL src1 src2));
6919 size(6);
6920 format %{ "SRLG $dst,$src1,$src2" %}
|