1259 #define VESLV_ZOPC (unsigned long)(0xe7L << 40 | 0x70L << 0) // V1 := SLL(V2, V3), unsigned, element-wise
1260 #define VESL_ZOPC (unsigned long)(0xe7L << 40 | 0x30L << 0) // V1 := SLL(V3), unsigned, shift count from d2(b2).
1261
1262 #define VESRAV_ZOPC (unsigned long)(0xe7L << 40 | 0x7AL << 0) // V1 := SRA(V2, V3), signed, element-wise
1263 #define VESRA_ZOPC (unsigned long)(0xe7L << 40 | 0x3AL << 0) // V1 := SRA(V3), signed, shift count from d2(b2).
1264 #define VESRLV_ZOPC (unsigned long)(0xe7L << 40 | 0x78L << 0) // V1 := SRL(V2, V3), unsigned, element-wise
1265 #define VESRL_ZOPC (unsigned long)(0xe7L << 40 | 0x38L << 0) // V1 := SRL(V3), unsigned, shift count from d2(b2).
1266
1267 #define VSL_ZOPC (unsigned long)(0xe7L << 40 | 0x74L << 0) // V1 := SLL(V2), unsigned, bit-count
1268 #define VSLB_ZOPC (unsigned long)(0xe7L << 40 | 0x75L << 0) // V1 := SLL(V2), unsigned, byte-count
1269 #define VSLDB_ZOPC (unsigned long)(0xe7L << 40 | 0x77L << 0) // V1 := SLL((V2,V3)), unsigned, byte-count
1270
1271 #define VSRA_ZOPC (unsigned long)(0xe7L << 40 | 0x7eL << 0) // V1 := SRA(V2), signed, bit-count
1272 #define VSRAB_ZOPC (unsigned long)(0xe7L << 40 | 0x7fL << 0) // V1 := SRA(V2), signed, byte-count
1273 #define VSRL_ZOPC (unsigned long)(0xe7L << 40 | 0x7cL << 0) // V1 := SRL(V2), unsigned, bit-count
1274 #define VSRLB_ZOPC (unsigned long)(0xe7L << 40 | 0x7dL << 0) // V1 := SRL(V2), unsigned, byte-count
1275
1276 // Test under Mask
1277 #define VTM_ZOPC (unsigned long)(0xe7L << 40 | 0xd8L << 0) // Like TM, set CC according to state of selected bits.
1278
1279
1280 //--------------------------------
1281 //-- Miscellaneous Operations --
1282 //--------------------------------
1283
1284 // Execute
1285 #define EX_ZOPC (unsigned int)(68L << 24)
1286 #define EXRL_ZOPC (unsigned long)(0xc6L << 40 | 0x00L << 32) // z10
1287
1288 // Compare and Swap
1289 #define CS_ZOPC (unsigned int)(0xba << 24)
1290 #define CSY_ZOPC (unsigned long)(0xebL << 40 | 0x14L)
1291 #define CSG_ZOPC (unsigned long)(0xebL << 40 | 0x30L)
1292
1293 // Interlocked-Update
1294 #define LAA_ZOPC (unsigned long)(0xebL << 40 | 0xf8L) // z196
1295 #define LAAG_ZOPC (unsigned long)(0xebL << 40 | 0xe8L) // z196
1296 #define LAAL_ZOPC (unsigned long)(0xebL << 40 | 0xfaL) // z196
1297 #define LAALG_ZOPC (unsigned long)(0xebL << 40 | 0xeaL) // z196
1298 #define LAN_ZOPC (unsigned long)(0xebL << 40 | 0xf4L) // z196
1458
1459 // Rounding mode for float-2-int conversions.
1460 enum RoundingMode {
1461 current_mode = 0, // Mode taken from FPC register.
1462 biased_to_nearest = 1,
1463 to_nearest = 4,
1464 to_zero = 5,
1465 to_plus_infinity = 6,
1466 to_minus_infinity = 7
1467 };
1468
1469 // Vector Register Element Type.
1470 enum VRegElemType {
1471 VRET_BYTE = 0,
1472 VRET_HW = 1,
1473 VRET_FW = 2,
1474 VRET_DW = 3,
1475 VRET_QW = 4
1476 };
1477
1478 // Vector Operation Condition Code Control.
1479 enum VOpCCC {
1480 VOP_CCIGN = 0, // ignore, don't set CC
1481 VOP_CCSET = 1 // set the CC
1482 };
1483
1484 // Inverse condition code, i.e. determine "15 - cc" for a given condition code cc.
1485 static branch_condition inverse_condition(branch_condition cc);
1486 static branch_condition inverse_float_condition(branch_condition cc);
1487
1488
1489 //-----------------------------------------------
1490 // instruction property getter methods
1491 //-----------------------------------------------
1492
1493 // Calculate length of instruction.
1494 static int instr_len(unsigned char *instr);
1495
1496 // Longest instructions are 6 bytes on z/Architecture.
1497 static int instr_maxlen() { return 6; }
1498
1499 // Average instruction is 4 bytes on z/Architecture (just a guess).
1500 static int instr_avglen() { return 4; }
1501
1608 return uimm4(size, pos, 48);
1609 }
1610
1611 // Vector Element IndeX. 4-bit field which indexes the target vector element.
1612 static int64_t veix_mask(int64_t ix, int el_size, int pos) {
1613 // el_size - size of the vector element. This is a VRegElemType enum value.
1614 // ix - vector element index.
1615 int max_ix = -1;
1616 switch (el_size) {
1617 case VRET_BYTE: max_ix = 15; break;
1618 case VRET_HW: max_ix = 7; break;
1619 case VRET_FW: max_ix = 3; break;
1620 case VRET_DW: max_ix = 1; break;
1621 case VRET_QW: max_ix = 0; break;
1622 default: guarantee(false, "bad vector element size %d", el_size); break;
1623 }
1624 assert((0 <= ix) && (ix <= max_ix), "element size out of range (0 <= %ld <= %d)", ix, max_ix);
1625 return uimm4(ix, pos, 48);
1626 }
1627
1628 // Vector Operation Condition Code Control. 4-bit field, one bit of which indicates if the condition code is to be set by the operation.
1629 static int64_t vccc_mask(int64_t flag, int pos) {
1630 assert((flag == VOP_CCIGN) || (flag == VOP_CCSET), "VCCC flag value out of range");
1631 return uimm4(flag, pos, 48);
1632 }
1633
1634 public:
1635
1636 //--------------------------------------------------
1637 // instruction field construction methods
1638 //--------------------------------------------------
1639
1640 // Compute relative address (32 bit) for branch.
1641 // Only used once in nativeInst_s390.cpp.
1642 static intptr_t z_pcrel_off(address dest, address pc) {
1643 return RelAddr::pcrel_off32(dest, pc);
1644 }
1645
1646 // Extract 20-bit signed displacement.
1647 // Only used in disassembler_s390.cpp for temp enhancements.
1648 static int inv_simm20_xx(address iLoc) {
1649 unsigned long instr = 0;
1650 unsigned long iLen = get_instruction(iLoc, &instr);
1651 return inv_simm20(instr);
2754 inline void z_vesrlvh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2755 inline void z_vesrlvf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2756 inline void z_vesrlvg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2757 inline void z_vesrl( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4);
2758 inline void z_vesrlb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2759 inline void z_vesrlh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2760 inline void z_vesrlf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2761 inline void z_vesrlg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2762
2763 inline void z_vsl( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2764 inline void z_vslb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2765 inline void z_vsldb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
2766
2767 inline void z_vsra( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2768 inline void z_vsrab( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2769 inline void z_vsrl( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2770 inline void z_vsrlb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2771
2772 // Test under Mask
2773 inline void z_vtm( VectorRegister v1, VectorRegister v2);
2774
2775
2776 // Floatingpoint instructions
2777 // ==========================
2778
2779 // compare instructions
2780 inline void z_cebr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; float
2781 inline void z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; float
2782 inline void z_ceb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; float
2783 inline void z_cdbr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; double
2784 inline void z_cdb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; double
2785 inline void z_cdb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; double
2786
2787 // load instructions
2788 inline void z_le( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; float
2789 inline void z_ley(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; float
2790 inline void z_ld( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; double
2791 inline void z_ldy(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; double
2792 inline void z_le( FloatRegister r1, const Address &a); // load r1 = *(a) ; float
2793 inline void z_ley(FloatRegister r1, const Address &a); // load r1 = *(a) ; float
|
1259 #define VESLV_ZOPC (unsigned long)(0xe7L << 40 | 0x70L << 0) // V1 := SLL(V2, V3), unsigned, element-wise
1260 #define VESL_ZOPC (unsigned long)(0xe7L << 40 | 0x30L << 0) // V1 := SLL(V3), unsigned, shift count from d2(b2).
1261
1262 #define VESRAV_ZOPC (unsigned long)(0xe7L << 40 | 0x7AL << 0) // V1 := SRA(V2, V3), signed, element-wise
1263 #define VESRA_ZOPC (unsigned long)(0xe7L << 40 | 0x3AL << 0) // V1 := SRA(V3), signed, shift count from d2(b2).
1264 #define VESRLV_ZOPC (unsigned long)(0xe7L << 40 | 0x78L << 0) // V1 := SRL(V2, V3), unsigned, element-wise
1265 #define VESRL_ZOPC (unsigned long)(0xe7L << 40 | 0x38L << 0) // V1 := SRL(V3), unsigned, shift count from d2(b2).
1266
1267 #define VSL_ZOPC (unsigned long)(0xe7L << 40 | 0x74L << 0) // V1 := SLL(V2), unsigned, bit-count
1268 #define VSLB_ZOPC (unsigned long)(0xe7L << 40 | 0x75L << 0) // V1 := SLL(V2), unsigned, byte-count
1269 #define VSLDB_ZOPC (unsigned long)(0xe7L << 40 | 0x77L << 0) // V1 := SLL((V2,V3)), unsigned, byte-count
1270
1271 #define VSRA_ZOPC (unsigned long)(0xe7L << 40 | 0x7eL << 0) // V1 := SRA(V2), signed, bit-count
1272 #define VSRAB_ZOPC (unsigned long)(0xe7L << 40 | 0x7fL << 0) // V1 := SRA(V2), signed, byte-count
1273 #define VSRL_ZOPC (unsigned long)(0xe7L << 40 | 0x7cL << 0) // V1 := SRL(V2), unsigned, bit-count
1274 #define VSRLB_ZOPC (unsigned long)(0xe7L << 40 | 0x7dL << 0) // V1 := SRL(V2), unsigned, byte-count
1275
1276 // Test under Mask
1277 #define VTM_ZOPC (unsigned long)(0xe7L << 40 | 0xd8L << 0) // Like TM, set CC according to state of selected bits.
1278
1279 //---< Vector String Instructions >---
1280 #define VFAE_ZOPC (unsigned long)(0xe7L << 40 | 0x82L << 0) // Find any element
1281 #define VFEE_ZOPC (unsigned long)(0xe7L << 40 | 0x80L << 0) // Find element equal
1282 #define VFENE_ZOPC (unsigned long)(0xe7L << 40 | 0x81L << 0) // Find element not equal
1283 #define VSTRC_ZOPC (unsigned long)(0xe7L << 40 | 0x8aL << 0) // String range compare
1284 #define VISTR_ZOPC (unsigned long)(0xe7L << 40 | 0x5cL << 0) // Isolate String
1285
1286
1287 //--------------------------------
1288 //-- Miscellaneous Operations --
1289 //--------------------------------
1290
1291 // Execute
1292 #define EX_ZOPC (unsigned int)(68L << 24)
1293 #define EXRL_ZOPC (unsigned long)(0xc6L << 40 | 0x00L << 32) // z10
1294
1295 // Compare and Swap
1296 #define CS_ZOPC (unsigned int)(0xba << 24)
1297 #define CSY_ZOPC (unsigned long)(0xebL << 40 | 0x14L)
1298 #define CSG_ZOPC (unsigned long)(0xebL << 40 | 0x30L)
1299
1300 // Interlocked-Update
1301 #define LAA_ZOPC (unsigned long)(0xebL << 40 | 0xf8L) // z196
1302 #define LAAG_ZOPC (unsigned long)(0xebL << 40 | 0xe8L) // z196
1303 #define LAAL_ZOPC (unsigned long)(0xebL << 40 | 0xfaL) // z196
1304 #define LAALG_ZOPC (unsigned long)(0xebL << 40 | 0xeaL) // z196
1305 #define LAN_ZOPC (unsigned long)(0xebL << 40 | 0xf4L) // z196
1465
1466 // Rounding mode for float-2-int conversions.
1467 enum RoundingMode {
1468 current_mode = 0, // Mode taken from FPC register.
1469 biased_to_nearest = 1,
1470 to_nearest = 4,
1471 to_zero = 5,
1472 to_plus_infinity = 6,
1473 to_minus_infinity = 7
1474 };
1475
1476 // Vector Register Element Type.
1477 enum VRegElemType {
1478 VRET_BYTE = 0,
1479 VRET_HW = 1,
1480 VRET_FW = 2,
1481 VRET_DW = 3,
1482 VRET_QW = 4
1483 };
1484
1485 // Vector Operation Result Control.
1486 // This is a set of flags used in some vector instructions to control
1487 // the result (side) effects of instruction execution.
1488 enum VOpRC {
1489 VOPRC_CCSET = 0b0001, // set the CC.
1490 VOPRC_CCIGN = 0b0000, // ignore, don't set CC.
1491 VOPRC_ZS = 0b0010, // Zero Search. Additional, elementwise, comparison against zero.
1492 VOPRC_NOZS = 0b0000, // No Zero Search.
1493 VOPRC_RTBYTEIX = 0b0100, // generate byte index to lowest element with true comparison.
1494 VOPRC_RTBITVEC = 0b0000, // generate bit vector, all 1s for true, all 0s for false element comparisons.
1495 VOPRC_INVERT = 0b1000, // invert comparison results.
1496 VOPRC_NOINVERT = 0b0000 // use comparison results as is, do not invert.
1497 };
1498
1499 // Inverse condition code, i.e. determine "15 - cc" for a given condition code cc.
1500 static branch_condition inverse_condition(branch_condition cc);
1501 static branch_condition inverse_float_condition(branch_condition cc);
1502
1503
1504 //-----------------------------------------------
1505 // instruction property getter methods
1506 //-----------------------------------------------
1507
1508 // Calculate length of instruction.
1509 static int instr_len(unsigned char *instr);
1510
1511 // Longest instructions are 6 bytes on z/Architecture.
1512 static int instr_maxlen() { return 6; }
1513
1514 // Average instruction is 4 bytes on z/Architecture (just a guess).
1515 static int instr_avglen() { return 4; }
1516
1623 return uimm4(size, pos, 48);
1624 }
1625
1626 // Vector Element IndeX. 4-bit field which indexes the target vector element.
1627 static int64_t veix_mask(int64_t ix, int el_size, int pos) {
1628 // el_size - size of the vector element. This is a VRegElemType enum value.
1629 // ix - vector element index.
1630 int max_ix = -1;
1631 switch (el_size) {
1632 case VRET_BYTE: max_ix = 15; break;
1633 case VRET_HW: max_ix = 7; break;
1634 case VRET_FW: max_ix = 3; break;
1635 case VRET_DW: max_ix = 1; break;
1636 case VRET_QW: max_ix = 0; break;
1637 default: guarantee(false, "bad vector element size %d", el_size); break;
1638 }
1639 assert((0 <= ix) && (ix <= max_ix), "element size out of range (0 <= %ld <= %d)", ix, max_ix);
1640 return uimm4(ix, pos, 48);
1641 }
1642
1643 // Vector Operation Result Control. 4-bit field.
1644 static int64_t voprc_any(int64_t flags, int pos, int64_t allowed_flags = 0b1111) {
1645 assert((flags & allowed_flags) == flags, "Invalid VOPRC_* flag combination: %d", (int)flags);
1646 return uimm4(flags, pos, 48);
1647 }
1648
1649 // Vector Operation Result Control. Condition code setting.
1650 static int64_t voprc_ccmask(int64_t flags, int pos) {
1651 return voprc_any(flags, pos, VOPRC_CCIGN | VOPRC_CCSET);
1652 }
1653
1654 public:
1655
1656 //--------------------------------------------------
1657 // instruction field construction methods
1658 //--------------------------------------------------
1659
1660 // Compute relative address (32 bit) for branch.
1661 // Only used once in nativeInst_s390.cpp.
1662 static intptr_t z_pcrel_off(address dest, address pc) {
1663 return RelAddr::pcrel_off32(dest, pc);
1664 }
1665
1666 // Extract 20-bit signed displacement.
1667 // Only used in disassembler_s390.cpp for temp enhancements.
1668 static int inv_simm20_xx(address iLoc) {
1669 unsigned long instr = 0;
1670 unsigned long iLen = get_instruction(iLoc, &instr);
1671 return inv_simm20(instr);
2774 inline void z_vesrlvh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2775 inline void z_vesrlvf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2776 inline void z_vesrlvg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2777 inline void z_vesrl( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4);
2778 inline void z_vesrlb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2779 inline void z_vesrlh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2780 inline void z_vesrlf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2781 inline void z_vesrlg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2782
2783 inline void z_vsl( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2784 inline void z_vslb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2785 inline void z_vsldb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
2786
2787 inline void z_vsra( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2788 inline void z_vsrab( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2789 inline void z_vsrl( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2790 inline void z_vsrlb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2791
2792 // Test under Mask
2793 inline void z_vtm( VectorRegister v1, VectorRegister v2);
2794
2795 //---< Vector String Instructions >---
2796 inline void z_vfae( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t cc5); // Find any element
2797 inline void z_vfaeb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5);
2798 inline void z_vfaeh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5);
2799 inline void z_vfaef( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5);
2800 inline void z_vfee( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t cc5); // Find element equal
2801 inline void z_vfeeb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5);
2802 inline void z_vfeeh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5);
2803 inline void z_vfeef( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5);
2804 inline void z_vfene( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t cc5); // Find element not equal
2805 inline void z_vfeneb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5);
2806 inline void z_vfeneh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5);
2807 inline void z_vfenef( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5);
2808 inline void z_vstrc( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t imm5, int64_t cc6); // String range compare
2809 inline void z_vstrcb( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t cc6);
2810 inline void z_vstrch( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t cc6);
2811 inline void z_vstrcf( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t cc6);
2812 inline void z_vistr( VectorRegister v1, VectorRegister v2, int64_t imm3, int64_t cc5); // Isolate String
2813 inline void z_vistrb( VectorRegister v1, VectorRegister v2, int64_t cc5);
2814 inline void z_vistrh( VectorRegister v1, VectorRegister v2, int64_t cc5);
2815 inline void z_vistrf( VectorRegister v1, VectorRegister v2, int64_t cc5);
2816 inline void z_vistrbs(VectorRegister v1, VectorRegister v2);
2817 inline void z_vistrhs(VectorRegister v1, VectorRegister v2);
2818 inline void z_vistrfs(VectorRegister v1, VectorRegister v2);
2819
2820
2821 // Floatingpoint instructions
2822 // ==========================
2823
2824 // compare instructions
2825 inline void z_cebr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; float
2826 inline void z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; float
2827 inline void z_ceb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; float
2828 inline void z_cdbr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; double
2829 inline void z_cdb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; double
2830 inline void z_cdb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; double
2831
2832 // load instructions
2833 inline void z_le( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; float
2834 inline void z_ley(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; float
2835 inline void z_ld( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; double
2836 inline void z_ldy(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; double
2837 inline void z_le( FloatRegister r1, const Address &a); // load r1 = *(a) ; float
2838 inline void z_ley(FloatRegister r1, const Address &a); // load r1 = *(a) ; float
|