11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef OS_CPU_LINUX_ARM_ORDERACCESS_LINUX_ARM_HPP
  26 #define OS_CPU_LINUX_ARM_ORDERACCESS_LINUX_ARM_HPP
  27 
  28 // Included in orderAccess.hpp header file.
  29 
  30 #include "runtime/os.hpp"
  31 #include "vm_version_arm.hpp"
  32 
  33 // Implementation of class OrderAccess.
  34 // - we define the high level barriers below and use the general
  35 //   implementation in orderAccess.hpp.
  36 
  37 // Memory Ordering on ARM is weak.
  38 //
  39 // Implement all 4 memory ordering barriers by DMB, since it is a
  40 // lighter version of DSB.
  41 // dmb_sy implies full system shareability domain. RD/WR access type.
  42 // dmb_st implies full system shareability domain. WR only access type.
  43 //
  44 // NOP on < ARMv6 (MP not supported)
  45 //
  46 // Non mcr instructions can be used if we build for armv7 or higher arch
  47 //    __asm__ __volatile__ ("dmb" : : : "memory");
  48 //    __asm__ __volatile__ ("dsb" : : : "memory");
  49 //
  50 // inline void _OrderAccess_dsb() {
  51 //    volatile intptr_t dummy = 0;

  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef OS_CPU_LINUX_ARM_ORDERACCESS_LINUX_ARM_HPP
  26 #define OS_CPU_LINUX_ARM_ORDERACCESS_LINUX_ARM_HPP
  27 
  28 // Included in orderAccess.hpp header file.
  29 
  30 #include "runtime/os.hpp"
  31 #include "runtime/vm_version.hpp"
  32 
  33 // Implementation of class OrderAccess.
  34 // - we define the high level barriers below and use the general
  35 //   implementation in orderAccess.hpp.
  36 
  37 // Memory Ordering on ARM is weak.
  38 //
  39 // Implement all 4 memory ordering barriers by DMB, since it is a
  40 // lighter version of DSB.
  41 // dmb_sy implies full system shareability domain. RD/WR access type.
  42 // dmb_st implies full system shareability domain. WR only access type.
  43 //
  44 // NOP on < ARMv6 (MP not supported)
  45 //
  46 // Non mcr instructions can be used if we build for armv7 or higher arch
  47 //    __asm__ __volatile__ ("dmb" : : : "memory");
  48 //    __asm__ __volatile__ ("dsb" : : : "memory");
  49 //
  50 // inline void _OrderAccess_dsb() {
  51 //    volatile intptr_t dummy = 0;