9929 ins_pipe( pipe_slow );
9930 %}
9931
9932 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9933 predicate (UseSSE>=2);
9934 effect(KILL cr);
9935 match(Set dst (Log10D src));
9936 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9937 // fyl2x ; compute log_10(2) * log_2(x)
9938 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9939 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9940 %}
9941 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9942 Push_SrcD(src),
9943 Opcode(0xD9), Opcode(0xF1), // fyl2x
9944 Push_ResultD(dst));
9945
9946 ins_pipe( pipe_slow );
9947 %}
9948
9949 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
9950 predicate (UseSSE<=1);
9951 // The source Double operand on FPU stack
9952 match(Set dst (LogD src));
9953 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9954 // fxch ; swap ST(0) with ST(1)
9955 // fyl2x ; compute log_e(2) * log_2(x)
9956 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9957 "FXCH \n\t"
9958 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9959 %}
9960 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9961 Opcode(0xD9), Opcode(0xC9), // fxch
9962 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9963
9964 ins_pipe( pipe_slow );
9965 %}
9966
9967 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
9968 predicate (UseSSE>=2);
9969 effect(KILL cr);
9970 // The source and result Double operands in XMM registers
9971 match(Set dst (LogD src));
9972 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9973 // fyl2x ; compute log_e(2) * log_2(x)
9974 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9975 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9976 %}
9977 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9978 Push_SrcD(src),
9979 Opcode(0xD9), Opcode(0xF1), // fyl2x
9980 Push_ResultD(dst));
9981 ins_pipe( pipe_slow );
9982 %}
9983
9984 //-------------Float Instructions-------------------------------
9985 // Float Math
9986
9987 // Code for float compare:
9988 // fcompp();
9989 // fwait(); fnstsw_ax();
9990 // sahf();
9991 // movl(dst, unordered_result);
9992 // jcc(Assembler::parity, exit);
9993 // movl(dst, less_result);
9994 // jcc(Assembler::below, exit);
9995 // movl(dst, equal_result);
9996 // jcc(Assembler::equal, exit);
9997 // movl(dst, greater_result);
9998 // exit:
9999
10000 // P6 version of float compare, sets condition codes in EFLAGS
10001 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10002 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10003 match(Set cr (CmpF src1 src2));
|
9929 ins_pipe( pipe_slow );
9930 %}
9931
9932 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9933 predicate (UseSSE>=2);
9934 effect(KILL cr);
9935 match(Set dst (Log10D src));
9936 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9937 // fyl2x ; compute log_10(2) * log_2(x)
9938 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9939 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9940 %}
9941 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9942 Push_SrcD(src),
9943 Opcode(0xD9), Opcode(0xF1), // fyl2x
9944 Push_ResultD(dst));
9945
9946 ins_pipe( pipe_slow );
9947 %}
9948
9949 //-------------Float Instructions-------------------------------
9950 // Float Math
9951
9952 // Code for float compare:
9953 // fcompp();
9954 // fwait(); fnstsw_ax();
9955 // sahf();
9956 // movl(dst, unordered_result);
9957 // jcc(Assembler::parity, exit);
9958 // movl(dst, less_result);
9959 // jcc(Assembler::below, exit);
9960 // movl(dst, equal_result);
9961 // jcc(Assembler::equal, exit);
9962 // movl(dst, greater_result);
9963 // exit:
9964
9965 // P6 version of float compare, sets condition codes in EFLAGS
9966 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
9967 predicate(VM_Version::supports_cmov() && UseSSE == 0);
9968 match(Set cr (CmpF src1 src2));
|