9849 Push_ResultXD(dst) );
9850 ins_pipe( pipe_slow );
9851 %}
9852
9853 instruct log10D_reg(regD dst) %{
9854 // The source and result Double operands in XMM registers
9855 match(Set dst (Log10D dst));
9856 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9857 // fyl2x ; compute log_10(2) * log_2(x)
9858 format %{ "fldlg2\t\t\t#Log10\n\t"
9859 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9860 %}
9861 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9862 Push_SrcXD(dst),
9863 Opcode(0xD9), Opcode(0xF1), // fyl2x
9864 Push_ResultXD(dst));
9865
9866 ins_pipe( pipe_slow );
9867 %}
9868
9869 instruct logD_reg(regD dst) %{
9870 // The source and result Double operands in XMM registers
9871 match(Set dst (LogD dst));
9872 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9873 // fyl2x ; compute log_e(2) * log_2(x)
9874 format %{ "fldln2\t\t\t#Log_e\n\t"
9875 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9876 %}
9877 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9878 Push_SrcXD(dst),
9879 Opcode(0xD9), Opcode(0xF1), // fyl2x
9880 Push_ResultXD(dst));
9881 ins_pipe( pipe_slow );
9882 %}
9883
9884 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9885 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9886 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9887 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9888 ins_encode %{
9889 __ subptr(rsp, 8);
9890 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9891 __ fld_d(Address(rsp, 0));
9892 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9893 __ fld_d(Address(rsp, 0));
9894 __ fast_pow();
9895 __ fstp_d(Address(rsp, 0));
9896 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9897 __ addptr(rsp, 8);
9898 %}
9899 ins_pipe( pipe_slow );
9900 %}
9901
9902 //----------Arithmetic Conversion Instructions---------------------------------
9903
|
9849 Push_ResultXD(dst) );
9850 ins_pipe( pipe_slow );
9851 %}
9852
9853 instruct log10D_reg(regD dst) %{
9854 // The source and result Double operands in XMM registers
9855 match(Set dst (Log10D dst));
9856 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9857 // fyl2x ; compute log_10(2) * log_2(x)
9858 format %{ "fldlg2\t\t\t#Log10\n\t"
9859 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9860 %}
9861 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9862 Push_SrcXD(dst),
9863 Opcode(0xD9), Opcode(0xF1), // fyl2x
9864 Push_ResultXD(dst));
9865
9866 ins_pipe( pipe_slow );
9867 %}
9868
9869 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9870 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9871 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9872 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9873 ins_encode %{
9874 __ subptr(rsp, 8);
9875 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9876 __ fld_d(Address(rsp, 0));
9877 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9878 __ fld_d(Address(rsp, 0));
9879 __ fast_pow();
9880 __ fstp_d(Address(rsp, 0));
9881 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9882 __ addptr(rsp, 8);
9883 %}
9884 ins_pipe( pipe_slow );
9885 %}
9886
9887 //----------Arithmetic Conversion Instructions---------------------------------
9888
|