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src/share/vm/c1/c1_LIR.cpp

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rev 9434 : 8138952: C1: Distinguish between PPC32 and PPC64
Reviewed-by: twisti


  38   return FrameMap::cpu_rnr2reg(cpu_regnrLo());
  39 }
  40 
  41 Register LIR_OprDesc::as_register_hi() const {
  42   return FrameMap::cpu_rnr2reg(cpu_regnrHi());
  43 }
  44 
  45 #if defined(X86)
  46 
  47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
  48   return FrameMap::nr2xmmreg(xmm_regnr());
  49 }
  50 
  51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
  52   assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
  53   return FrameMap::nr2xmmreg(xmm_regnrLo());
  54 }
  55 
  56 #endif // X86
  57 
  58 #if defined(SPARC) || defined(PPC)
  59 
  60 FloatRegister LIR_OprDesc::as_float_reg() const {
  61   return FrameMap::nr2floatreg(fpu_regnr());
  62 }
  63 
  64 FloatRegister LIR_OprDesc::as_double_reg() const {
  65   return FrameMap::nr2floatreg(fpu_regnrHi());
  66 }
  67 
  68 #endif
  69 
  70 #if defined(ARM) || defined (AARCH64)
  71 
  72 FloatRegister LIR_OprDesc::as_float_reg() const {
  73   return as_FloatRegister(fpu_regnr());
  74 }
  75 
  76 FloatRegister LIR_OprDesc::as_double_reg() const {
  77   return as_FloatRegister(fpu_regnrLo());
  78 }
  79 
  80 #endif
  81 
  82 
  83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
  84 
  85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
  86   ValueTag tag = type->tag();
  87   switch (tag) {
  88   case metaDataTag : {
  89     ClassConstant* c = type->as_ClassConstant();
  90     if (c != NULL && !c->value()->is_loaded()) {


 190       return '?';
 191 
 192     default:
 193       ShouldNotReachHere();
 194       return '?';
 195   }
 196 }
 197 
 198 #ifndef PRODUCT
 199 void LIR_OprDesc::validate_type() const {
 200 
 201 #ifdef ASSERT
 202   if (!is_pointer() && !is_illegal()) {
 203     OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
 204     switch (as_BasicType(type_field())) {
 205     case T_LONG:
 206       assert((kindfield == cpu_register || kindfield == stack_value) &&
 207              size_field() == double_size, "must match");
 208       break;
 209     case T_FLOAT:
 210       // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
 211       assert((kindfield == fpu_register || kindfield == stack_value
 212              ARM_ONLY(|| kindfield == cpu_register)
 213              PPC_ONLY(|| kindfield == cpu_register) ) &&
 214              size_field() == single_size, "must match");
 215       break;
 216     case T_DOUBLE:
 217       // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
 218       assert((kindfield == fpu_register || kindfield == stack_value
 219              ARM_ONLY(|| kindfield == cpu_register)
 220              PPC_ONLY(|| kindfield == cpu_register) ) &&
 221              size_field() == double_size, "must match");
 222       break;
 223     case T_BOOLEAN:
 224     case T_CHAR:
 225     case T_BYTE:
 226     case T_SHORT:
 227     case T_INT:
 228     case T_ADDRESS:
 229     case T_OBJECT:
 230     case T_METADATA:
 231     case T_ARRAY:
 232       assert((kindfield == cpu_register || kindfield == stack_value) &&
 233              size_field() == single_size, "must match");
 234       break;
 235 
 236     case T_ILLEGAL:
 237       // XXX TKR also means unknown right now
 238       // assert(is_illegal(), "must match");
 239       break;
 240 


 541     {
 542       assert(op->as_Op1() != NULL, "must be");
 543       LIR_Op1* op1 = (LIR_Op1*)op;
 544 
 545       assert(op1->_info != NULL, "");  do_info(op1->_info);
 546       if (op1->_opr->is_valid())       do_temp(op1->_opr); // safepoints on SPARC need temporary register
 547       assert(op1->_result->is_illegal(), "safepoint does not produce value");
 548 
 549       break;
 550     }
 551 
 552 // LIR_OpConvert;
 553     case lir_convert:        // input and result always valid, info always invalid
 554     {
 555       assert(op->as_OpConvert() != NULL, "must be");
 556       LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
 557 
 558       assert(opConvert->_info == NULL, "must be");
 559       if (opConvert->_opr->is_valid())       do_input(opConvert->_opr);
 560       if (opConvert->_result->is_valid())    do_output(opConvert->_result);
 561 #ifdef PPC
 562       if (opConvert->_tmp1->is_valid())      do_temp(opConvert->_tmp1);
 563       if (opConvert->_tmp2->is_valid())      do_temp(opConvert->_tmp2);
 564 #endif
 565       do_stub(opConvert->_stub);
 566 
 567       break;
 568     }
 569 
 570 // LIR_OpBranch;
 571     case lir_branch:                   // may have info, input and result register always invalid
 572     case lir_cond_float_branch:        // may have info, input and result register always invalid
 573     {
 574       assert(op->as_OpBranch() != NULL, "must be");
 575       LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
 576 
 577       if (opBranch->_info != NULL)     do_info(opBranch->_info);
 578       assert(opBranch->_result->is_illegal(), "not used");
 579       if (opBranch->_stub != NULL)     opBranch->stub()->visit(this);
 580 
 581       break;


1936 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1937   switch(cond) {
1938     case lir_cond_equal:           out->print("[EQ]");      break;
1939     case lir_cond_notEqual:        out->print("[NE]");      break;
1940     case lir_cond_less:            out->print("[LT]");      break;
1941     case lir_cond_lessEqual:       out->print("[LE]");      break;
1942     case lir_cond_greaterEqual:    out->print("[GE]");      break;
1943     case lir_cond_greater:         out->print("[GT]");      break;
1944     case lir_cond_belowEqual:      out->print("[BE]");      break;
1945     case lir_cond_aboveEqual:      out->print("[AE]");      break;
1946     case lir_cond_always:          out->print("[AL]");      break;
1947     default:                       out->print("[%d]",cond); break;
1948   }
1949 }
1950 
1951 // LIR_OpConvert
1952 void LIR_OpConvert::print_instr(outputStream* out) const {
1953   print_bytecode(out, bytecode());
1954   in_opr()->print(out);                  out->print(" ");
1955   result_opr()->print(out);              out->print(" ");
1956 #ifdef PPC
1957   if(tmp1()->is_valid()) {
1958     tmp1()->print(out); out->print(" ");
1959     tmp2()->print(out); out->print(" ");
1960   }
1961 #endif
1962 }
1963 
1964 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1965   switch(code) {
1966     case Bytecodes::_d2f: out->print("[d2f] "); break;
1967     case Bytecodes::_d2i: out->print("[d2i] "); break;
1968     case Bytecodes::_d2l: out->print("[d2l] "); break;
1969     case Bytecodes::_f2d: out->print("[f2d] "); break;
1970     case Bytecodes::_f2i: out->print("[f2i] "); break;
1971     case Bytecodes::_f2l: out->print("[f2l] "); break;
1972     case Bytecodes::_i2b: out->print("[i2b] "); break;
1973     case Bytecodes::_i2c: out->print("[i2c] "); break;
1974     case Bytecodes::_i2d: out->print("[i2d] "); break;
1975     case Bytecodes::_i2f: out->print("[i2f] "); break;
1976     case Bytecodes::_i2l: out->print("[i2l] "); break;




  38   return FrameMap::cpu_rnr2reg(cpu_regnrLo());
  39 }
  40 
  41 Register LIR_OprDesc::as_register_hi() const {
  42   return FrameMap::cpu_rnr2reg(cpu_regnrHi());
  43 }
  44 
  45 #if defined(X86)
  46 
  47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
  48   return FrameMap::nr2xmmreg(xmm_regnr());
  49 }
  50 
  51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
  52   assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
  53   return FrameMap::nr2xmmreg(xmm_regnrLo());
  54 }
  55 
  56 #endif // X86
  57 
  58 #if defined(SPARC) || defined(PPC32)
  59 
  60 FloatRegister LIR_OprDesc::as_float_reg() const {
  61   return FrameMap::nr2floatreg(fpu_regnr());
  62 }
  63 
  64 FloatRegister LIR_OprDesc::as_double_reg() const {
  65   return FrameMap::nr2floatreg(fpu_regnrHi());
  66 }
  67 
  68 #endif
  69 
  70 #if defined(ARM) || defined(AARCH64) || defined(PPC64)
  71 
  72 FloatRegister LIR_OprDesc::as_float_reg() const {
  73   return as_FloatRegister(fpu_regnr());
  74 }
  75 
  76 FloatRegister LIR_OprDesc::as_double_reg() const {
  77   return as_FloatRegister(fpu_regnrLo());
  78 }
  79 
  80 #endif
  81 
  82 
  83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
  84 
  85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
  86   ValueTag tag = type->tag();
  87   switch (tag) {
  88   case metaDataTag : {
  89     ClassConstant* c = type->as_ClassConstant();
  90     if (c != NULL && !c->value()->is_loaded()) {


 190       return '?';
 191 
 192     default:
 193       ShouldNotReachHere();
 194       return '?';
 195   }
 196 }
 197 
 198 #ifndef PRODUCT
 199 void LIR_OprDesc::validate_type() const {
 200 
 201 #ifdef ASSERT
 202   if (!is_pointer() && !is_illegal()) {
 203     OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
 204     switch (as_BasicType(type_field())) {
 205     case T_LONG:
 206       assert((kindfield == cpu_register || kindfield == stack_value) &&
 207              size_field() == double_size, "must match");
 208       break;
 209     case T_FLOAT:
 210       // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
 211       assert((kindfield == fpu_register || kindfield == stack_value
 212              ARM_ONLY(|| kindfield == cpu_register)
 213              PPC32_ONLY(|| kindfield == cpu_register) ) &&
 214              size_field() == single_size, "must match");
 215       break;
 216     case T_DOUBLE:
 217       // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
 218       assert((kindfield == fpu_register || kindfield == stack_value
 219              ARM_ONLY(|| kindfield == cpu_register)
 220              PPC32_ONLY(|| kindfield == cpu_register) ) &&
 221              size_field() == double_size, "must match");
 222       break;
 223     case T_BOOLEAN:
 224     case T_CHAR:
 225     case T_BYTE:
 226     case T_SHORT:
 227     case T_INT:
 228     case T_ADDRESS:
 229     case T_OBJECT:
 230     case T_METADATA:
 231     case T_ARRAY:
 232       assert((kindfield == cpu_register || kindfield == stack_value) &&
 233              size_field() == single_size, "must match");
 234       break;
 235 
 236     case T_ILLEGAL:
 237       // XXX TKR also means unknown right now
 238       // assert(is_illegal(), "must match");
 239       break;
 240 


 541     {
 542       assert(op->as_Op1() != NULL, "must be");
 543       LIR_Op1* op1 = (LIR_Op1*)op;
 544 
 545       assert(op1->_info != NULL, "");  do_info(op1->_info);
 546       if (op1->_opr->is_valid())       do_temp(op1->_opr); // safepoints on SPARC need temporary register
 547       assert(op1->_result->is_illegal(), "safepoint does not produce value");
 548 
 549       break;
 550     }
 551 
 552 // LIR_OpConvert;
 553     case lir_convert:        // input and result always valid, info always invalid
 554     {
 555       assert(op->as_OpConvert() != NULL, "must be");
 556       LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
 557 
 558       assert(opConvert->_info == NULL, "must be");
 559       if (opConvert->_opr->is_valid())       do_input(opConvert->_opr);
 560       if (opConvert->_result->is_valid())    do_output(opConvert->_result);
 561 #ifdef PPC32
 562       if (opConvert->_tmp1->is_valid())      do_temp(opConvert->_tmp1);
 563       if (opConvert->_tmp2->is_valid())      do_temp(opConvert->_tmp2);
 564 #endif
 565       do_stub(opConvert->_stub);
 566 
 567       break;
 568     }
 569 
 570 // LIR_OpBranch;
 571     case lir_branch:                   // may have info, input and result register always invalid
 572     case lir_cond_float_branch:        // may have info, input and result register always invalid
 573     {
 574       assert(op->as_OpBranch() != NULL, "must be");
 575       LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
 576 
 577       if (opBranch->_info != NULL)     do_info(opBranch->_info);
 578       assert(opBranch->_result->is_illegal(), "not used");
 579       if (opBranch->_stub != NULL)     opBranch->stub()->visit(this);
 580 
 581       break;


1936 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1937   switch(cond) {
1938     case lir_cond_equal:           out->print("[EQ]");      break;
1939     case lir_cond_notEqual:        out->print("[NE]");      break;
1940     case lir_cond_less:            out->print("[LT]");      break;
1941     case lir_cond_lessEqual:       out->print("[LE]");      break;
1942     case lir_cond_greaterEqual:    out->print("[GE]");      break;
1943     case lir_cond_greater:         out->print("[GT]");      break;
1944     case lir_cond_belowEqual:      out->print("[BE]");      break;
1945     case lir_cond_aboveEqual:      out->print("[AE]");      break;
1946     case lir_cond_always:          out->print("[AL]");      break;
1947     default:                       out->print("[%d]",cond); break;
1948   }
1949 }
1950 
1951 // LIR_OpConvert
1952 void LIR_OpConvert::print_instr(outputStream* out) const {
1953   print_bytecode(out, bytecode());
1954   in_opr()->print(out);                  out->print(" ");
1955   result_opr()->print(out);              out->print(" ");
1956 #ifdef PPC32
1957   if(tmp1()->is_valid()) {
1958     tmp1()->print(out); out->print(" ");
1959     tmp2()->print(out); out->print(" ");
1960   }
1961 #endif
1962 }
1963 
1964 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1965   switch(code) {
1966     case Bytecodes::_d2f: out->print("[d2f] "); break;
1967     case Bytecodes::_d2i: out->print("[d2i] "); break;
1968     case Bytecodes::_d2l: out->print("[d2l] "); break;
1969     case Bytecodes::_f2d: out->print("[f2d] "); break;
1970     case Bytecodes::_f2i: out->print("[f2i] "); break;
1971     case Bytecodes::_f2l: out->print("[f2l] "); break;
1972     case Bytecodes::_i2b: out->print("[i2b] "); break;
1973     case Bytecodes::_i2c: out->print("[i2c] "); break;
1974     case Bytecodes::_i2d: out->print("[i2d] "); break;
1975     case Bytecodes::_i2f: out->print("[i2f] "); break;
1976     case Bytecodes::_i2l: out->print("[i2l] "); break;


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