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src/hotspot/cpu/ppc/assembler_ppc.hpp

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rev 47384 : 8188868: PPC64: Support AES intrinsics on Big Endian
Reviewed-by: goetz


2282   inline void stfs(  FloatRegister s, int si16);
2283   inline void stfsx( FloatRegister s, Register b);
2284   inline void stfd(  FloatRegister s, int si16);
2285   inline void stfdx( FloatRegister s, Register b);
2286   inline void lvebx( VectorRegister d, Register s2);
2287   inline void lvehx( VectorRegister d, Register s2);
2288   inline void lvewx( VectorRegister d, Register s2);
2289   inline void lvx(   VectorRegister d, Register s2);
2290   inline void lvxl(  VectorRegister d, Register s2);
2291   inline void stvebx(VectorRegister d, Register s2);
2292   inline void stvehx(VectorRegister d, Register s2);
2293   inline void stvewx(VectorRegister d, Register s2);
2294   inline void stvx(  VectorRegister d, Register s2);
2295   inline void stvxl( VectorRegister d, Register s2);
2296   inline void lvsl(  VectorRegister d, Register s2);
2297   inline void lvsr(  VectorRegister d, Register s2);
2298 
2299   // Endianess specific concatenation of 2 loaded vectors.
2300   inline void load_perm(VectorRegister perm, Register addr);
2301   inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);

2302 
2303   // RegisterOrConstant versions.
2304   // These emitters choose between the versions using two registers and
2305   // those with register and immediate, depending on the content of roc.
2306   // If the constant is not encodable as immediate, instructions to
2307   // load the constant are emitted beforehand. Store instructions need a
2308   // tmp reg if the constant is not encodable as immediate.
2309   // Size unpredictable.
2310   void ld(  Register d, RegisterOrConstant roc, Register s1 = noreg);
2311   void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2312   void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2313   void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2314   void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2315   void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2316   void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2317   void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2318   void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2319   void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2320   void add( Register d, RegisterOrConstant roc, Register s1);
2321   void subf(Register d, RegisterOrConstant roc, Register s1);




2282   inline void stfs(  FloatRegister s, int si16);
2283   inline void stfsx( FloatRegister s, Register b);
2284   inline void stfd(  FloatRegister s, int si16);
2285   inline void stfdx( FloatRegister s, Register b);
2286   inline void lvebx( VectorRegister d, Register s2);
2287   inline void lvehx( VectorRegister d, Register s2);
2288   inline void lvewx( VectorRegister d, Register s2);
2289   inline void lvx(   VectorRegister d, Register s2);
2290   inline void lvxl(  VectorRegister d, Register s2);
2291   inline void stvebx(VectorRegister d, Register s2);
2292   inline void stvehx(VectorRegister d, Register s2);
2293   inline void stvewx(VectorRegister d, Register s2);
2294   inline void stvx(  VectorRegister d, Register s2);
2295   inline void stvxl( VectorRegister d, Register s2);
2296   inline void lvsl(  VectorRegister d, Register s2);
2297   inline void lvsr(  VectorRegister d, Register s2);
2298 
2299   // Endianess specific concatenation of 2 loaded vectors.
2300   inline void load_perm(VectorRegister perm, Register addr);
2301   inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);
2302   inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm);
2303 
2304   // RegisterOrConstant versions.
2305   // These emitters choose between the versions using two registers and
2306   // those with register and immediate, depending on the content of roc.
2307   // If the constant is not encodable as immediate, instructions to
2308   // load the constant are emitted beforehand. Store instructions need a
2309   // tmp reg if the constant is not encodable as immediate.
2310   // Size unpredictable.
2311   void ld(  Register d, RegisterOrConstant roc, Register s1 = noreg);
2312   void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2313   void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2314   void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2315   void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2316   void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2317   void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2318   void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2319   void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2320   void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2321   void add( Register d, RegisterOrConstant roc, Register s1);
2322   void subf(Register d, RegisterOrConstant roc, Register s1);
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