281 // last Java Frame (fills frame anchor) 282 void set_last_Java_frame(Register thread, 283 Register last_java_sp, 284 Register last_java_fp, 285 address last_java_pc); 286 287 // thread in the default location (r15_thread on 64bit) 288 void set_last_Java_frame(Register last_java_sp, 289 Register last_java_fp, 290 address last_java_pc); 291 292 void reset_last_Java_frame(Register thread, bool clear_fp); 293 294 // thread in the default location (r15_thread on 64bit) 295 void reset_last_Java_frame(bool clear_fp); 296 297 // Stores 298 void store_check(Register obj); // store check for obj - register is destroyed afterwards 299 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 300 301 #if INCLUDE_ALL_GCS 302 303 void g1_write_barrier_pre(Register obj, 304 Register pre_val, 305 Register thread, 306 Register tmp, 307 bool tosca_live, 308 bool expand_call); 309 310 void g1_write_barrier_post(Register store_addr, 311 Register new_val, 312 Register thread, 313 Register tmp, 314 Register tmp2); 315 316 #endif // INCLUDE_ALL_GCS 317 318 // split store_check(Register obj) to enhance instruction interleaving 319 void store_check_part_1(Register obj); 320 void store_check_part_2(Register obj); | 281 // last Java Frame (fills frame anchor) 282 void set_last_Java_frame(Register thread, 283 Register last_java_sp, 284 Register last_java_fp, 285 address last_java_pc); 286 287 // thread in the default location (r15_thread on 64bit) 288 void set_last_Java_frame(Register last_java_sp, 289 Register last_java_fp, 290 address last_java_pc); 291 292 void reset_last_Java_frame(Register thread, bool clear_fp); 293 294 // thread in the default location (r15_thread on 64bit) 295 void reset_last_Java_frame(bool clear_fp); 296 297 // Stores 298 void store_check(Register obj); // store check for obj - register is destroyed afterwards 299 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 300 301 void resolve_jobject(Register value, Register thread, Register tmp); 302 void clear_jweak_tag(Register possibly_jweak); 303 304 #if INCLUDE_ALL_GCS 305 306 void g1_write_barrier_pre(Register obj, 307 Register pre_val, 308 Register thread, 309 Register tmp, 310 bool tosca_live, 311 bool expand_call); 312 313 void g1_write_barrier_post(Register store_addr, 314 Register new_val, 315 Register thread, 316 Register tmp, 317 Register tmp2); 318 319 #endif // INCLUDE_ALL_GCS 320 321 // split store_check(Register obj) to enhance instruction interleaving 322 void store_check_part_1(Register obj); 323 void store_check_part_2(Register obj); |