2220 #undef INSN
2221
2222 #define INSN(NAME, opc, opc2) \
2223 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2224 starti; \
2225 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2226 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2227 rf(Vn, 5), rf(Vd, 0); \
2228 }
2229
2230 INSN(absr, 0, 0b100000101110);
2231 INSN(negr, 1, 0b100000101110);
2232 INSN(notr, 1, 0b100000010110);
2233 INSN(addv, 0, 0b110001101110);
2234 INSN(cls, 0, 0b100000010010);
2235 INSN(clz, 1, 0b100000010010);
2236 INSN(cnt, 0, 0b100000010110);
2237
2238 #undef INSN
2239
2240 #define INSN(NAME, op0, cmode0) \
2241 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2242 unsigned cmode = cmode0; \
2243 unsigned op = op0; \
2244 starti; \
2245 assert(lsl == 0 || \
2246 ((T == T4H || T == T8H) && lsl == 8) || \
2247 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2248 cmode |= lsl >> 2; \
2249 if (T == T4H || T == T8H) cmode |= 0b1000; \
2250 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2251 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2252 cmode = 0b1110; \
2253 if (T == T1D || T == T2D) op = 1; \
2254 } \
2255 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2256 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2257 rf(Vd, 0); \
2258 }
2259
2261 INSN(orri, 0, 1);
2262 INSN(mvni, 1, 0);
2263 INSN(bici, 1, 1);
2264
2265 #undef INSN
2266
2267 #define INSN(NAME, op1, op2, op3) \
2268 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2269 starti; \
2270 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2271 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2272 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2273 }
2274
2275 INSN(fadd, 0, 0, 0b110101);
2276 INSN(fdiv, 1, 0, 0b111111);
2277 INSN(fmul, 1, 0, 0b110111);
2278 INSN(fsub, 0, 1, 0b110101);
2279 INSN(fmla, 0, 0, 0b110011);
2280 INSN(fmls, 0, 1, 0b110011);
2281
2282 #undef INSN
2283
2284 #define INSN(NAME, opc) \
2285 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2286 starti; \
2287 assert(T == T4S, "arrangement must be T4S"); \
2288 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2289 }
2290
2291 INSN(sha1c, 0b000000);
2292 INSN(sha1m, 0b001000);
2293 INSN(sha1p, 0b000100);
2294 INSN(sha1su0, 0b001100);
2295 INSN(sha256h2, 0b010100);
2296 INSN(sha256h, 0b010000);
2297 INSN(sha256su1, 0b011000);
2298
2299 #undef INSN
2300
|
2220 #undef INSN
2221
2222 #define INSN(NAME, opc, opc2) \
2223 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2224 starti; \
2225 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2226 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2227 rf(Vn, 5), rf(Vd, 0); \
2228 }
2229
2230 INSN(absr, 0, 0b100000101110);
2231 INSN(negr, 1, 0b100000101110);
2232 INSN(notr, 1, 0b100000010110);
2233 INSN(addv, 0, 0b110001101110);
2234 INSN(cls, 0, 0b100000010010);
2235 INSN(clz, 1, 0b100000010010);
2236 INSN(cnt, 0, 0b100000010110);
2237
2238 #undef INSN
2239
2240 #define INSN(NAME, opc) \
2241 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2242 starti; \
2243 assert(T == T4S, "arrangement must be T4S"); \
2244 f(0b01101110, 31, 24), f(opc, 23), f(0b0110000111110, 22, 10); \
2245 rf(Vn, 5), rf(Vd, 0); \
2246 }
2247
2248 INSN(fmaxv, 0);
2249 INSN(fminv, 1);
2250
2251 #undef INSN
2252
2253 #define INSN(NAME, op0, cmode0) \
2254 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2255 unsigned cmode = cmode0; \
2256 unsigned op = op0; \
2257 starti; \
2258 assert(lsl == 0 || \
2259 ((T == T4H || T == T8H) && lsl == 8) || \
2260 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2261 cmode |= lsl >> 2; \
2262 if (T == T4H || T == T8H) cmode |= 0b1000; \
2263 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2264 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2265 cmode = 0b1110; \
2266 if (T == T1D || T == T2D) op = 1; \
2267 } \
2268 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2269 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2270 rf(Vd, 0); \
2271 }
2272
2274 INSN(orri, 0, 1);
2275 INSN(mvni, 1, 0);
2276 INSN(bici, 1, 1);
2277
2278 #undef INSN
2279
2280 #define INSN(NAME, op1, op2, op3) \
2281 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2282 starti; \
2283 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2284 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2285 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2286 }
2287
2288 INSN(fadd, 0, 0, 0b110101);
2289 INSN(fdiv, 1, 0, 0b111111);
2290 INSN(fmul, 1, 0, 0b110111);
2291 INSN(fsub, 0, 1, 0b110101);
2292 INSN(fmla, 0, 0, 0b110011);
2293 INSN(fmls, 0, 1, 0b110011);
2294 INSN(fmax, 0, 0, 0b111101);
2295 INSN(fmin, 0, 1, 0b111101);
2296
2297 #undef INSN
2298
2299 #define INSN(NAME, opc) \
2300 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2301 starti; \
2302 assert(T == T4S, "arrangement must be T4S"); \
2303 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2304 }
2305
2306 INSN(sha1c, 0b000000);
2307 INSN(sha1m, 0b001000);
2308 INSN(sha1p, 0b000100);
2309 INSN(sha1su0, 0b001100);
2310 INSN(sha256h2, 0b010100);
2311 INSN(sha256h, 0b010000);
2312 INSN(sha256su1, 0b011000);
2313
2314 #undef INSN
2315
|