1104         acond = Assembler::EQ;  // unreachable
1105       }
1106     } else {
1107       switch (op->cond()) {
1108         case lir_cond_equal:        acond = Assembler::EQ; break;
1109         case lir_cond_notEqual:     acond = Assembler::NE; break;
1110         case lir_cond_less:         acond = Assembler::LT; break;
1111         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1112         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1113         case lir_cond_greater:      acond = Assembler::GT; break;
1114         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1115         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1116         default:                    ShouldNotReachHere();
1117           acond = Assembler::EQ;  // unreachable
1118       }
1119     }
1120     __ br(acond,*(op->label()));
1121   }
1122 }
1123 
1124 #if INCLUDE_SHENANDOAHGC
1125 void LIR_Assembler::emit_opShenandoahWriteBarrier(LIR_OpShenandoahWriteBarrier* op) {
1126 
1127   Register obj = op->in_opr()->as_register();
1128   Register res = op->result_opr()->as_register();
1129 
1130   Label done;
1131 
1132   __ block_comment("Shenandoah write barrier {");
1133 
1134   if (res != obj) {
1135     __ mov(res, obj);
1136   }
1137   // Check for null.
1138   if (op->need_null_check()) {
1139     __ cbz(res, done);
1140   }
1141 
1142   __ shenandoah_write_barrier(res);
1143 
1144   __ bind(done);
1145 
1146   __ block_comment("} Shenandoah write barrier");
1147 
1148 }
1149 #endif
1150 
1151 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1152   LIR_Opr src  = op->in_opr();
1153   LIR_Opr dest = op->result_opr();
1154 
1155   switch (op->bytecode()) {
1156     case Bytecodes::_i2f:
1157       {
1158         __ scvtfws(dest->as_float_reg(), src->as_register());
1159         break;
1160       }
1161     case Bytecodes::_i2d:
1162       {
1163         __ scvtfwd(dest->as_double_reg(), src->as_register());
1164         break;
1165       }
1166     case Bytecodes::_l2d:
1167       {
1168         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1169         break;

1104         acond = Assembler::EQ;  // unreachable
1105       }
1106     } else {
1107       switch (op->cond()) {
1108         case lir_cond_equal:        acond = Assembler::EQ; break;
1109         case lir_cond_notEqual:     acond = Assembler::NE; break;
1110         case lir_cond_less:         acond = Assembler::LT; break;
1111         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1112         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1113         case lir_cond_greater:      acond = Assembler::GT; break;
1114         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1115         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1116         default:                    ShouldNotReachHere();
1117           acond = Assembler::EQ;  // unreachable
1118       }
1119     }
1120     __ br(acond,*(op->label()));
1121   }
1122 }
1123 


























1124 
1125 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1126   LIR_Opr src  = op->in_opr();
1127   LIR_Opr dest = op->result_opr();
1128 
1129   switch (op->bytecode()) {
1130     case Bytecodes::_i2f:
1131       {
1132         __ scvtfws(dest->as_float_reg(), src->as_register());
1133         break;
1134       }
1135     case Bytecodes::_i2d:
1136       {
1137         __ scvtfwd(dest->as_double_reg(), src->as_register());
1138         break;
1139       }
1140     case Bytecodes::_l2d:
1141       {
1142         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1143         break;