1127 #endif // !AARCH64
1128     __ b(*(op->ublock()->label()), vs);
1129   }
1130 #endif // __SOFTFP__
1131 
1132   AsmCondition acond = al;
1133   switch (op->cond()) {
1134     case lir_cond_equal:        acond = eq; break;
1135     case lir_cond_notEqual:     acond = ne; break;
1136     case lir_cond_less:         acond = lt; break;
1137     case lir_cond_lessEqual:    acond = le; break;
1138     case lir_cond_greaterEqual: acond = ge; break;
1139     case lir_cond_greater:      acond = gt; break;
1140     case lir_cond_aboveEqual:   acond = hs; break;
1141     case lir_cond_belowEqual:   acond = ls; break;
1142     default: assert(op->cond() == lir_cond_always, "must be");
1143   }
1144   __ b(*(op->label()), acond);
1145 }
1146 
1147 #if INCLUDE_SHENANDOAHGC
1148 void LIR_Assembler::emit_opShenandoahWriteBarrier(LIR_OpShenandoahWriteBarrier* op) {
1149   Unimplemented();
1150 }
1151 #endif
1152 
1153 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1154   LIR_Opr src  = op->in_opr();
1155   LIR_Opr dest = op->result_opr();
1156 
1157   switch (op->bytecode()) {
1158     case Bytecodes::_i2l:
1159 #ifdef AARCH64
1160       __ sign_extend(dest->as_register_lo(), src->as_register(), 32);
1161 #else
1162       move_regs(src->as_register(), dest->as_register_lo());
1163       __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
1164 #endif // AARCH64
1165       break;
1166     case Bytecodes::_l2i:
1167       move_regs(src->as_register_lo(), dest->as_register());
1168       break;
1169     case Bytecodes::_i2b:
1170       __ sign_extend(dest->as_register(), src->as_register(), 8);
1171       break;

1127 #endif // !AARCH64
1128     __ b(*(op->ublock()->label()), vs);
1129   }
1130 #endif // __SOFTFP__
1131 
1132   AsmCondition acond = al;
1133   switch (op->cond()) {
1134     case lir_cond_equal:        acond = eq; break;
1135     case lir_cond_notEqual:     acond = ne; break;
1136     case lir_cond_less:         acond = lt; break;
1137     case lir_cond_lessEqual:    acond = le; break;
1138     case lir_cond_greaterEqual: acond = ge; break;
1139     case lir_cond_greater:      acond = gt; break;
1140     case lir_cond_aboveEqual:   acond = hs; break;
1141     case lir_cond_belowEqual:   acond = ls; break;
1142     default: assert(op->cond() == lir_cond_always, "must be");
1143   }
1144   __ b(*(op->label()), acond);
1145 }
1146 





1147 
1148 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1149   LIR_Opr src  = op->in_opr();
1150   LIR_Opr dest = op->result_opr();
1151 
1152   switch (op->bytecode()) {
1153     case Bytecodes::_i2l:
1154 #ifdef AARCH64
1155       __ sign_extend(dest->as_register_lo(), src->as_register(), 32);
1156 #else
1157       move_regs(src->as_register(), dest->as_register_lo());
1158       __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
1159 #endif // AARCH64
1160       break;
1161     case Bytecodes::_l2i:
1162       move_regs(src->as_register_lo(), dest->as_register());
1163       break;
1164     case Bytecodes::_i2b:
1165       __ sign_extend(dest->as_register(), src->as_register(), 8);
1166       break;