src/hotspot/cpu/arm/macroAssembler_arm.hpp

*** 399,409 ****
    void biased_locking_enter_with_cas(Register obj_reg, Register old_mark_reg, Register new_mark_reg,
                                       Register tmp, Label& slow_case, int* counter_addr);
  
    void resolve_jobject(Register value, Register tmp1, Register tmp2);
  
! #if INCLUDE_ALL_GCS
    // G1 pre-barrier.
    // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
    // If store_addr != noreg, then previous value is loaded from [store_addr];
    // in such case store_addr and new_val registers are preserved;
    // otherwise pre_val register is preserved.
--- 399,409 ----
    void biased_locking_enter_with_cas(Register obj_reg, Register old_mark_reg, Register new_mark_reg,
                                       Register tmp, Label& slow_case, int* counter_addr);
  
    void resolve_jobject(Register value, Register tmp1, Register tmp2);
  
! #if INCLUDE_G1GC
    // G1 pre-barrier.
    // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
    // If store_addr != noreg, then previous value is loaded from [store_addr];
    // in such case store_addr and new_val registers are preserved;
    // otherwise pre_val register is preserved.
*** 418,428 ****
    void g1_write_barrier_post(Register store_addr,
                               Register new_val,
                               Register tmp1,
                               Register tmp2,
                               Register tmp3);
! #endif // INCLUDE_ALL_GCS
  
  #ifndef AARCH64
    void nop() {
      mov(R0, R0);
    }
--- 418,428 ----
    void g1_write_barrier_post(Register store_addr,
                               Register new_val,
                               Register tmp1,
                               Register tmp2,
                               Register tmp3);
! #endif // INCLUDE_G1GC
  
  #ifndef AARCH64
    void nop() {
      mov(R0, R0);
    }