src/hotspot/cpu/arm/templateTable_arm.cpp

*** 191,201 ****
                           bool precise,
                           bool is_null) {
  
    assert_different_registers(obj.base(), new_val, tmp1, tmp2, tmp3, noreg);
    switch (barrier) {
! #if INCLUDE_ALL_GCS
      case BarrierSet::G1BarrierSet:
        {
          // flatten object address if needed
          assert (obj.mode() == basic_offset, "pre- or post-indexing is not supported here");
  
--- 191,201 ----
                           bool precise,
                           bool is_null) {
  
    assert_different_registers(obj.base(), new_val, tmp1, tmp2, tmp3, noreg);
    switch (barrier) {
! #if INCLUDE_G1GC
      case BarrierSet::G1BarrierSet:
        {
          // flatten object address if needed
          assert (obj.mode() == basic_offset, "pre- or post-indexing is not supported here");
  
*** 226,236 ****
            val_to_store = noreg;
            __ g1_write_barrier_post(store_addr, new_val, tmp1, tmp2, tmp3);
          }
        }
        break;
! #endif // INCLUDE_ALL_GCS
      case BarrierSet::CardTableBarrierSet:
        {
          if (is_null) {
            __ store_heap_oop_null(new_val, obj);
          } else {
--- 226,236 ----
            val_to_store = noreg;
            __ g1_write_barrier_post(store_addr, new_val, tmp1, tmp2, tmp3);
          }
        }
        break;
! #endif // INCLUDE_G1GC
      case BarrierSet::CardTableBarrierSet:
        {
          if (is_null) {
            __ store_heap_oop_null(new_val, obj);
          } else {