8164 %}
8165
8166 instruct xchgP( memory mem, rRegP newval) %{
8167 match(Set newval (GetAndSetP mem newval));
8168 format %{ "XCHGQ $newval,[$mem]" %}
8169 ins_encode %{
8170 __ xchgq($newval$$Register, $mem$$Address);
8171 %}
8172 ins_pipe( pipe_cmpxchg );
8173 %}
8174
8175 instruct xchgN( memory mem, rRegN newval) %{
8176 match(Set newval (GetAndSetN mem newval));
8177 format %{ "XCHGL $newval,$mem]" %}
8178 ins_encode %{
8179 __ xchgl($newval$$Register, $mem$$Address);
8180 %}
8181 ins_pipe( pipe_cmpxchg );
8182 %}
8183
8184 //----------Subtraction Instructions-------------------------------------------
8185
8186 // Integer Subtraction Instructions
8187 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8188 %{
8189 match(Set dst (SubI dst src));
8190 effect(KILL cr);
8191
8192 format %{ "subl $dst, $src\t# int" %}
8193 opcode(0x2B);
8194 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8195 ins_pipe(ialu_reg_reg);
8196 %}
8197
8198 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8199 %{
8200 match(Set dst (SubI dst src));
8201 effect(KILL cr);
8202
8203 format %{ "subl $dst, $src\t# int" %}
|
8164 %}
8165
8166 instruct xchgP( memory mem, rRegP newval) %{
8167 match(Set newval (GetAndSetP mem newval));
8168 format %{ "XCHGQ $newval,[$mem]" %}
8169 ins_encode %{
8170 __ xchgq($newval$$Register, $mem$$Address);
8171 %}
8172 ins_pipe( pipe_cmpxchg );
8173 %}
8174
8175 instruct xchgN( memory mem, rRegN newval) %{
8176 match(Set newval (GetAndSetN mem newval));
8177 format %{ "XCHGL $newval,$mem]" %}
8178 ins_encode %{
8179 __ xchgl($newval$$Register, $mem$$Address);
8180 %}
8181 ins_pipe( pipe_cmpxchg );
8182 %}
8183
8184 //----------Abs Instructions-------------------------------------------
8185
8186 // Integer Absolute Instructions
8187 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
8188 %{
8189 match(Set dst (AbsI src));
8190 effect(TEMP dst, TEMP tmp, KILL cr);
8191 format %{ "movl $tmp, $src\n\t"
8192 "sarl $tmp, 31\n\t"
8193 "movl $dst, $src\n\t"
8194 "xorl $dst, $tmp\n\t"
8195 "subl $dst, $tmp\n"
8196 %}
8197 ins_encode %{
8198 __ movl($tmp$$Register, $src$$Register);
8199 __ sarl($tmp$$Register, 31);
8200 __ movl($dst$$Register, $src$$Register);
8201 __ xorl($dst$$Register, $tmp$$Register);
8202 __ subl($dst$$Register, $tmp$$Register);
8203 %}
8204
8205 ins_pipe(ialu_reg_reg);
8206 %}
8207
8208 // Long Absolute Instructions
8209 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
8210 %{
8211 match(Set dst (AbsL src));
8212 effect(TEMP dst, TEMP tmp, KILL cr);
8213 format %{ "movq $tmp, $src\n\t"
8214 "sarq $tmp, 63\n\t"
8215 "movq $dst, $src\n\t"
8216 "xorq $dst, $tmp\n\t"
8217 "subq $dst, $tmp\n"
8218 %}
8219 ins_encode %{
8220 __ movq($tmp$$Register, $src$$Register);
8221 __ sarq($tmp$$Register, 63);
8222 __ movq($dst$$Register, $src$$Register);
8223 __ xorq($dst$$Register, $tmp$$Register);
8224 __ subq($dst$$Register, $tmp$$Register);
8225 %}
8226
8227 ins_pipe(ialu_reg_reg);
8228 %}
8229
8230 //----------Subtraction Instructions-------------------------------------------
8231
8232 // Integer Subtraction Instructions
8233 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8234 %{
8235 match(Set dst (SubI dst src));
8236 effect(KILL cr);
8237
8238 format %{ "subl $dst, $src\t# int" %}
8239 opcode(0x2B);
8240 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8241 ins_pipe(ialu_reg_reg);
8242 %}
8243
8244 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8245 %{
8246 match(Set dst (SubI dst src));
8247 effect(KILL cr);
8248
8249 format %{ "subl $dst, $src\t# int" %}
|