3305 // necessarily the start) requires. If > 1, a compute_padding()
3306 // function must be provided for the instruction
3307
3308 //----------OPERANDS-----------------------------------------------------------
3309 // Operand definitions must precede instruction definitions for correct parsing
3310 // in the ADLC because operands constitute user defined types which are used in
3311 // instruction definitions.
3312
3313 //----------Simple Operands----------------------------------------------------
3314 // Immediate Operands
3315 // Integer Immediate
3316 operand immI() %{
3317 match(ConI);
3318
3319 op_cost(10);
3320 format %{ %}
3321 interface(CONST_INTER);
3322 %}
3323
3324 // Constant for test vs zero
3325 operand immI0() %{
3326 predicate(n->get_int() == 0);
3327 match(ConI);
3328
3329 op_cost(0);
3330 format %{ %}
3331 interface(CONST_INTER);
3332 %}
3333
3334 // Constant for increment
3335 operand immI1() %{
3336 predicate(n->get_int() == 1);
3337 match(ConI);
3338
3339 op_cost(0);
3340 format %{ %}
3341 interface(CONST_INTER);
3342 %}
3343
3344 // Constant for decrement
3345 operand immI_M1() %{
3346 predicate(n->get_int() == -1);
3347 match(ConI);
3348
3349 op_cost(0);
3350 format %{ %}
3351 interface(CONST_INTER);
3352 %}
3353
3354 // Valid scale values for addressing modes
3355 operand immI2() %{
3409 %}
3410
3411 operand immI_1_31() %{
3412 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3413 match(ConI);
3414
3415 op_cost(0);
3416 format %{ %}
3417 interface(CONST_INTER);
3418 %}
3419
3420 operand immI_32_63() %{
3421 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3422 match(ConI);
3423 op_cost(0);
3424
3425 format %{ %}
3426 interface(CONST_INTER);
3427 %}
3428
3429 operand immI_1() %{
3430 predicate( n->get_int() == 1 );
3431 match(ConI);
3432
3433 op_cost(0);
3434 format %{ %}
3435 interface(CONST_INTER);
3436 %}
3437
3438 operand immI_2() %{
3439 predicate( n->get_int() == 2 );
3440 match(ConI);
3441
3442 op_cost(0);
3443 format %{ %}
3444 interface(CONST_INTER);
3445 %}
3446
3447 operand immI_3() %{
3448 predicate( n->get_int() == 3 );
3449 match(ConI);
3450
3451 op_cost(0);
3452 format %{ %}
3453 interface(CONST_INTER);
3454 %}
3455
3456 // Pointer Immediate
3457 operand immP() %{
3458 match(ConP);
3459
3460 op_cost(10);
3461 format %{ %}
3462 interface(CONST_INTER);
3463 %}
3464
3465 // NULL Pointer Immediate
3466 operand immP0() %{
3467 predicate( n->get_ptr() == 0 );
3468 match(ConP);
3805 match(eCXRegP);
3806 match(eDIRegP);
3807 match(eRegP);
3808
3809 format %{ %}
3810 interface(REG_INTER);
3811 %}
3812
3813 operand eRegP() %{
3814 constraint(ALLOC_IN_RC(int_reg));
3815 match(RegP);
3816 match(eAXRegP);
3817 match(eBXRegP);
3818 match(eCXRegP);
3819 match(eDIRegP);
3820
3821 format %{ %}
3822 interface(REG_INTER);
3823 %}
3824
3825 // On windows95, EBP is not safe to use for implicit null tests.
3826 operand eRegP_no_EBP() %{
3827 constraint(ALLOC_IN_RC(int_reg_no_ebp));
3828 match(RegP);
3829 match(eAXRegP);
3830 match(eBXRegP);
3831 match(eCXRegP);
3832 match(eDIRegP);
3833
3834 op_cost(100);
3835 format %{ %}
3836 interface(REG_INTER);
3837 %}
3838
3839 operand naxRegP() %{
3840 constraint(ALLOC_IN_RC(nax_reg));
3841 match(RegP);
3842 match(eBXRegP);
3843 match(eDXRegP);
3844 match(eCXRegP);
3938 %}
3939
3940 operand eBCXRegL( eRegL reg ) %{
3941 constraint(ALLOC_IN_RC(ebcx_reg));
3942 match(reg);
3943
3944 format %{ "EBX:ECX" %}
3945 interface(REG_INTER);
3946 %}
3947
3948 // Special case for integer high multiply
3949 operand eADXRegL_low_only() %{
3950 constraint(ALLOC_IN_RC(eadx_reg));
3951 match(RegL);
3952
3953 format %{ "EAX" %}
3954 interface(REG_INTER);
3955 %}
3956
3957 // Flags register, used as output of compare instructions
3958 operand eFlagsReg() %{
3959 constraint(ALLOC_IN_RC(int_flags));
3960 match(RegFlags);
3961
3962 format %{ "EFLAGS" %}
3963 interface(REG_INTER);
3964 %}
3965
3966 // Flags register, used as output of FLOATING POINT compare instructions
3967 operand eFlagsRegU() %{
3968 constraint(ALLOC_IN_RC(int_flags));
3969 match(RegFlags);
3970
3971 format %{ "EFLAGS_U" %}
3972 interface(REG_INTER);
3973 %}
3974
3975 operand eFlagsRegUCF() %{
3976 constraint(ALLOC_IN_RC(int_flags));
3977 match(RegFlags);
4067 %}
4068
4069 // Float register operands
4070 operand regFPR1(regFPR reg) %{
4071 predicate( UseSSE < 2 );
4072 constraint(ALLOC_IN_RC(fp_flt_reg0));
4073 match(reg);
4074 format %{ "FPR1" %}
4075 interface(REG_INTER);
4076 %}
4077
4078 // XMM Float register operands
4079 operand regF() %{
4080 predicate( UseSSE>=1 );
4081 constraint(ALLOC_IN_RC(float_reg_legacy));
4082 match(RegF);
4083 format %{ %}
4084 interface(REG_INTER);
4085 %}
4086
4087 // Float register operands
4088 operand vlRegF() %{
4089 constraint(ALLOC_IN_RC(float_reg_vl));
4090 match(RegF);
4091
4092 format %{ %}
4093 interface(REG_INTER);
4094 %}
4095
4096 // XMM Double register operands
4097 operand regD() %{
4098 predicate( UseSSE>=2 );
4099 constraint(ALLOC_IN_RC(double_reg_legacy));
4100 match(RegD);
4101 format %{ %}
4102 interface(REG_INTER);
4103 %}
4104
4105 // Double register operands
4106 operand vlRegD() %{
4107 constraint(ALLOC_IN_RC(double_reg_vl));
4108 match(RegD);
4109
4110 format %{ %}
4111 interface(REG_INTER);
4112 %}
4113
4114 //----------Memory Operands----------------------------------------------------
4115 // Direct Memory Operand
4116 operand direct(immP addr) %{
4117 match(addr);
4118
4119 format %{ "[$addr]" %}
4120 interface(MEMORY_INTER) %{
4121 base(0xFFFFFFFF);
4122 index(0x4);
4123 scale(0x0);
4124 disp($addr);
4125 %}
5836 match(Set dst (LoadP mem));
5837
5838 ins_cost(125);
5839 format %{ "MOV $dst,$mem" %}
5840 opcode(0x8B);
5841 ins_encode( OpcP, RegMem(dst,mem));
5842 ins_pipe( ialu_reg_mem );
5843 %}
5844
5845 // Load Klass Pointer
5846 instruct loadKlass(eRegP dst, memory mem) %{
5847 match(Set dst (LoadKlass mem));
5848
5849 ins_cost(125);
5850 format %{ "MOV $dst,$mem" %}
5851 opcode(0x8B);
5852 ins_encode( OpcP, RegMem(dst,mem));
5853 ins_pipe( ialu_reg_mem );
5854 %}
5855
5856 // Load Double
5857 instruct loadDPR(regDPR dst, memory mem) %{
5858 predicate(UseSSE<=1);
5859 match(Set dst (LoadD mem));
5860
5861 ins_cost(150);
5862 format %{ "FLD_D ST,$mem\n\t"
5863 "FSTP $dst" %}
5864 opcode(0xDD); /* DD /0 */
5865 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5866 Pop_Reg_DPR(dst) );
5867 ins_pipe( fpu_reg_mem );
5868 %}
5869
5870 // Load Double to XMM
5871 instruct loadD(regD dst, memory mem) %{
5872 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
5873 match(Set dst (LoadD mem));
5874 ins_cost(145);
5875 format %{ "MOVSD $dst,$mem" %}
5961 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
5962 match(Set dst mem);
5963
5964 ins_cost(110);
5965 format %{ "LEA $dst,$mem" %}
5966 opcode(0x8D);
5967 ins_encode( OpcP, RegMem(dst,mem));
5968 ins_pipe( ialu_reg_reg_fat );
5969 %}
5970
5971 // Load Constant
5972 instruct loadConI(rRegI dst, immI src) %{
5973 match(Set dst src);
5974
5975 format %{ "MOV $dst,$src" %}
5976 ins_encode( LdImmI(dst, src) );
5977 ins_pipe( ialu_reg_fat );
5978 %}
5979
5980 // Load Constant zero
5981 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
5982 match(Set dst src);
5983 effect(KILL cr);
5984
5985 ins_cost(50);
5986 format %{ "XOR $dst,$dst" %}
5987 opcode(0x33); /* + rd */
5988 ins_encode( OpcP, RegReg( dst, dst ) );
5989 ins_pipe( ialu_reg );
5990 %}
5991
5992 instruct loadConP(eRegP dst, immP src) %{
5993 match(Set dst src);
5994
5995 format %{ "MOV $dst,$src" %}
5996 opcode(0xB8); /* + rd */
5997 ins_encode( LdImmP(dst, src) );
5998 ins_pipe( ialu_reg_fat );
5999 %}
6000
6001 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7073 match(Set dst (AddI dst src));
7074 effect(KILL cr);
7075
7076 size(2);
7077 format %{ "ADD $dst,$src" %}
7078 opcode(0x03);
7079 ins_encode( OpcP, RegReg( dst, src) );
7080 ins_pipe( ialu_reg_reg );
7081 %}
7082
7083 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7084 match(Set dst (AddI dst src));
7085 effect(KILL cr);
7086
7087 format %{ "ADD $dst,$src" %}
7088 opcode(0x81, 0x00); /* /0 id */
7089 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7090 ins_pipe( ialu_reg );
7091 %}
7092
7093 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7094 predicate(UseIncDec);
7095 match(Set dst (AddI dst src));
7096 effect(KILL cr);
7097
7098 size(1);
7099 format %{ "INC $dst" %}
7100 opcode(0x40); /* */
7101 ins_encode( Opc_plus( primary, dst ) );
7102 ins_pipe( ialu_reg );
7103 %}
7104
7105 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7106 match(Set dst (AddI src0 src1));
7107 ins_cost(110);
7108
7109 format %{ "LEA $dst,[$src0 + $src1]" %}
7110 opcode(0x8D); /* 0x8D /r */
7111 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7112 ins_pipe( ialu_reg_reg );
7113 %}
7173
7174 ins_cost(150);
7175 format %{ "ADD $dst,$src" %}
7176 opcode(0x01); /* Opcode 01 /r */
7177 ins_encode( OpcP, RegMem( src, dst ) );
7178 ins_pipe( ialu_mem_reg );
7179 %}
7180
7181 // Add Memory with Immediate
7182 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7183 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7184 effect(KILL cr);
7185
7186 ins_cost(125);
7187 format %{ "ADD $dst,$src" %}
7188 opcode(0x81); /* Opcode 81 /0 id */
7189 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7190 ins_pipe( ialu_mem_imm );
7191 %}
7192
7193 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7194 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7195 effect(KILL cr);
7196
7197 ins_cost(125);
7198 format %{ "INC $dst" %}
7199 opcode(0xFF); /* Opcode FF /0 */
7200 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7201 ins_pipe( ialu_mem_imm );
7202 %}
7203
7204 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7205 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7206 effect(KILL cr);
7207
7208 ins_cost(125);
7209 format %{ "DEC $dst" %}
7210 opcode(0xFF); /* Opcode FF /1 */
7211 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7212 ins_pipe( ialu_mem_imm );
7213 %}
7542
7543 ins_cost(125);
7544 format %{ "SUB $dst,$src" %}
7545 opcode(0x2B);
7546 ins_encode( OpcP, RegMem( dst, src) );
7547 ins_pipe( ialu_reg_mem );
7548 %}
7549
7550 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7551 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7552 effect(KILL cr);
7553
7554 ins_cost(150);
7555 format %{ "SUB $dst,$src" %}
7556 opcode(0x29); /* Opcode 29 /r */
7557 ins_encode( OpcP, RegMem( src, dst ) );
7558 ins_pipe( ialu_mem_reg );
7559 %}
7560
7561 // Subtract from a pointer
7562 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7563 match(Set dst (AddP dst (SubI zero src)));
7564 effect(KILL cr);
7565
7566 size(2);
7567 format %{ "SUB $dst,$src" %}
7568 opcode(0x2B);
7569 ins_encode( OpcP, RegReg( dst, src) );
7570 ins_pipe( ialu_reg_reg );
7571 %}
7572
7573 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7574 match(Set dst (SubI zero dst));
7575 effect(KILL cr);
7576
7577 size(2);
7578 format %{ "NEG $dst" %}
7579 opcode(0xF7,0x03); // Opcode F7 /3
7580 ins_encode( OpcP, RegOpc( dst ) );
7581 ins_pipe( ialu_reg );
7582 %}
7583
7584 //----------Multiplication/Division Instructions-------------------------------
7585 // Integer Multiplication Instructions
7586 // Multiply Register
7587 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7588 match(Set dst (MulI dst src));
7589 effect(KILL cr);
7590
7591 size(3);
7592 ins_cost(300);
7593 format %{ "IMUL $dst,$src" %}
8007 __ jmpb(Ldone);
8008
8009 __ bind(Lpos);
8010 __ divl($tmp$$Register);
8011 __ movl($dst$$Register, $tmp2$$Register);
8012
8013 __ bind(Lfast);
8014 // fast path: src is positive
8015 __ divl($tmp$$Register);
8016
8017 __ bind(Ldone);
8018 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8019 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8020
8021 %}
8022 ins_pipe( pipe_slow );
8023 %}
8024
8025 // Integer Shift Instructions
8026 // Shift Left by one
8027 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8028 match(Set dst (LShiftI dst shift));
8029 effect(KILL cr);
8030
8031 size(2);
8032 format %{ "SHL $dst,$shift" %}
8033 opcode(0xD1, 0x4); /* D1 /4 */
8034 ins_encode( OpcP, RegOpc( dst ) );
8035 ins_pipe( ialu_reg );
8036 %}
8037
8038 // Shift Left by 8-bit immediate
8039 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8040 match(Set dst (LShiftI dst shift));
8041 effect(KILL cr);
8042
8043 size(3);
8044 format %{ "SHL $dst,$shift" %}
8045 opcode(0xC1, 0x4); /* C1 /4 ib */
8046 ins_encode( RegOpcImm( dst, shift) );
8047 ins_pipe( ialu_reg );
8048 %}
8049
8050 // Shift Left by variable
8051 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8052 match(Set dst (LShiftI dst shift));
8053 effect(KILL cr);
8054
8055 size(2);
8056 format %{ "SHL $dst,$shift" %}
8057 opcode(0xD3, 0x4); /* D3 /4 */
8058 ins_encode( OpcP, RegOpc( dst ) );
8059 ins_pipe( ialu_reg_reg );
8060 %}
8061
8062 // Arithmetic shift right by one
8063 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8064 match(Set dst (RShiftI dst shift));
8065 effect(KILL cr);
8066
8067 size(2);
8068 format %{ "SAR $dst,$shift" %}
8069 opcode(0xD1, 0x7); /* D1 /7 */
8070 ins_encode( OpcP, RegOpc( dst ) );
8071 ins_pipe( ialu_reg );
8072 %}
8073
8074 // Arithmetic shift right by one
8075 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8076 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8077 effect(KILL cr);
8078 format %{ "SAR $dst,$shift" %}
8079 opcode(0xD1, 0x7); /* D1 /7 */
8080 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8081 ins_pipe( ialu_mem_imm );
8082 %}
8083
8084 // Arithmetic Shift Right by 8-bit immediate
8085 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8086 match(Set dst (RShiftI dst shift));
8087 effect(KILL cr);
8088
8089 size(3);
8090 format %{ "SAR $dst,$shift" %}
8091 opcode(0xC1, 0x7); /* C1 /7 ib */
8092 ins_encode( RegOpcImm( dst, shift ) );
8093 ins_pipe( ialu_mem_imm );
8094 %}
8095
8100
8101 format %{ "SAR $dst,$shift" %}
8102 opcode(0xC1, 0x7); /* C1 /7 ib */
8103 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8104 ins_pipe( ialu_mem_imm );
8105 %}
8106
8107 // Arithmetic Shift Right by variable
8108 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8109 match(Set dst (RShiftI dst shift));
8110 effect(KILL cr);
8111
8112 size(2);
8113 format %{ "SAR $dst,$shift" %}
8114 opcode(0xD3, 0x7); /* D3 /7 */
8115 ins_encode( OpcP, RegOpc( dst ) );
8116 ins_pipe( ialu_reg_reg );
8117 %}
8118
8119 // Logical shift right by one
8120 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8121 match(Set dst (URShiftI dst shift));
8122 effect(KILL cr);
8123
8124 size(2);
8125 format %{ "SHR $dst,$shift" %}
8126 opcode(0xD1, 0x5); /* D1 /5 */
8127 ins_encode( OpcP, RegOpc( dst ) );
8128 ins_pipe( ialu_reg );
8129 %}
8130
8131 // Logical Shift Right by 8-bit immediate
8132 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8133 match(Set dst (URShiftI dst shift));
8134 effect(KILL cr);
8135
8136 size(3);
8137 format %{ "SHR $dst,$shift" %}
8138 opcode(0xC1, 0x5); /* C1 /5 ib */
8139 ins_encode( RegOpcImm( dst, shift) );
8140 ins_pipe( ialu_reg );
8256 ins_encode %{
8257 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8258 %}
8259 ins_pipe(ialu_reg);
8260 %}
8261
8262 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
8263 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
8264 predicate(UseBMI1Instructions);
8265 effect(KILL cr);
8266
8267 ins_cost(125);
8268 format %{ "ANDNL $dst, $src1, $src2" %}
8269
8270 ins_encode %{
8271 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8272 %}
8273 ins_pipe(ialu_reg_mem);
8274 %}
8275
8276 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
8277 match(Set dst (AndI (SubI imm_zero src) src));
8278 predicate(UseBMI1Instructions);
8279 effect(KILL cr);
8280
8281 format %{ "BLSIL $dst, $src" %}
8282
8283 ins_encode %{
8284 __ blsil($dst$$Register, $src$$Register);
8285 %}
8286 ins_pipe(ialu_reg);
8287 %}
8288
8289 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
8290 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8291 predicate(UseBMI1Instructions);
8292 effect(KILL cr);
8293
8294 ins_cost(125);
8295 format %{ "BLSIL $dst, $src" %}
8296
8297 ins_encode %{
8298 __ blsil($dst$$Register, $src$$Address);
8299 %}
8300 ins_pipe(ialu_reg_mem);
8301 %}
8302
8303 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8304 %{
8305 match(Set dst (XorI (AddI src minus_1) src));
8306 predicate(UseBMI1Instructions);
8307 effect(KILL cr);
8308
8309 format %{ "BLSMSKL $dst, $src" %}
8421 opcode(0x09); /* Opcode 09 /r */
8422 ins_encode( OpcP, RegMem( src, dst ) );
8423 ins_pipe( ialu_mem_reg );
8424 %}
8425
8426 // Or Memory with Immediate
8427 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8428 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8429 effect(KILL cr);
8430
8431 ins_cost(125);
8432 format %{ "OR $dst,$src" %}
8433 opcode(0x81,0x1); /* Opcode 81 /1 id */
8434 // ins_encode( MemImm( dst, src) );
8435 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8436 ins_pipe( ialu_mem_imm );
8437 %}
8438
8439 // ROL/ROR
8440 // ROL expand
8441 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8442 effect(USE_DEF dst, USE shift, KILL cr);
8443
8444 format %{ "ROL $dst, $shift" %}
8445 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8446 ins_encode( OpcP, RegOpc( dst ));
8447 ins_pipe( ialu_reg );
8448 %}
8449
8450 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8451 effect(USE_DEF dst, USE shift, KILL cr);
8452
8453 format %{ "ROL $dst, $shift" %}
8454 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8455 ins_encode( RegOpcImm(dst, shift) );
8456 ins_pipe(ialu_reg);
8457 %}
8458
8459 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8460 effect(USE_DEF dst, USE shift, KILL cr);
8461
8462 format %{ "ROL $dst, $shift" %}
8463 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8464 ins_encode(OpcP, RegOpc(dst));
8465 ins_pipe( ialu_reg_reg );
8466 %}
8467 // end of ROL expand
8468
8469 // ROL 32bit by one once
8470 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8471 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8472
8473 expand %{
8474 rolI_eReg_imm1(dst, lshift, cr);
8475 %}
8476 %}
8477
8478 // ROL 32bit var by imm8 once
8479 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8480 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8481 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8482
8483 expand %{
8484 rolI_eReg_imm8(dst, lshift, cr);
8485 %}
8486 %}
8487
8488 // ROL 32bit var by var once
8489 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8490 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8491
8492 expand %{
8493 rolI_eReg_CL(dst, shift, cr);
8494 %}
8495 %}
8496
8497 // ROL 32bit var by var once
8498 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8499 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8500
8501 expand %{
8502 rolI_eReg_CL(dst, shift, cr);
8503 %}
8504 %}
8505
8506 // ROR expand
8507 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8508 effect(USE_DEF dst, USE shift, KILL cr);
8509
8510 format %{ "ROR $dst, $shift" %}
8511 opcode(0xD1,0x1); /* Opcode D1 /1 */
8512 ins_encode( OpcP, RegOpc( dst ) );
8513 ins_pipe( ialu_reg );
8514 %}
8515
8516 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8517 effect (USE_DEF dst, USE shift, KILL cr);
8518
8519 format %{ "ROR $dst, $shift" %}
8520 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8521 ins_encode( RegOpcImm(dst, shift) );
8522 ins_pipe( ialu_reg );
8523 %}
8524
8525 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8526 effect(USE_DEF dst, USE shift, KILL cr);
8527
8528 format %{ "ROR $dst, $shift" %}
8529 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8530 ins_encode(OpcP, RegOpc(dst));
8531 ins_pipe( ialu_reg_reg );
8532 %}
8533 // end of ROR expand
8534
8535 // ROR right once
8536 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8537 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8538
8539 expand %{
8540 rorI_eReg_imm1(dst, rshift, cr);
8541 %}
8542 %}
8543
8544 // ROR 32bit by immI8 once
8545 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8546 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8547 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8548
8549 expand %{
8550 rorI_eReg_imm8(dst, rshift, cr);
8551 %}
8552 %}
8553
8554 // ROR 32bit var by var once
8555 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8556 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8557
8558 expand %{
8559 rorI_eReg_CL(dst, shift, cr);
8560 %}
8561 %}
8562
8563 // ROR 32bit var by var once
8564 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8565 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8566
8567 expand %{
8568 rorI_eReg_CL(dst, shift, cr);
8569 %}
8570 %}
8571
8572 // Xor Instructions
8573 // Xor Register with Register
8574 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8575 match(Set dst (XorI dst src));
8703
8704 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8705 format %{ "XOR $dst,$dst\n\t"
8706 "CMP $p,$q\n\t"
8707 "SETlt $dst\n\t"
8708 "NEG $dst" %}
8709 ins_encode %{
8710 Register Rp = $p$$Register;
8711 Register Rq = $q$$Register;
8712 Register Rd = $dst$$Register;
8713 Label done;
8714 __ xorl(Rd, Rd);
8715 __ cmpl(Rp, Rq);
8716 __ setb(Assembler::less, Rd);
8717 __ negl(Rd);
8718 %}
8719
8720 ins_pipe(pipe_slow);
8721 %}
8722
8723 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8724 match(Set dst (CmpLTMask dst zero));
8725 effect(DEF dst, KILL cr);
8726 ins_cost(100);
8727
8728 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8729 ins_encode %{
8730 __ sarl($dst$$Register, 31);
8731 %}
8732 ins_pipe(ialu_reg);
8733 %}
8734
8735 /* better to save a register than avoid a branch */
8736 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8737 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8738 effect(KILL cr);
8739 ins_cost(400);
8740 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8741 "JGE done\n\t"
8742 "ADD $p,$y\n"
8743 "done: " %}
8817 match(Set cr (OverflowSubI op1 op2));
8818
8819 format %{ "CMP $op1, $op2\t# overflow check int" %}
8820 ins_encode %{
8821 __ cmpl($op1$$Register, $op2$$Register);
8822 %}
8823 ins_pipe(ialu_reg_reg);
8824 %}
8825
8826 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2)
8827 %{
8828 match(Set cr (OverflowSubI op1 op2));
8829
8830 format %{ "CMP $op1, $op2\t# overflow check int" %}
8831 ins_encode %{
8832 __ cmpl($op1$$Register, $op2$$constant);
8833 %}
8834 ins_pipe(ialu_reg_reg);
8835 %}
8836
8837 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
8838 %{
8839 match(Set cr (OverflowSubI zero op2));
8840 effect(DEF cr, USE_KILL op2);
8841
8842 format %{ "NEG $op2\t# overflow check int" %}
8843 ins_encode %{
8844 __ negl($op2$$Register);
8845 %}
8846 ins_pipe(ialu_reg_reg);
8847 %}
8848
8849 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8850 %{
8851 match(Set cr (OverflowMulI op1 op2));
8852 effect(DEF cr, USE_KILL op1, USE op2);
8853
8854 format %{ "IMUL $op1, $op2\t# overflow check int" %}
8855 ins_encode %{
8856 __ imull($op1$$Register, $op2$$Register);
8857 %}
11955 match(Set cr (CmpI op1 op2));
11956 effect( DEF cr, USE op1 );
11957 format %{ "CMP $op1,$op2" %}
11958 opcode(0x81,0x07); /* Opcode 81 /7 */
11959 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11960 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11961 ins_pipe( ialu_cr_reg_imm );
11962 %}
11963
11964 // Cisc-spilled version of cmpI_eReg
11965 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11966 match(Set cr (CmpI op1 (LoadI op2)));
11967
11968 format %{ "CMP $op1,$op2" %}
11969 ins_cost(500);
11970 opcode(0x3B); /* Opcode 3B /r */
11971 ins_encode( OpcP, RegMem( op1, op2) );
11972 ins_pipe( ialu_cr_reg_mem );
11973 %}
11974
11975 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11976 match(Set cr (CmpI src zero));
11977 effect( DEF cr, USE src );
11978
11979 format %{ "TEST $src,$src" %}
11980 opcode(0x85);
11981 ins_encode( OpcP, RegReg( src, src ) );
11982 ins_pipe( ialu_cr_reg_imm );
11983 %}
11984
11985 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11986 match(Set cr (CmpI (AndI src con) zero));
11987
11988 format %{ "TEST $src,$con" %}
11989 opcode(0xF7,0x00);
11990 ins_encode( OpcP, RegOpc(src), Con32(con) );
11991 ins_pipe( ialu_cr_reg_imm );
11992 %}
11993
11994 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11995 match(Set cr (CmpI (AndI src mem) zero));
11996
11997 format %{ "TEST $src,$mem" %}
11998 opcode(0x85);
11999 ins_encode( OpcP, RegMem( src, mem ) );
12000 ins_pipe( ialu_cr_reg_mem );
12001 %}
12002
12003 // Unsigned compare Instructions; really, same as signed except they
12004 // produce an eFlagsRegU instead of eFlagsReg.
12005 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
12006 match(Set cr (CmpU op1 op2));
12007
12008 format %{ "CMPu $op1,$op2" %}
12009 opcode(0x3B); /* Opcode 3B /r */
12010 ins_encode( OpcP, RegReg( op1, op2) );
12011 ins_pipe( ialu_cr_reg_reg );
12012 %}
12013
12014 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
12024 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
12025 match(Set cr (CmpU op1 (LoadI op2)));
12026
12027 format %{ "CMPu $op1,$op2" %}
12028 ins_cost(500);
12029 opcode(0x3B); /* Opcode 3B /r */
12030 ins_encode( OpcP, RegMem( op1, op2) );
12031 ins_pipe( ialu_cr_reg_mem );
12032 %}
12033
12034 // // Cisc-spilled version of cmpU_eReg
12035 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
12036 // match(Set cr (CmpU (LoadI op1) op2));
12037 //
12038 // format %{ "CMPu $op1,$op2" %}
12039 // ins_cost(500);
12040 // opcode(0x39); /* Opcode 39 /r */
12041 // ins_encode( OpcP, RegMem( op1, op2) );
12042 //%}
12043
12044 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
12045 match(Set cr (CmpU src zero));
12046
12047 format %{ "TESTu $src,$src" %}
12048 opcode(0x85);
12049 ins_encode( OpcP, RegReg( src, src ) );
12050 ins_pipe( ialu_cr_reg_imm );
12051 %}
12052
12053 // Unsigned pointer compare Instructions
12054 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12055 match(Set cr (CmpP op1 op2));
12056
12057 format %{ "CMPu $op1,$op2" %}
12058 opcode(0x3B); /* Opcode 3B /r */
12059 ins_encode( OpcP, RegReg( op1, op2) );
12060 ins_pipe( ialu_cr_reg_reg );
12061 %}
12062
12063 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12064 match(Set cr (CmpP op1 op2));
12101 opcode(0x3B); /* Opcode 3B /r */
12102 ins_encode( OpcP, RegMem( op1, op2) );
12103 ins_pipe( ialu_cr_reg_mem );
12104 %}
12105
12106 //
12107 // This will generate a signed flags result. This should be ok
12108 // since any compare to a zero should be eq/neq.
12109 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12110 match(Set cr (CmpP src zero));
12111
12112 format %{ "TEST $src,$src" %}
12113 opcode(0x85);
12114 ins_encode( OpcP, RegReg( src, src ) );
12115 ins_pipe( ialu_cr_reg_imm );
12116 %}
12117
12118 // Cisc-spilled version of testP_reg
12119 // This will generate a signed flags result. This should be ok
12120 // since any compare to a zero should be eq/neq.
12121 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12122 match(Set cr (CmpP (LoadP op) zero));
12123
12124 format %{ "TEST $op,0xFFFFFFFF" %}
12125 ins_cost(500);
12126 opcode(0xF7); /* Opcode F7 /0 */
12127 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12128 ins_pipe( ialu_cr_reg_imm );
12129 %}
12130
12131 // Yanked all unsigned pointer compare operations.
12132 // Pointer compares are done with CmpP which is already unsigned.
12133
12134 //----------Max and Min--------------------------------------------------------
12135 // Min Instructions
12136 ////
12137 // *** Min and Max using the conditional move are slower than the
12138 // *** branch version on a Pentium III.
12139 // // Conditional move for min
12140 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12141 // effect( USE_DEF op2, USE op1, USE cr );
13472 //
13473 // Each peephole rule is given an identifying number starting with zero and
13474 // increasing by one in the order seen by the parser. An individual peephole
13475 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13476 // on the command-line.
13477 //
13478 // ---------CURRENT LIMITATIONS----------------------------------------------
13479 //
13480 // Only match adjacent instructions in same basic block
13481 // Only equality constraints
13482 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13483 // Only one replacement instruction
13484 //
13485 // ---------EXAMPLE----------------------------------------------------------
13486 //
13487 // // pertinent parts of existing instructions in architecture description
13488 // instruct movI(rRegI dst, rRegI src) %{
13489 // match(Set dst (CopyI src));
13490 // %}
13491 //
13492 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13493 // match(Set dst (AddI dst src));
13494 // effect(KILL cr);
13495 // %}
13496 //
13497 // // Change (inc mov) to lea
13498 // peephole %{
13499 // // increment preceeded by register-register move
13500 // peepmatch ( incI_eReg movI );
13501 // // require that the destination register of the increment
13502 // // match the destination register of the move
13503 // peepconstraint ( 0.dst == 1.dst );
13504 // // construct a replacement instruction that sets
13505 // // the destination to ( move's source register + one )
13506 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13507 // %}
13508 //
13509 // Implementation no longer uses movX instructions since
13510 // machine-independent system no longer uses CopyX nodes.
13511 //
13512 // peephole %{
|
3305 // necessarily the start) requires. If > 1, a compute_padding()
3306 // function must be provided for the instruction
3307
3308 //----------OPERANDS-----------------------------------------------------------
3309 // Operand definitions must precede instruction definitions for correct parsing
3310 // in the ADLC because operands constitute user defined types which are used in
3311 // instruction definitions.
3312
3313 //----------Simple Operands----------------------------------------------------
3314 // Immediate Operands
3315 // Integer Immediate
3316 operand immI() %{
3317 match(ConI);
3318
3319 op_cost(10);
3320 format %{ %}
3321 interface(CONST_INTER);
3322 %}
3323
3324 // Constant for test vs zero
3325 operand immI_0() %{
3326 predicate(n->get_int() == 0);
3327 match(ConI);
3328
3329 op_cost(0);
3330 format %{ %}
3331 interface(CONST_INTER);
3332 %}
3333
3334 // Constant for increment
3335 operand immI_1() %{
3336 predicate(n->get_int() == 1);
3337 match(ConI);
3338
3339 op_cost(0);
3340 format %{ %}
3341 interface(CONST_INTER);
3342 %}
3343
3344 // Constant for decrement
3345 operand immI_M1() %{
3346 predicate(n->get_int() == -1);
3347 match(ConI);
3348
3349 op_cost(0);
3350 format %{ %}
3351 interface(CONST_INTER);
3352 %}
3353
3354 // Valid scale values for addressing modes
3355 operand immI2() %{
3409 %}
3410
3411 operand immI_1_31() %{
3412 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3413 match(ConI);
3414
3415 op_cost(0);
3416 format %{ %}
3417 interface(CONST_INTER);
3418 %}
3419
3420 operand immI_32_63() %{
3421 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3422 match(ConI);
3423 op_cost(0);
3424
3425 format %{ %}
3426 interface(CONST_INTER);
3427 %}
3428
3429 operand immI_2() %{
3430 predicate( n->get_int() == 2 );
3431 match(ConI);
3432
3433 op_cost(0);
3434 format %{ %}
3435 interface(CONST_INTER);
3436 %}
3437
3438 operand immI_3() %{
3439 predicate( n->get_int() == 3 );
3440 match(ConI);
3441
3442 op_cost(0);
3443 format %{ %}
3444 interface(CONST_INTER);
3445 %}
3446
3447 operand immI_4()
3448 %{
3449 predicate(n->get_int() == 4);
3450 match(ConI);
3451
3452 op_cost(0);
3453 format %{ %}
3454 interface(CONST_INTER);
3455 %}
3456
3457 operand immI_8()
3458 %{
3459 predicate(n->get_int() == 8);
3460 match(ConI);
3461
3462 op_cost(0);
3463 format %{ %}
3464 interface(CONST_INTER);
3465 %}
3466
3467 // Pointer Immediate
3468 operand immP() %{
3469 match(ConP);
3470
3471 op_cost(10);
3472 format %{ %}
3473 interface(CONST_INTER);
3474 %}
3475
3476 // NULL Pointer Immediate
3477 operand immP0() %{
3478 predicate( n->get_ptr() == 0 );
3479 match(ConP);
3816 match(eCXRegP);
3817 match(eDIRegP);
3818 match(eRegP);
3819
3820 format %{ %}
3821 interface(REG_INTER);
3822 %}
3823
3824 operand eRegP() %{
3825 constraint(ALLOC_IN_RC(int_reg));
3826 match(RegP);
3827 match(eAXRegP);
3828 match(eBXRegP);
3829 match(eCXRegP);
3830 match(eDIRegP);
3831
3832 format %{ %}
3833 interface(REG_INTER);
3834 %}
3835
3836 operand rRegP() %{
3837 constraint(ALLOC_IN_RC(int_reg));
3838 match(RegP);
3839 match(eAXRegP);
3840 match(eBXRegP);
3841 match(eCXRegP);
3842 match(eDIRegP);
3843
3844 format %{ %}
3845 interface(REG_INTER);
3846 %}
3847
3848 // On windows95, EBP is not safe to use for implicit null tests.
3849 operand eRegP_no_EBP() %{
3850 constraint(ALLOC_IN_RC(int_reg_no_ebp));
3851 match(RegP);
3852 match(eAXRegP);
3853 match(eBXRegP);
3854 match(eCXRegP);
3855 match(eDIRegP);
3856
3857 op_cost(100);
3858 format %{ %}
3859 interface(REG_INTER);
3860 %}
3861
3862 operand naxRegP() %{
3863 constraint(ALLOC_IN_RC(nax_reg));
3864 match(RegP);
3865 match(eBXRegP);
3866 match(eDXRegP);
3867 match(eCXRegP);
3961 %}
3962
3963 operand eBCXRegL( eRegL reg ) %{
3964 constraint(ALLOC_IN_RC(ebcx_reg));
3965 match(reg);
3966
3967 format %{ "EBX:ECX" %}
3968 interface(REG_INTER);
3969 %}
3970
3971 // Special case for integer high multiply
3972 operand eADXRegL_low_only() %{
3973 constraint(ALLOC_IN_RC(eadx_reg));
3974 match(RegL);
3975
3976 format %{ "EAX" %}
3977 interface(REG_INTER);
3978 %}
3979
3980 // Flags register, used as output of compare instructions
3981 operand rFlagsReg() %{
3982 constraint(ALLOC_IN_RC(int_flags));
3983 match(RegFlags);
3984
3985 format %{ "EFLAGS" %}
3986 interface(REG_INTER);
3987 %}
3988
3989 // Flags register, used as output of compare instructions
3990 operand eFlagsReg() %{
3991 constraint(ALLOC_IN_RC(int_flags));
3992 match(RegFlags);
3993
3994 format %{ "EFLAGS" %}
3995 interface(REG_INTER);
3996 %}
3997
3998 // Flags register, used as output of FLOATING POINT compare instructions
3999 operand eFlagsRegU() %{
4000 constraint(ALLOC_IN_RC(int_flags));
4001 match(RegFlags);
4002
4003 format %{ "EFLAGS_U" %}
4004 interface(REG_INTER);
4005 %}
4006
4007 operand eFlagsRegUCF() %{
4008 constraint(ALLOC_IN_RC(int_flags));
4009 match(RegFlags);
4099 %}
4100
4101 // Float register operands
4102 operand regFPR1(regFPR reg) %{
4103 predicate( UseSSE < 2 );
4104 constraint(ALLOC_IN_RC(fp_flt_reg0));
4105 match(reg);
4106 format %{ "FPR1" %}
4107 interface(REG_INTER);
4108 %}
4109
4110 // XMM Float register operands
4111 operand regF() %{
4112 predicate( UseSSE>=1 );
4113 constraint(ALLOC_IN_RC(float_reg_legacy));
4114 match(RegF);
4115 format %{ %}
4116 interface(REG_INTER);
4117 %}
4118
4119 operand legRegF() %{
4120 predicate( UseSSE>=1 );
4121 constraint(ALLOC_IN_RC(float_reg_legacy));
4122 match(RegF);
4123 format %{ %}
4124 interface(REG_INTER);
4125 %}
4126
4127 // Float register operands
4128 operand vlRegF() %{
4129 constraint(ALLOC_IN_RC(float_reg_vl));
4130 match(RegF);
4131
4132 format %{ %}
4133 interface(REG_INTER);
4134 %}
4135
4136 // XMM Double register operands
4137 operand regD() %{
4138 predicate( UseSSE>=2 );
4139 constraint(ALLOC_IN_RC(double_reg_legacy));
4140 match(RegD);
4141 format %{ %}
4142 interface(REG_INTER);
4143 %}
4144
4145 // Double register operands
4146 operand legRegD() %{
4147 predicate( UseSSE>=2 );
4148 constraint(ALLOC_IN_RC(double_reg_legacy));
4149 match(RegD);
4150 format %{ %}
4151 interface(REG_INTER);
4152 %}
4153
4154 operand vlRegD() %{
4155 constraint(ALLOC_IN_RC(double_reg_vl));
4156 match(RegD);
4157
4158 format %{ %}
4159 interface(REG_INTER);
4160 %}
4161
4162 //----------Memory Operands----------------------------------------------------
4163 // Direct Memory Operand
4164 operand direct(immP addr) %{
4165 match(addr);
4166
4167 format %{ "[$addr]" %}
4168 interface(MEMORY_INTER) %{
4169 base(0xFFFFFFFF);
4170 index(0x4);
4171 scale(0x0);
4172 disp($addr);
4173 %}
5884 match(Set dst (LoadP mem));
5885
5886 ins_cost(125);
5887 format %{ "MOV $dst,$mem" %}
5888 opcode(0x8B);
5889 ins_encode( OpcP, RegMem(dst,mem));
5890 ins_pipe( ialu_reg_mem );
5891 %}
5892
5893 // Load Klass Pointer
5894 instruct loadKlass(eRegP dst, memory mem) %{
5895 match(Set dst (LoadKlass mem));
5896
5897 ins_cost(125);
5898 format %{ "MOV $dst,$mem" %}
5899 opcode(0x8B);
5900 ins_encode( OpcP, RegMem(dst,mem));
5901 ins_pipe( ialu_reg_mem );
5902 %}
5903
5904 // Load Float
5905 instruct MoveF2LEG(legRegF dst, regF src) %{
5906 match(Set dst src);
5907 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5908 ins_encode %{
5909 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5910 %}
5911 ins_pipe( fpu_reg_reg );
5912 %}
5913
5914 // Load Float
5915 instruct MoveLEG2F(regF dst, legRegF src) %{
5916 match(Set dst src);
5917 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5918 ins_encode %{
5919 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5920 %}
5921 ins_pipe( fpu_reg_reg );
5922 %}
5923
5924 // Load Double
5925 instruct MoveD2LEG(legRegD dst, regD src) %{
5926 match(Set dst src);
5927 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5928 ins_encode %{
5929 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5930 %}
5931 ins_pipe( fpu_reg_reg );
5932 %}
5933
5934 // Load Double
5935 instruct MoveLEG2D(regD dst, legRegD src) %{
5936 match(Set dst src);
5937 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5938 ins_encode %{
5939 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5940 %}
5941 ins_pipe( fpu_reg_reg );
5942 %}
5943
5944 // Load Double
5945 instruct loadDPR(regDPR dst, memory mem) %{
5946 predicate(UseSSE<=1);
5947 match(Set dst (LoadD mem));
5948
5949 ins_cost(150);
5950 format %{ "FLD_D ST,$mem\n\t"
5951 "FSTP $dst" %}
5952 opcode(0xDD); /* DD /0 */
5953 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5954 Pop_Reg_DPR(dst) );
5955 ins_pipe( fpu_reg_mem );
5956 %}
5957
5958 // Load Double to XMM
5959 instruct loadD(regD dst, memory mem) %{
5960 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
5961 match(Set dst (LoadD mem));
5962 ins_cost(145);
5963 format %{ "MOVSD $dst,$mem" %}
6049 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6050 match(Set dst mem);
6051
6052 ins_cost(110);
6053 format %{ "LEA $dst,$mem" %}
6054 opcode(0x8D);
6055 ins_encode( OpcP, RegMem(dst,mem));
6056 ins_pipe( ialu_reg_reg_fat );
6057 %}
6058
6059 // Load Constant
6060 instruct loadConI(rRegI dst, immI src) %{
6061 match(Set dst src);
6062
6063 format %{ "MOV $dst,$src" %}
6064 ins_encode( LdImmI(dst, src) );
6065 ins_pipe( ialu_reg_fat );
6066 %}
6067
6068 // Load Constant zero
6069 instruct loadConI0(rRegI dst, immI_0 src, eFlagsReg cr) %{
6070 match(Set dst src);
6071 effect(KILL cr);
6072
6073 ins_cost(50);
6074 format %{ "XOR $dst,$dst" %}
6075 opcode(0x33); /* + rd */
6076 ins_encode( OpcP, RegReg( dst, dst ) );
6077 ins_pipe( ialu_reg );
6078 %}
6079
6080 instruct loadConP(eRegP dst, immP src) %{
6081 match(Set dst src);
6082
6083 format %{ "MOV $dst,$src" %}
6084 opcode(0xB8); /* + rd */
6085 ins_encode( LdImmP(dst, src) );
6086 ins_pipe( ialu_reg_fat );
6087 %}
6088
6089 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7161 match(Set dst (AddI dst src));
7162 effect(KILL cr);
7163
7164 size(2);
7165 format %{ "ADD $dst,$src" %}
7166 opcode(0x03);
7167 ins_encode( OpcP, RegReg( dst, src) );
7168 ins_pipe( ialu_reg_reg );
7169 %}
7170
7171 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7172 match(Set dst (AddI dst src));
7173 effect(KILL cr);
7174
7175 format %{ "ADD $dst,$src" %}
7176 opcode(0x81, 0x00); /* /0 id */
7177 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7178 ins_pipe( ialu_reg );
7179 %}
7180
7181 instruct incI_eReg(rRegI dst, immI_1 src, eFlagsReg cr) %{
7182 predicate(UseIncDec);
7183 match(Set dst (AddI dst src));
7184 effect(KILL cr);
7185
7186 size(1);
7187 format %{ "INC $dst" %}
7188 opcode(0x40); /* */
7189 ins_encode( Opc_plus( primary, dst ) );
7190 ins_pipe( ialu_reg );
7191 %}
7192
7193 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7194 match(Set dst (AddI src0 src1));
7195 ins_cost(110);
7196
7197 format %{ "LEA $dst,[$src0 + $src1]" %}
7198 opcode(0x8D); /* 0x8D /r */
7199 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7200 ins_pipe( ialu_reg_reg );
7201 %}
7261
7262 ins_cost(150);
7263 format %{ "ADD $dst,$src" %}
7264 opcode(0x01); /* Opcode 01 /r */
7265 ins_encode( OpcP, RegMem( src, dst ) );
7266 ins_pipe( ialu_mem_reg );
7267 %}
7268
7269 // Add Memory with Immediate
7270 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7271 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7272 effect(KILL cr);
7273
7274 ins_cost(125);
7275 format %{ "ADD $dst,$src" %}
7276 opcode(0x81); /* Opcode 81 /0 id */
7277 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7278 ins_pipe( ialu_mem_imm );
7279 %}
7280
7281 instruct incI_mem(memory dst, immI_1 src, eFlagsReg cr) %{
7282 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7283 effect(KILL cr);
7284
7285 ins_cost(125);
7286 format %{ "INC $dst" %}
7287 opcode(0xFF); /* Opcode FF /0 */
7288 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7289 ins_pipe( ialu_mem_imm );
7290 %}
7291
7292 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7293 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7294 effect(KILL cr);
7295
7296 ins_cost(125);
7297 format %{ "DEC $dst" %}
7298 opcode(0xFF); /* Opcode FF /1 */
7299 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7300 ins_pipe( ialu_mem_imm );
7301 %}
7630
7631 ins_cost(125);
7632 format %{ "SUB $dst,$src" %}
7633 opcode(0x2B);
7634 ins_encode( OpcP, RegMem( dst, src) );
7635 ins_pipe( ialu_reg_mem );
7636 %}
7637
7638 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7639 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7640 effect(KILL cr);
7641
7642 ins_cost(150);
7643 format %{ "SUB $dst,$src" %}
7644 opcode(0x29); /* Opcode 29 /r */
7645 ins_encode( OpcP, RegMem( src, dst ) );
7646 ins_pipe( ialu_mem_reg );
7647 %}
7648
7649 // Subtract from a pointer
7650 instruct subP_eReg(eRegP dst, rRegI src, immI_0 zero, eFlagsReg cr) %{
7651 match(Set dst (AddP dst (SubI zero src)));
7652 effect(KILL cr);
7653
7654 size(2);
7655 format %{ "SUB $dst,$src" %}
7656 opcode(0x2B);
7657 ins_encode( OpcP, RegReg( dst, src) );
7658 ins_pipe( ialu_reg_reg );
7659 %}
7660
7661 instruct negI_eReg(rRegI dst, immI_0 zero, eFlagsReg cr) %{
7662 match(Set dst (SubI zero dst));
7663 effect(KILL cr);
7664
7665 size(2);
7666 format %{ "NEG $dst" %}
7667 opcode(0xF7,0x03); // Opcode F7 /3
7668 ins_encode( OpcP, RegOpc( dst ) );
7669 ins_pipe( ialu_reg );
7670 %}
7671
7672 //----------Multiplication/Division Instructions-------------------------------
7673 // Integer Multiplication Instructions
7674 // Multiply Register
7675 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7676 match(Set dst (MulI dst src));
7677 effect(KILL cr);
7678
7679 size(3);
7680 ins_cost(300);
7681 format %{ "IMUL $dst,$src" %}
8095 __ jmpb(Ldone);
8096
8097 __ bind(Lpos);
8098 __ divl($tmp$$Register);
8099 __ movl($dst$$Register, $tmp2$$Register);
8100
8101 __ bind(Lfast);
8102 // fast path: src is positive
8103 __ divl($tmp$$Register);
8104
8105 __ bind(Ldone);
8106 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8107 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8108
8109 %}
8110 ins_pipe( pipe_slow );
8111 %}
8112
8113 // Integer Shift Instructions
8114 // Shift Left by one
8115 instruct shlI_eReg_1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
8116 match(Set dst (LShiftI dst shift));
8117 effect(KILL cr);
8118
8119 size(2);
8120 format %{ "SHL $dst,$shift" %}
8121 opcode(0xD1, 0x4); /* D1 /4 */
8122 ins_encode( OpcP, RegOpc( dst ) );
8123 ins_pipe( ialu_reg );
8124 %}
8125
8126 // Shift Left by 8-bit immediate
8127 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8128 match(Set dst (LShiftI dst shift));
8129 effect(KILL cr);
8130
8131 size(3);
8132 format %{ "SHL $dst,$shift" %}
8133 opcode(0xC1, 0x4); /* C1 /4 ib */
8134 ins_encode( RegOpcImm( dst, shift) );
8135 ins_pipe( ialu_reg );
8136 %}
8137
8138 // Shift Left by variable
8139 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8140 match(Set dst (LShiftI dst shift));
8141 effect(KILL cr);
8142
8143 size(2);
8144 format %{ "SHL $dst,$shift" %}
8145 opcode(0xD3, 0x4); /* D3 /4 */
8146 ins_encode( OpcP, RegOpc( dst ) );
8147 ins_pipe( ialu_reg_reg );
8148 %}
8149
8150 // Arithmetic shift right by one
8151 instruct sarI_eReg_1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
8152 match(Set dst (RShiftI dst shift));
8153 effect(KILL cr);
8154
8155 size(2);
8156 format %{ "SAR $dst,$shift" %}
8157 opcode(0xD1, 0x7); /* D1 /7 */
8158 ins_encode( OpcP, RegOpc( dst ) );
8159 ins_pipe( ialu_reg );
8160 %}
8161
8162 // Arithmetic shift right by one
8163 instruct sarI_mem_1(memory dst, immI_1 shift, eFlagsReg cr) %{
8164 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8165 effect(KILL cr);
8166 format %{ "SAR $dst,$shift" %}
8167 opcode(0xD1, 0x7); /* D1 /7 */
8168 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8169 ins_pipe( ialu_mem_imm );
8170 %}
8171
8172 // Arithmetic Shift Right by 8-bit immediate
8173 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8174 match(Set dst (RShiftI dst shift));
8175 effect(KILL cr);
8176
8177 size(3);
8178 format %{ "SAR $dst,$shift" %}
8179 opcode(0xC1, 0x7); /* C1 /7 ib */
8180 ins_encode( RegOpcImm( dst, shift ) );
8181 ins_pipe( ialu_mem_imm );
8182 %}
8183
8188
8189 format %{ "SAR $dst,$shift" %}
8190 opcode(0xC1, 0x7); /* C1 /7 ib */
8191 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8192 ins_pipe( ialu_mem_imm );
8193 %}
8194
8195 // Arithmetic Shift Right by variable
8196 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8197 match(Set dst (RShiftI dst shift));
8198 effect(KILL cr);
8199
8200 size(2);
8201 format %{ "SAR $dst,$shift" %}
8202 opcode(0xD3, 0x7); /* D3 /7 */
8203 ins_encode( OpcP, RegOpc( dst ) );
8204 ins_pipe( ialu_reg_reg );
8205 %}
8206
8207 // Logical shift right by one
8208 instruct shrI_eReg_1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
8209 match(Set dst (URShiftI dst shift));
8210 effect(KILL cr);
8211
8212 size(2);
8213 format %{ "SHR $dst,$shift" %}
8214 opcode(0xD1, 0x5); /* D1 /5 */
8215 ins_encode( OpcP, RegOpc( dst ) );
8216 ins_pipe( ialu_reg );
8217 %}
8218
8219 // Logical Shift Right by 8-bit immediate
8220 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8221 match(Set dst (URShiftI dst shift));
8222 effect(KILL cr);
8223
8224 size(3);
8225 format %{ "SHR $dst,$shift" %}
8226 opcode(0xC1, 0x5); /* C1 /5 ib */
8227 ins_encode( RegOpcImm( dst, shift) );
8228 ins_pipe( ialu_reg );
8344 ins_encode %{
8345 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8346 %}
8347 ins_pipe(ialu_reg);
8348 %}
8349
8350 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
8351 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
8352 predicate(UseBMI1Instructions);
8353 effect(KILL cr);
8354
8355 ins_cost(125);
8356 format %{ "ANDNL $dst, $src1, $src2" %}
8357
8358 ins_encode %{
8359 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8360 %}
8361 ins_pipe(ialu_reg_mem);
8362 %}
8363
8364 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, eFlagsReg cr) %{
8365 match(Set dst (AndI (SubI imm_zero src) src));
8366 predicate(UseBMI1Instructions);
8367 effect(KILL cr);
8368
8369 format %{ "BLSIL $dst, $src" %}
8370
8371 ins_encode %{
8372 __ blsil($dst$$Register, $src$$Register);
8373 %}
8374 ins_pipe(ialu_reg);
8375 %}
8376
8377 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, eFlagsReg cr) %{
8378 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8379 predicate(UseBMI1Instructions);
8380 effect(KILL cr);
8381
8382 ins_cost(125);
8383 format %{ "BLSIL $dst, $src" %}
8384
8385 ins_encode %{
8386 __ blsil($dst$$Register, $src$$Address);
8387 %}
8388 ins_pipe(ialu_reg_mem);
8389 %}
8390
8391 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8392 %{
8393 match(Set dst (XorI (AddI src minus_1) src));
8394 predicate(UseBMI1Instructions);
8395 effect(KILL cr);
8396
8397 format %{ "BLSMSKL $dst, $src" %}
8509 opcode(0x09); /* Opcode 09 /r */
8510 ins_encode( OpcP, RegMem( src, dst ) );
8511 ins_pipe( ialu_mem_reg );
8512 %}
8513
8514 // Or Memory with Immediate
8515 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8516 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8517 effect(KILL cr);
8518
8519 ins_cost(125);
8520 format %{ "OR $dst,$src" %}
8521 opcode(0x81,0x1); /* Opcode 81 /1 id */
8522 // ins_encode( MemImm( dst, src) );
8523 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8524 ins_pipe( ialu_mem_imm );
8525 %}
8526
8527 // ROL/ROR
8528 // ROL expand
8529 instruct rolI_eReg_imm1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
8530 effect(USE_DEF dst, USE shift, KILL cr);
8531
8532 format %{ "ROL $dst, $shift" %}
8533 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8534 ins_encode( OpcP, RegOpc( dst ));
8535 ins_pipe( ialu_reg );
8536 %}
8537
8538 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8539 effect(USE_DEF dst, USE shift, KILL cr);
8540
8541 format %{ "ROL $dst, $shift" %}
8542 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8543 ins_encode( RegOpcImm(dst, shift) );
8544 ins_pipe(ialu_reg);
8545 %}
8546
8547 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8548 effect(USE_DEF dst, USE shift, KILL cr);
8549
8550 format %{ "ROL $dst, $shift" %}
8551 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8552 ins_encode(OpcP, RegOpc(dst));
8553 ins_pipe( ialu_reg_reg );
8554 %}
8555 // end of ROL expand
8556
8557 // ROL 32bit by one once
8558 instruct rolI_eReg_i1(rRegI dst, immI_1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8559 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8560
8561 expand %{
8562 rolI_eReg_imm1(dst, lshift, cr);
8563 %}
8564 %}
8565
8566 // ROL 32bit var by imm8 once
8567 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8568 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8569 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8570
8571 expand %{
8572 rolI_eReg_imm8(dst, lshift, cr);
8573 %}
8574 %}
8575
8576 // ROL 32bit var by var once
8577 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI_0 zero, eFlagsReg cr) %{
8578 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8579
8580 expand %{
8581 rolI_eReg_CL(dst, shift, cr);
8582 %}
8583 %}
8584
8585 // ROL 32bit var by var once
8586 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8587 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8588
8589 expand %{
8590 rolI_eReg_CL(dst, shift, cr);
8591 %}
8592 %}
8593
8594 // ROR expand
8595 instruct rorI_eReg_imm1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
8596 effect(USE_DEF dst, USE shift, KILL cr);
8597
8598 format %{ "ROR $dst, $shift" %}
8599 opcode(0xD1,0x1); /* Opcode D1 /1 */
8600 ins_encode( OpcP, RegOpc( dst ) );
8601 ins_pipe( ialu_reg );
8602 %}
8603
8604 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8605 effect (USE_DEF dst, USE shift, KILL cr);
8606
8607 format %{ "ROR $dst, $shift" %}
8608 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8609 ins_encode( RegOpcImm(dst, shift) );
8610 ins_pipe( ialu_reg );
8611 %}
8612
8613 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8614 effect(USE_DEF dst, USE shift, KILL cr);
8615
8616 format %{ "ROR $dst, $shift" %}
8617 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8618 ins_encode(OpcP, RegOpc(dst));
8619 ins_pipe( ialu_reg_reg );
8620 %}
8621 // end of ROR expand
8622
8623 // ROR right once
8624 instruct rorI_eReg_i1(rRegI dst, immI_1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8625 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8626
8627 expand %{
8628 rorI_eReg_imm1(dst, rshift, cr);
8629 %}
8630 %}
8631
8632 // ROR 32bit by immI8 once
8633 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8634 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8635 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8636
8637 expand %{
8638 rorI_eReg_imm8(dst, rshift, cr);
8639 %}
8640 %}
8641
8642 // ROR 32bit var by var once
8643 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI_0 zero, eFlagsReg cr) %{
8644 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8645
8646 expand %{
8647 rorI_eReg_CL(dst, shift, cr);
8648 %}
8649 %}
8650
8651 // ROR 32bit var by var once
8652 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8653 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8654
8655 expand %{
8656 rorI_eReg_CL(dst, shift, cr);
8657 %}
8658 %}
8659
8660 // Xor Instructions
8661 // Xor Register with Register
8662 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8663 match(Set dst (XorI dst src));
8791
8792 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8793 format %{ "XOR $dst,$dst\n\t"
8794 "CMP $p,$q\n\t"
8795 "SETlt $dst\n\t"
8796 "NEG $dst" %}
8797 ins_encode %{
8798 Register Rp = $p$$Register;
8799 Register Rq = $q$$Register;
8800 Register Rd = $dst$$Register;
8801 Label done;
8802 __ xorl(Rd, Rd);
8803 __ cmpl(Rp, Rq);
8804 __ setb(Assembler::less, Rd);
8805 __ negl(Rd);
8806 %}
8807
8808 ins_pipe(pipe_slow);
8809 %}
8810
8811 instruct cmpLTMask0(rRegI dst, immI_0 zero, eFlagsReg cr) %{
8812 match(Set dst (CmpLTMask dst zero));
8813 effect(DEF dst, KILL cr);
8814 ins_cost(100);
8815
8816 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8817 ins_encode %{
8818 __ sarl($dst$$Register, 31);
8819 %}
8820 ins_pipe(ialu_reg);
8821 %}
8822
8823 /* better to save a register than avoid a branch */
8824 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8825 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8826 effect(KILL cr);
8827 ins_cost(400);
8828 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8829 "JGE done\n\t"
8830 "ADD $p,$y\n"
8831 "done: " %}
8905 match(Set cr (OverflowSubI op1 op2));
8906
8907 format %{ "CMP $op1, $op2\t# overflow check int" %}
8908 ins_encode %{
8909 __ cmpl($op1$$Register, $op2$$Register);
8910 %}
8911 ins_pipe(ialu_reg_reg);
8912 %}
8913
8914 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2)
8915 %{
8916 match(Set cr (OverflowSubI op1 op2));
8917
8918 format %{ "CMP $op1, $op2\t# overflow check int" %}
8919 ins_encode %{
8920 __ cmpl($op1$$Register, $op2$$constant);
8921 %}
8922 ins_pipe(ialu_reg_reg);
8923 %}
8924
8925 instruct overflowNegI_rReg(eFlagsReg cr, immI_0 zero, eAXRegI op2)
8926 %{
8927 match(Set cr (OverflowSubI zero op2));
8928 effect(DEF cr, USE_KILL op2);
8929
8930 format %{ "NEG $op2\t# overflow check int" %}
8931 ins_encode %{
8932 __ negl($op2$$Register);
8933 %}
8934 ins_pipe(ialu_reg_reg);
8935 %}
8936
8937 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8938 %{
8939 match(Set cr (OverflowMulI op1 op2));
8940 effect(DEF cr, USE_KILL op1, USE op2);
8941
8942 format %{ "IMUL $op1, $op2\t# overflow check int" %}
8943 ins_encode %{
8944 __ imull($op1$$Register, $op2$$Register);
8945 %}
12043 match(Set cr (CmpI op1 op2));
12044 effect( DEF cr, USE op1 );
12045 format %{ "CMP $op1,$op2" %}
12046 opcode(0x81,0x07); /* Opcode 81 /7 */
12047 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12048 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12049 ins_pipe( ialu_cr_reg_imm );
12050 %}
12051
12052 // Cisc-spilled version of cmpI_eReg
12053 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
12054 match(Set cr (CmpI op1 (LoadI op2)));
12055
12056 format %{ "CMP $op1,$op2" %}
12057 ins_cost(500);
12058 opcode(0x3B); /* Opcode 3B /r */
12059 ins_encode( OpcP, RegMem( op1, op2) );
12060 ins_pipe( ialu_cr_reg_mem );
12061 %}
12062
12063 instruct testI_reg( eFlagsReg cr, rRegI src, immI_0 zero ) %{
12064 match(Set cr (CmpI src zero));
12065 effect( DEF cr, USE src );
12066
12067 format %{ "TEST $src,$src" %}
12068 opcode(0x85);
12069 ins_encode( OpcP, RegReg( src, src ) );
12070 ins_pipe( ialu_cr_reg_imm );
12071 %}
12072
12073 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI_0 zero ) %{
12074 match(Set cr (CmpI (AndI src con) zero));
12075
12076 format %{ "TEST $src,$con" %}
12077 opcode(0xF7,0x00);
12078 ins_encode( OpcP, RegOpc(src), Con32(con) );
12079 ins_pipe( ialu_cr_reg_imm );
12080 %}
12081
12082 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI_0 zero ) %{
12083 match(Set cr (CmpI (AndI src mem) zero));
12084
12085 format %{ "TEST $src,$mem" %}
12086 opcode(0x85);
12087 ins_encode( OpcP, RegMem( src, mem ) );
12088 ins_pipe( ialu_cr_reg_mem );
12089 %}
12090
12091 // Unsigned compare Instructions; really, same as signed except they
12092 // produce an eFlagsRegU instead of eFlagsReg.
12093 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
12094 match(Set cr (CmpU op1 op2));
12095
12096 format %{ "CMPu $op1,$op2" %}
12097 opcode(0x3B); /* Opcode 3B /r */
12098 ins_encode( OpcP, RegReg( op1, op2) );
12099 ins_pipe( ialu_cr_reg_reg );
12100 %}
12101
12102 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
12112 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
12113 match(Set cr (CmpU op1 (LoadI op2)));
12114
12115 format %{ "CMPu $op1,$op2" %}
12116 ins_cost(500);
12117 opcode(0x3B); /* Opcode 3B /r */
12118 ins_encode( OpcP, RegMem( op1, op2) );
12119 ins_pipe( ialu_cr_reg_mem );
12120 %}
12121
12122 // // Cisc-spilled version of cmpU_eReg
12123 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
12124 // match(Set cr (CmpU (LoadI op1) op2));
12125 //
12126 // format %{ "CMPu $op1,$op2" %}
12127 // ins_cost(500);
12128 // opcode(0x39); /* Opcode 39 /r */
12129 // ins_encode( OpcP, RegMem( op1, op2) );
12130 //%}
12131
12132 instruct testU_reg( eFlagsRegU cr, rRegI src, immI_0 zero ) %{
12133 match(Set cr (CmpU src zero));
12134
12135 format %{ "TESTu $src,$src" %}
12136 opcode(0x85);
12137 ins_encode( OpcP, RegReg( src, src ) );
12138 ins_pipe( ialu_cr_reg_imm );
12139 %}
12140
12141 // Unsigned pointer compare Instructions
12142 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12143 match(Set cr (CmpP op1 op2));
12144
12145 format %{ "CMPu $op1,$op2" %}
12146 opcode(0x3B); /* Opcode 3B /r */
12147 ins_encode( OpcP, RegReg( op1, op2) );
12148 ins_pipe( ialu_cr_reg_reg );
12149 %}
12150
12151 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12152 match(Set cr (CmpP op1 op2));
12189 opcode(0x3B); /* Opcode 3B /r */
12190 ins_encode( OpcP, RegMem( op1, op2) );
12191 ins_pipe( ialu_cr_reg_mem );
12192 %}
12193
12194 //
12195 // This will generate a signed flags result. This should be ok
12196 // since any compare to a zero should be eq/neq.
12197 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12198 match(Set cr (CmpP src zero));
12199
12200 format %{ "TEST $src,$src" %}
12201 opcode(0x85);
12202 ins_encode( OpcP, RegReg( src, src ) );
12203 ins_pipe( ialu_cr_reg_imm );
12204 %}
12205
12206 // Cisc-spilled version of testP_reg
12207 // This will generate a signed flags result. This should be ok
12208 // since any compare to a zero should be eq/neq.
12209 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI_0 zero ) %{
12210 match(Set cr (CmpP (LoadP op) zero));
12211
12212 format %{ "TEST $op,0xFFFFFFFF" %}
12213 ins_cost(500);
12214 opcode(0xF7); /* Opcode F7 /0 */
12215 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12216 ins_pipe( ialu_cr_reg_imm );
12217 %}
12218
12219 // Yanked all unsigned pointer compare operations.
12220 // Pointer compares are done with CmpP which is already unsigned.
12221
12222 //----------Max and Min--------------------------------------------------------
12223 // Min Instructions
12224 ////
12225 // *** Min and Max using the conditional move are slower than the
12226 // *** branch version on a Pentium III.
12227 // // Conditional move for min
12228 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12229 // effect( USE_DEF op2, USE op1, USE cr );
13560 //
13561 // Each peephole rule is given an identifying number starting with zero and
13562 // increasing by one in the order seen by the parser. An individual peephole
13563 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13564 // on the command-line.
13565 //
13566 // ---------CURRENT LIMITATIONS----------------------------------------------
13567 //
13568 // Only match adjacent instructions in same basic block
13569 // Only equality constraints
13570 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13571 // Only one replacement instruction
13572 //
13573 // ---------EXAMPLE----------------------------------------------------------
13574 //
13575 // // pertinent parts of existing instructions in architecture description
13576 // instruct movI(rRegI dst, rRegI src) %{
13577 // match(Set dst (CopyI src));
13578 // %}
13579 //
13580 // instruct incI_eReg(rRegI dst, immI_1 src, eFlagsReg cr) %{
13581 // match(Set dst (AddI dst src));
13582 // effect(KILL cr);
13583 // %}
13584 //
13585 // // Change (inc mov) to lea
13586 // peephole %{
13587 // // increment preceeded by register-register move
13588 // peepmatch ( incI_eReg movI );
13589 // // require that the destination register of the increment
13590 // // match the destination register of the move
13591 // peepconstraint ( 0.dst == 1.dst );
13592 // // construct a replacement instruction that sets
13593 // // the destination to ( move's source register + one )
13594 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13595 // %}
13596 //
13597 // Implementation no longer uses movX instructions since
13598 // machine-independent system no longer uses CopyX nodes.
13599 //
13600 // peephole %{
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