2858 // provided for the instruction
2859
2860 //----------OPERANDS-----------------------------------------------------------
2861 // Operand definitions must precede instruction definitions for correct parsing
2862 // in the ADLC because operands constitute user defined types which are used in
2863 // instruction definitions.
2864
2865 //----------Simple Operands----------------------------------------------------
2866 // Immediate Operands
2867 // Integer Immediate
2868 operand immI()
2869 %{
2870 match(ConI);
2871
2872 op_cost(10);
2873 format %{ %}
2874 interface(CONST_INTER);
2875 %}
2876
2877 // Constant for test vs zero
2878 operand immI0()
2879 %{
2880 predicate(n->get_int() == 0);
2881 match(ConI);
2882
2883 op_cost(0);
2884 format %{ %}
2885 interface(CONST_INTER);
2886 %}
2887
2888 // Constant for increment
2889 operand immI1()
2890 %{
2891 predicate(n->get_int() == 1);
2892 match(ConI);
2893
2894 op_cost(0);
2895 format %{ %}
2896 interface(CONST_INTER);
2897 %}
2898
2899 // Constant for decrement
2900 operand immI_M1()
2901 %{
2902 predicate(n->get_int() == -1);
2903 match(ConI);
2904
2905 op_cost(0);
2906 format %{ %}
2907 interface(CONST_INTER);
2908 %}
2909
2910 // Valid scale values for addressing modes
2911 operand immI2()
2912 %{
2913 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2914 match(ConI);
2915
2916 format %{ %}
2917 interface(CONST_INTER);
2918 %}
2919
2920 operand immI8()
2921 %{
2922 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2923 match(ConI);
2924
2925 op_cost(5);
2926 format %{ %}
2927 interface(CONST_INTER);
2928 %}
2929
5247 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5248 ins_encode %{
5249 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5250 %}
5251 ins_pipe( fpu_reg_reg );
5252 %}
5253
5254 // Following pseudo code describes the algorithm for max[FD]:
5255 // Min algorithm is on similar lines
5256 // btmp = (b < +0.0) ? a : b
5257 // atmp = (b < +0.0) ? b : a
5258 // Tmp = Max_Float(atmp , btmp)
5259 // Res = (atmp == NaN) ? atmp : Tmp
5260
5261 // max = java.lang.Math.max(float a, float b)
5262 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5263 predicate(UseAVX > 0 && !n->is_reduction());
5264 match(Set dst (MaxF a b));
5265 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5266 format %{
5267 "blendvps $btmp,$b,$a,$b \n\t"
5268 "blendvps $atmp,$a,$b,$b \n\t"
5269 "vmaxss $tmp,$atmp,$btmp \n\t"
5270 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5271 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5272 %}
5273 ins_encode %{
5274 int vector_len = Assembler::AVX_128bit;
5275 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5276 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5277 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5278 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5279 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5280 %}
5281 ins_pipe( pipe_slow );
5282 %}
5283
5284 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5285 predicate(UseAVX > 0 && n->is_reduction());
5286 match(Set dst (MaxF a b));
5287 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5288
5289 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5290 ins_encode %{
5291 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5292 false /*min*/, true /*single*/);
5293 %}
5294 ins_pipe( pipe_slow );
5295 %}
5296
5297 // max = java.lang.Math.max(double a, double b)
5298 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5299 predicate(UseAVX > 0 && !n->is_reduction());
5300 match(Set dst (MaxD a b));
5301 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5302 format %{
5303 "blendvpd $btmp,$b,$a,$b \n\t"
5304 "blendvpd $atmp,$a,$b,$b \n\t"
5305 "vmaxsd $tmp,$atmp,$btmp \n\t"
5306 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5307 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5308 %}
5309 ins_encode %{
5310 int vector_len = Assembler::AVX_128bit;
5311 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5312 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5313 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5314 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5315 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5316 %}
5317 ins_pipe( pipe_slow );
5318 %}
5319
5320 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5321 predicate(UseAVX > 0 && n->is_reduction());
5322 match(Set dst (MaxD a b));
5323 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5324
5325 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5326 ins_encode %{
5327 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5328 false /*min*/, false /*single*/);
5329 %}
5330 ins_pipe( pipe_slow );
5331 %}
5332
5333 // min = java.lang.Math.min(float a, float b)
5334 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5335 predicate(UseAVX > 0 && !n->is_reduction());
5336 match(Set dst (MinF a b));
5337 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5338 format %{
5339 "blendvps $atmp,$a,$b,$a \n\t"
5340 "blendvps $btmp,$b,$a,$a \n\t"
5341 "vminss $tmp,$atmp,$btmp \n\t"
5342 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5343 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5344 %}
5345 ins_encode %{
5346 int vector_len = Assembler::AVX_128bit;
5347 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5348 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5349 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5350 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5351 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5352 %}
5353 ins_pipe( pipe_slow );
5354 %}
5355
5356 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5357 predicate(UseAVX > 0 && n->is_reduction());
5358 match(Set dst (MinF a b));
5359 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5360
5361 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5362 ins_encode %{
5363 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5364 true /*min*/, true /*single*/);
5365 %}
5366 ins_pipe( pipe_slow );
5367 %}
5368
5369 // min = java.lang.Math.min(double a, double b)
5370 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5371 predicate(UseAVX > 0 && !n->is_reduction());
5372 match(Set dst (MinD a b));
5373 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5374 format %{
5375 "blendvpd $atmp,$a,$b,$a \n\t"
5376 "blendvpd $btmp,$b,$a,$a \n\t"
5377 "vminsd $tmp,$atmp,$btmp \n\t"
5378 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5379 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5380 %}
5381 ins_encode %{
5382 int vector_len = Assembler::AVX_128bit;
5383 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5384 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5385 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5386 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5387 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5388 %}
5389 ins_pipe( pipe_slow );
5390 %}
5391
5392 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5393 predicate(UseAVX > 0 && n->is_reduction());
5394 match(Set dst (MinD a b));
5395 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5396
5397 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5398 ins_encode %{
5399 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5400 true /*min*/, false /*single*/);
5401 %}
5402 ins_pipe( pipe_slow );
5403 %}
5404
5405 // Load Effective Address
5406 instruct leaP8(rRegP dst, indOffset8 mem)
5407 %{
5591 %{
5592 predicate(CompressedOops::shift() == 0);
5593 match(Set dst mem);
5594
5595 ins_cost(110);
5596 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5597 opcode(0x8D);
5598 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5599 ins_pipe(ialu_reg_reg_fat);
5600 %}
5601
5602 instruct loadConI(rRegI dst, immI src)
5603 %{
5604 match(Set dst src);
5605
5606 format %{ "movl $dst, $src\t# int" %}
5607 ins_encode(load_immI(dst, src));
5608 ins_pipe(ialu_reg_fat); // XXX
5609 %}
5610
5611 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5612 %{
5613 match(Set dst src);
5614 effect(KILL cr);
5615
5616 ins_cost(50);
5617 format %{ "xorl $dst, $dst\t# int" %}
5618 opcode(0x33); /* + rd */
5619 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5620 ins_pipe(ialu_reg);
5621 %}
5622
5623 instruct loadConL(rRegL dst, immL src)
5624 %{
5625 match(Set dst src);
5626
5627 ins_cost(150);
5628 format %{ "movq $dst, $src\t# long" %}
5629 ins_encode(load_immL(dst, src));
5630 ins_pipe(ialu_reg);
5631 %}
6027 } else {
6028 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6029 }
6030 %}
6031 ins_pipe(ialu_mem_imm);
6032 %}
6033
6034 instruct storeImmNKlass(memory mem, immNKlass src)
6035 %{
6036 match(Set mem (StoreNKlass mem src));
6037
6038 ins_cost(150); // XXX
6039 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6040 ins_encode %{
6041 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6042 %}
6043 ins_pipe(ialu_mem_imm);
6044 %}
6045
6046 // Store Integer Immediate
6047 instruct storeImmI0(memory mem, immI0 zero)
6048 %{
6049 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6050 match(Set mem (StoreI mem zero));
6051
6052 ins_cost(125); // XXX
6053 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6054 ins_encode %{
6055 __ movl($mem$$Address, r12);
6056 %}
6057 ins_pipe(ialu_mem_reg);
6058 %}
6059
6060 instruct storeImmI(memory mem, immI src)
6061 %{
6062 match(Set mem (StoreI mem src));
6063
6064 ins_cost(150);
6065 format %{ "movl $mem, $src\t# int" %}
6066 opcode(0xC7); /* C7 /0 */
6067 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6077 ins_cost(125); // XXX
6078 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6079 ins_encode %{
6080 __ movq($mem$$Address, r12);
6081 %}
6082 ins_pipe(ialu_mem_reg);
6083 %}
6084
6085 instruct storeImmL(memory mem, immL32 src)
6086 %{
6087 match(Set mem (StoreL mem src));
6088
6089 ins_cost(150);
6090 format %{ "movq $mem, $src\t# long" %}
6091 opcode(0xC7); /* C7 /0 */
6092 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6093 ins_pipe(ialu_mem_imm);
6094 %}
6095
6096 // Store Short/Char Immediate
6097 instruct storeImmC0(memory mem, immI0 zero)
6098 %{
6099 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6100 match(Set mem (StoreC mem zero));
6101
6102 ins_cost(125); // XXX
6103 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6104 ins_encode %{
6105 __ movw($mem$$Address, r12);
6106 %}
6107 ins_pipe(ialu_mem_reg);
6108 %}
6109
6110 instruct storeImmI16(memory mem, immI16 src)
6111 %{
6112 predicate(UseStoreImmI16);
6113 match(Set mem (StoreC mem src));
6114
6115 ins_cost(150);
6116 format %{ "movw $mem, $src\t# short/char" %}
6117 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6118 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6119 ins_pipe(ialu_mem_imm);
6120 %}
6121
6122 // Store Byte Immediate
6123 instruct storeImmB0(memory mem, immI0 zero)
6124 %{
6125 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6126 match(Set mem (StoreB mem zero));
6127
6128 ins_cost(125); // XXX
6129 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6130 ins_encode %{
6131 __ movb($mem$$Address, r12);
6132 %}
6133 ins_pipe(ialu_mem_reg);
6134 %}
6135
6136 instruct storeImmB(memory mem, immI8 src)
6137 %{
6138 match(Set mem (StoreB mem src));
6139
6140 ins_cost(150); // XXX
6141 format %{ "movb $mem, $src\t# byte" %}
6142 opcode(0xC6); /* C6 /0 */
6143 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6144 ins_pipe(ialu_mem_imm);
6145 %}
6146
6147 // Store CMS card-mark Immediate
6148 instruct storeImmCM0_reg(memory mem, immI0 zero)
6149 %{
6150 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6151 match(Set mem (StoreCM mem zero));
6152
6153 ins_cost(125); // XXX
6154 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6155 ins_encode %{
6156 __ movb($mem$$Address, r12);
6157 %}
6158 ins_pipe(ialu_mem_reg);
6159 %}
6160
6161 instruct storeImmCM0(memory mem, immI0 src)
6162 %{
6163 match(Set mem (StoreCM mem src));
6164
6165 ins_cost(150); // XXX
6166 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6167 opcode(0xC6); /* C6 /0 */
6168 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6169 ins_pipe(ialu_mem_imm);
6170 %}
6171
6172 // Store Float
6173 instruct storeF(memory mem, regF src)
6174 %{
6175 match(Set mem (StoreF mem src));
6176
6177 ins_cost(95); // XXX
6178 format %{ "movss $mem, $src\t# float" %}
6179 ins_encode %{
6180 __ movflt($mem$$Address, $src$$XMMRegister);
6181 %}
7226
7227 ins_cost(150); // XXX
7228 format %{ "addl $dst, $src\t# int" %}
7229 opcode(0x01); /* Opcode 01 /r */
7230 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7231 ins_pipe(ialu_mem_reg);
7232 %}
7233
7234 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7235 %{
7236 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7237 effect(KILL cr);
7238
7239 ins_cost(125); // XXX
7240 format %{ "addl $dst, $src\t# int" %}
7241 opcode(0x81); /* Opcode 81 /0 id */
7242 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7243 ins_pipe(ialu_mem_imm);
7244 %}
7245
7246 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7247 %{
7248 predicate(UseIncDec);
7249 match(Set dst (AddI dst src));
7250 effect(KILL cr);
7251
7252 format %{ "incl $dst\t# int" %}
7253 opcode(0xFF, 0x00); // FF /0
7254 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7255 ins_pipe(ialu_reg);
7256 %}
7257
7258 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7259 %{
7260 predicate(UseIncDec);
7261 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7262 effect(KILL cr);
7263
7264 ins_cost(125); // XXX
7265 format %{ "incl $dst\t# int" %}
7266 opcode(0xFF); /* Opcode FF /0 */
7267 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7268 ins_pipe(ialu_mem_imm);
7269 %}
7270
7271 // XXX why does that use AddI
7272 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7273 %{
7274 predicate(UseIncDec);
7275 match(Set dst (AddI dst src));
7276 effect(KILL cr);
7277
7278 format %{ "decl $dst\t# int" %}
8121 opcode(0x29); /* Opcode 29 /r */
8122 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8123 ins_pipe(ialu_mem_reg);
8124 %}
8125
8126 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8127 %{
8128 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8129 effect(KILL cr);
8130
8131 ins_cost(125); // XXX
8132 format %{ "subq $dst, $src\t# long" %}
8133 opcode(0x81); /* Opcode 81 /5 id */
8134 ins_encode(REX_mem_wide(dst),
8135 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8136 ins_pipe(ialu_mem_imm);
8137 %}
8138
8139 // Subtract from a pointer
8140 // XXX hmpf???
8141 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8142 %{
8143 match(Set dst (AddP dst (SubI zero src)));
8144 effect(KILL cr);
8145
8146 format %{ "subq $dst, $src\t# ptr - int" %}
8147 opcode(0x2B);
8148 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8149 ins_pipe(ialu_reg_reg);
8150 %}
8151
8152 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8153 %{
8154 match(Set dst (SubI zero dst));
8155 effect(KILL cr);
8156
8157 format %{ "negl $dst\t# int" %}
8158 opcode(0xF7, 0x03); // Opcode F7 /3
8159 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8160 ins_pipe(ialu_reg);
8161 %}
8162
8163 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8164 %{
8165 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8166 effect(KILL cr);
8167
8168 format %{ "negl $dst\t# int" %}
8169 opcode(0xF7, 0x03); // Opcode F7 /3
8170 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8171 ins_pipe(ialu_reg);
8172 %}
8173
8174 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8175 %{
8176 match(Set dst (SubL zero dst));
8177 effect(KILL cr);
8178
8179 format %{ "negq $dst\t# long" %}
8180 opcode(0xF7, 0x03); // Opcode F7 /3
8181 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8182 ins_pipe(ialu_reg);
8183 %}
8184
8185 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8186 %{
8187 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8188 effect(KILL cr);
8189
8190 format %{ "negq $dst\t# long" %}
8191 opcode(0xF7, 0x03); // Opcode F7 /3
8192 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8193 ins_pipe(ialu_reg);
8194 %}
8195
8196 //----------Multiplication/Division Instructions-------------------------------
8197 // Integer Multiplication Instructions
8198 // Multiply Register
8199
8200 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8201 %{
8202 match(Set dst (MulI dst src));
8203 effect(KILL cr);
8204
8490 match(Set rdx (ModL rax div));
8491 effect(KILL rax, KILL cr);
8492
8493 ins_cost(300); // XXX
8494 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8495 "cmpq rax, rdx\n\t"
8496 "jne,s normal\n\t"
8497 "xorl rdx, rdx\n\t"
8498 "cmpq $div, -1\n\t"
8499 "je,s done\n"
8500 "normal: cdqq\n\t"
8501 "idivq $div\n"
8502 "done:" %}
8503 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8504 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8505 ins_pipe(ialu_reg_reg_alu0);
8506 %}
8507
8508 // Integer Shift Instructions
8509 // Shift Left by one
8510 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8511 %{
8512 match(Set dst (LShiftI dst shift));
8513 effect(KILL cr);
8514
8515 format %{ "sall $dst, $shift" %}
8516 opcode(0xD1, 0x4); /* D1 /4 */
8517 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8518 ins_pipe(ialu_reg);
8519 %}
8520
8521 // Shift Left by one
8522 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8523 %{
8524 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8525 effect(KILL cr);
8526
8527 format %{ "sall $dst, $shift\t" %}
8528 opcode(0xD1, 0x4); /* D1 /4 */
8529 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8530 ins_pipe(ialu_mem_imm);
8531 %}
8532
8533 // Shift Left by 8-bit immediate
8534 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8535 %{
8536 match(Set dst (LShiftI dst shift));
8537 effect(KILL cr);
8538
8539 format %{ "sall $dst, $shift" %}
8540 opcode(0xC1, 0x4); /* C1 /4 ib */
8541 ins_encode(reg_opc_imm(dst, shift));
8542 ins_pipe(ialu_reg);
8562
8563 format %{ "sall $dst, $shift" %}
8564 opcode(0xD3, 0x4); /* D3 /4 */
8565 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8566 ins_pipe(ialu_reg_reg);
8567 %}
8568
8569 // Shift Left by variable
8570 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8571 %{
8572 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8573 effect(KILL cr);
8574
8575 format %{ "sall $dst, $shift" %}
8576 opcode(0xD3, 0x4); /* D3 /4 */
8577 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8578 ins_pipe(ialu_mem_reg);
8579 %}
8580
8581 // Arithmetic shift right by one
8582 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8583 %{
8584 match(Set dst (RShiftI dst shift));
8585 effect(KILL cr);
8586
8587 format %{ "sarl $dst, $shift" %}
8588 opcode(0xD1, 0x7); /* D1 /7 */
8589 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8590 ins_pipe(ialu_reg);
8591 %}
8592
8593 // Arithmetic shift right by one
8594 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8595 %{
8596 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8597 effect(KILL cr);
8598
8599 format %{ "sarl $dst, $shift" %}
8600 opcode(0xD1, 0x7); /* D1 /7 */
8601 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8602 ins_pipe(ialu_mem_imm);
8603 %}
8604
8605 // Arithmetic Shift Right by 8-bit immediate
8606 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8607 %{
8608 match(Set dst (RShiftI dst shift));
8609 effect(KILL cr);
8610
8611 format %{ "sarl $dst, $shift" %}
8612 opcode(0xC1, 0x7); /* C1 /7 ib */
8613 ins_encode(reg_opc_imm(dst, shift));
8614 ins_pipe(ialu_mem_imm);
8634
8635 format %{ "sarl $dst, $shift" %}
8636 opcode(0xD3, 0x7); /* D3 /7 */
8637 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8638 ins_pipe(ialu_reg_reg);
8639 %}
8640
8641 // Arithmetic Shift Right by variable
8642 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8643 %{
8644 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8645 effect(KILL cr);
8646
8647 format %{ "sarl $dst, $shift" %}
8648 opcode(0xD3, 0x7); /* D3 /7 */
8649 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8650 ins_pipe(ialu_mem_reg);
8651 %}
8652
8653 // Logical shift right by one
8654 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8655 %{
8656 match(Set dst (URShiftI dst shift));
8657 effect(KILL cr);
8658
8659 format %{ "shrl $dst, $shift" %}
8660 opcode(0xD1, 0x5); /* D1 /5 */
8661 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8662 ins_pipe(ialu_reg);
8663 %}
8664
8665 // Logical shift right by one
8666 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8667 %{
8668 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8669 effect(KILL cr);
8670
8671 format %{ "shrl $dst, $shift" %}
8672 opcode(0xD1, 0x5); /* D1 /5 */
8673 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8674 ins_pipe(ialu_mem_imm);
8675 %}
8676
8677 // Logical Shift Right by 8-bit immediate
8678 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8679 %{
8680 match(Set dst (URShiftI dst shift));
8681 effect(KILL cr);
8682
8683 format %{ "shrl $dst, $shift" %}
8684 opcode(0xC1, 0x5); /* C1 /5 ib */
8685 ins_encode(reg_opc_imm(dst, shift));
8686 ins_pipe(ialu_reg);
8707 format %{ "shrl $dst, $shift" %}
8708 opcode(0xD3, 0x5); /* D3 /5 */
8709 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8710 ins_pipe(ialu_reg_reg);
8711 %}
8712
8713 // Logical Shift Right by variable
8714 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8715 %{
8716 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8717 effect(KILL cr);
8718
8719 format %{ "shrl $dst, $shift" %}
8720 opcode(0xD3, 0x5); /* D3 /5 */
8721 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8722 ins_pipe(ialu_mem_reg);
8723 %}
8724
8725 // Long Shift Instructions
8726 // Shift Left by one
8727 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8728 %{
8729 match(Set dst (LShiftL dst shift));
8730 effect(KILL cr);
8731
8732 format %{ "salq $dst, $shift" %}
8733 opcode(0xD1, 0x4); /* D1 /4 */
8734 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8735 ins_pipe(ialu_reg);
8736 %}
8737
8738 // Shift Left by one
8739 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8740 %{
8741 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8742 effect(KILL cr);
8743
8744 format %{ "salq $dst, $shift" %}
8745 opcode(0xD1, 0x4); /* D1 /4 */
8746 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8747 ins_pipe(ialu_mem_imm);
8748 %}
8749
8750 // Shift Left by 8-bit immediate
8751 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8752 %{
8753 match(Set dst (LShiftL dst shift));
8754 effect(KILL cr);
8755
8756 format %{ "salq $dst, $shift" %}
8757 opcode(0xC1, 0x4); /* C1 /4 ib */
8758 ins_encode(reg_opc_imm_wide(dst, shift));
8759 ins_pipe(ialu_reg);
8780
8781 format %{ "salq $dst, $shift" %}
8782 opcode(0xD3, 0x4); /* D3 /4 */
8783 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8784 ins_pipe(ialu_reg_reg);
8785 %}
8786
8787 // Shift Left by variable
8788 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8789 %{
8790 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8791 effect(KILL cr);
8792
8793 format %{ "salq $dst, $shift" %}
8794 opcode(0xD3, 0x4); /* D3 /4 */
8795 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8796 ins_pipe(ialu_mem_reg);
8797 %}
8798
8799 // Arithmetic shift right by one
8800 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8801 %{
8802 match(Set dst (RShiftL dst shift));
8803 effect(KILL cr);
8804
8805 format %{ "sarq $dst, $shift" %}
8806 opcode(0xD1, 0x7); /* D1 /7 */
8807 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8808 ins_pipe(ialu_reg);
8809 %}
8810
8811 // Arithmetic shift right by one
8812 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8813 %{
8814 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8815 effect(KILL cr);
8816
8817 format %{ "sarq $dst, $shift" %}
8818 opcode(0xD1, 0x7); /* D1 /7 */
8819 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8820 ins_pipe(ialu_mem_imm);
8821 %}
8822
8823 // Arithmetic Shift Right by 8-bit immediate
8824 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8825 %{
8826 match(Set dst (RShiftL dst shift));
8827 effect(KILL cr);
8828
8829 format %{ "sarq $dst, $shift" %}
8830 opcode(0xC1, 0x7); /* C1 /7 ib */
8831 ins_encode(reg_opc_imm_wide(dst, shift));
8832 ins_pipe(ialu_mem_imm);
8853
8854 format %{ "sarq $dst, $shift" %}
8855 opcode(0xD3, 0x7); /* D3 /7 */
8856 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8857 ins_pipe(ialu_reg_reg);
8858 %}
8859
8860 // Arithmetic Shift Right by variable
8861 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8862 %{
8863 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8864 effect(KILL cr);
8865
8866 format %{ "sarq $dst, $shift" %}
8867 opcode(0xD3, 0x7); /* D3 /7 */
8868 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8869 ins_pipe(ialu_mem_reg);
8870 %}
8871
8872 // Logical shift right by one
8873 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8874 %{
8875 match(Set dst (URShiftL dst shift));
8876 effect(KILL cr);
8877
8878 format %{ "shrq $dst, $shift" %}
8879 opcode(0xD1, 0x5); /* D1 /5 */
8880 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8881 ins_pipe(ialu_reg);
8882 %}
8883
8884 // Logical shift right by one
8885 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8886 %{
8887 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8888 effect(KILL cr);
8889
8890 format %{ "shrq $dst, $shift" %}
8891 opcode(0xD1, 0x5); /* D1 /5 */
8892 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8893 ins_pipe(ialu_mem_imm);
8894 %}
8895
8896 // Logical Shift Right by 8-bit immediate
8897 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8898 %{
8899 match(Set dst (URShiftL dst shift));
8900 effect(KILL cr);
8901
8902 format %{ "shrq $dst, $shift" %}
8903 opcode(0xC1, 0x5); /* C1 /5 ib */
8904 ins_encode(reg_opc_imm_wide(dst, shift));
8905 ins_pipe(ialu_reg);
8983 effect(USE_DEF dst, USE shift, KILL cr);
8984
8985 format %{ "roll $dst, $shift" %}
8986 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8987 ins_encode( reg_opc_imm(dst, shift) );
8988 ins_pipe(ialu_reg);
8989 %}
8990
8991 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8992 %{
8993 effect(USE_DEF dst, USE shift, KILL cr);
8994
8995 format %{ "roll $dst, $shift" %}
8996 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8997 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8998 ins_pipe(ialu_reg_reg);
8999 %}
9000 // end of ROL expand
9001
9002 // Rotate Left by one
9003 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9004 %{
9005 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9006
9007 expand %{
9008 rolI_rReg_imm1(dst, cr);
9009 %}
9010 %}
9011
9012 // Rotate Left by 8-bit immediate
9013 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9014 %{
9015 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9016 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9017
9018 expand %{
9019 rolI_rReg_imm8(dst, lshift, cr);
9020 %}
9021 %}
9022
9023 // Rotate Left by variable
9024 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9025 %{
9026 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9027
9028 expand %{
9029 rolI_rReg_CL(dst, shift, cr);
9030 %}
9031 %}
9032
9033 // Rotate Left by variable
9034 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9035 %{
9036 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9037
9038 expand %{
9039 rolI_rReg_CL(dst, shift, cr);
9040 %}
9041 %}
9042
9043 // ROR expand
9044 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9056 effect(USE_DEF dst, USE shift, KILL cr);
9057
9058 format %{ "rorl $dst, $shift" %}
9059 opcode(0xC1, 0x1); /* C1 /1 ib */
9060 ins_encode(reg_opc_imm(dst, shift));
9061 ins_pipe(ialu_reg);
9062 %}
9063
9064 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9065 %{
9066 effect(USE_DEF dst, USE shift, KILL cr);
9067
9068 format %{ "rorl $dst, $shift" %}
9069 opcode(0xD3, 0x1); /* D3 /1 */
9070 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9071 ins_pipe(ialu_reg_reg);
9072 %}
9073 // end of ROR expand
9074
9075 // Rotate Right by one
9076 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9077 %{
9078 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9079
9080 expand %{
9081 rorI_rReg_imm1(dst, cr);
9082 %}
9083 %}
9084
9085 // Rotate Right by 8-bit immediate
9086 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9087 %{
9088 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9089 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9090
9091 expand %{
9092 rorI_rReg_imm8(dst, rshift, cr);
9093 %}
9094 %}
9095
9096 // Rotate Right by variable
9097 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9098 %{
9099 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9100
9101 expand %{
9102 rorI_rReg_CL(dst, shift, cr);
9103 %}
9104 %}
9105
9106 // Rotate Right by variable
9107 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9108 %{
9109 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9110
9111 expand %{
9112 rorI_rReg_CL(dst, shift, cr);
9113 %}
9114 %}
9115
9116 // for long rotate
9117 // ROL expand
9128 effect(USE_DEF dst, USE shift, KILL cr);
9129
9130 format %{ "rolq $dst, $shift" %}
9131 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9132 ins_encode( reg_opc_imm_wide(dst, shift) );
9133 ins_pipe(ialu_reg);
9134 %}
9135
9136 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9137 %{
9138 effect(USE_DEF dst, USE shift, KILL cr);
9139
9140 format %{ "rolq $dst, $shift" %}
9141 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9142 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9143 ins_pipe(ialu_reg_reg);
9144 %}
9145 // end of ROL expand
9146
9147 // Rotate Left by one
9148 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9149 %{
9150 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9151
9152 expand %{
9153 rolL_rReg_imm1(dst, cr);
9154 %}
9155 %}
9156
9157 // Rotate Left by 8-bit immediate
9158 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9159 %{
9160 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9161 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9162
9163 expand %{
9164 rolL_rReg_imm8(dst, lshift, cr);
9165 %}
9166 %}
9167
9168 // Rotate Left by variable
9169 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9170 %{
9171 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9172
9173 expand %{
9174 rolL_rReg_CL(dst, shift, cr);
9175 %}
9176 %}
9177
9178 // Rotate Left by variable
9179 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9180 %{
9181 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9182
9183 expand %{
9184 rolL_rReg_CL(dst, shift, cr);
9185 %}
9186 %}
9187
9188 // ROR expand
9189 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9201 effect(USE_DEF dst, USE shift, KILL cr);
9202
9203 format %{ "rorq $dst, $shift" %}
9204 opcode(0xC1, 0x1); /* C1 /1 ib */
9205 ins_encode(reg_opc_imm_wide(dst, shift));
9206 ins_pipe(ialu_reg);
9207 %}
9208
9209 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9210 %{
9211 effect(USE_DEF dst, USE shift, KILL cr);
9212
9213 format %{ "rorq $dst, $shift" %}
9214 opcode(0xD3, 0x1); /* D3 /1 */
9215 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9216 ins_pipe(ialu_reg_reg);
9217 %}
9218 // end of ROR expand
9219
9220 // Rotate Right by one
9221 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9222 %{
9223 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9224
9225 expand %{
9226 rorL_rReg_imm1(dst, cr);
9227 %}
9228 %}
9229
9230 // Rotate Right by 8-bit immediate
9231 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9232 %{
9233 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9234 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9235
9236 expand %{
9237 rorL_rReg_imm8(dst, rshift, cr);
9238 %}
9239 %}
9240
9241 // Rotate Right by variable
9242 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9243 %{
9244 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9245
9246 expand %{
9247 rorL_rReg_CL(dst, shift, cr);
9248 %}
9249 %}
9250
9251 // Rotate Right by variable
9252 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9253 %{
9254 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9255
9256 expand %{
9257 rorL_rReg_CL(dst, shift, cr);
9258 %}
9259 %}
9260
9261 // Logical Instructions
9262
9394
9395 ins_encode %{
9396 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9397 %}
9398 ins_pipe(ialu_reg_mem);
9399 %}
9400
9401 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9402 match(Set dst (AndI (XorI src1 minus_1) src2));
9403 predicate(UseBMI1Instructions);
9404 effect(KILL cr);
9405
9406 format %{ "andnl $dst, $src1, $src2" %}
9407
9408 ins_encode %{
9409 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9410 %}
9411 ins_pipe(ialu_reg);
9412 %}
9413
9414 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9415 match(Set dst (AndI (SubI imm_zero src) src));
9416 predicate(UseBMI1Instructions);
9417 effect(KILL cr);
9418
9419 format %{ "blsil $dst, $src" %}
9420
9421 ins_encode %{
9422 __ blsil($dst$$Register, $src$$Register);
9423 %}
9424 ins_pipe(ialu_reg);
9425 %}
9426
9427 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9428 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9429 predicate(UseBMI1Instructions);
9430 effect(KILL cr);
9431
9432 ins_cost(125);
9433 format %{ "blsil $dst, $src" %}
9434
9435 ins_encode %{
9436 __ blsil($dst$$Register, $src$$Address);
9437 %}
9438 ins_pipe(ialu_reg_mem);
9439 %}
9440
9441 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9442 %{
9443 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9444 predicate(UseBMI1Instructions);
9445 effect(KILL cr);
9446
9447 ins_cost(125);
10090 %}
10091
10092 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10093 %{
10094 match(Set dst (CmpLTMask p q));
10095 effect(KILL cr);
10096
10097 ins_cost(400);
10098 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10099 "setlt $dst\n\t"
10100 "movzbl $dst, $dst\n\t"
10101 "negl $dst" %}
10102 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10103 setLT_reg(dst),
10104 REX_reg_breg(dst, dst), // movzbl
10105 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10106 neg_reg(dst));
10107 ins_pipe(pipe_slow);
10108 %}
10109
10110 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10111 %{
10112 match(Set dst (CmpLTMask dst zero));
10113 effect(KILL cr);
10114
10115 ins_cost(100);
10116 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10117 ins_encode %{
10118 __ sarl($dst$$Register, 31);
10119 %}
10120 ins_pipe(ialu_reg);
10121 %}
10122
10123 /* Better to save a register than avoid a branch */
10124 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10125 %{
10126 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10127 effect(KILL cr);
10128 ins_cost(300);
10129 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10130 "jge done\n\t"
11423 match(Set cr (OverflowSubL op1 op2));
11424
11425 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11426 ins_encode %{
11427 __ cmpq($op1$$Register, $op2$$Register);
11428 %}
11429 ins_pipe(ialu_reg_reg);
11430 %}
11431
11432 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11433 %{
11434 match(Set cr (OverflowSubL op1 op2));
11435
11436 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11437 ins_encode %{
11438 __ cmpq($op1$$Register, $op2$$constant);
11439 %}
11440 ins_pipe(ialu_reg_reg);
11441 %}
11442
11443 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11444 %{
11445 match(Set cr (OverflowSubI zero op2));
11446 effect(DEF cr, USE_KILL op2);
11447
11448 format %{ "negl $op2\t# overflow check int" %}
11449 ins_encode %{
11450 __ negl($op2$$Register);
11451 %}
11452 ins_pipe(ialu_reg_reg);
11453 %}
11454
11455 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11456 %{
11457 match(Set cr (OverflowSubL zero op2));
11458 effect(DEF cr, USE_KILL op2);
11459
11460 format %{ "negq $op2\t# overflow check long" %}
11461 ins_encode %{
11462 __ negq($op2$$Register);
11463 %}
11532 %{
11533 match(Set cr (CmpI op1 op2));
11534
11535 format %{ "cmpl $op1, $op2" %}
11536 opcode(0x81, 0x07); /* Opcode 81 /7 */
11537 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11538 ins_pipe(ialu_cr_reg_imm);
11539 %}
11540
11541 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11542 %{
11543 match(Set cr (CmpI op1 (LoadI op2)));
11544
11545 ins_cost(500); // XXX
11546 format %{ "cmpl $op1, $op2" %}
11547 opcode(0x3B); /* Opcode 3B /r */
11548 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11549 ins_pipe(ialu_cr_reg_mem);
11550 %}
11551
11552 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11553 %{
11554 match(Set cr (CmpI src zero));
11555
11556 format %{ "testl $src, $src" %}
11557 opcode(0x85);
11558 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11559 ins_pipe(ialu_cr_reg_imm);
11560 %}
11561
11562 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11563 %{
11564 match(Set cr (CmpI (AndI src con) zero));
11565
11566 format %{ "testl $src, $con" %}
11567 opcode(0xF7, 0x00);
11568 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11569 ins_pipe(ialu_cr_reg_imm);
11570 %}
11571
11572 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11573 %{
11574 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11575
11576 format %{ "testl $src, $mem" %}
11577 opcode(0x85);
11578 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11579 ins_pipe(ialu_cr_reg_mem);
11580 %}
11581
11582 // Unsigned compare Instructions; really, same as signed except they
11583 // produce an rFlagsRegU instead of rFlagsReg.
11584 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11585 %{
11586 match(Set cr (CmpU op1 op2));
11587
11588 format %{ "cmpl $op1, $op2\t# unsigned" %}
11589 opcode(0x3B); /* Opcode 3B /r */
11590 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11591 ins_pipe(ialu_cr_reg_reg);
11592 %}
11606 match(Set cr (CmpU op1 (LoadI op2)));
11607
11608 ins_cost(500); // XXX
11609 format %{ "cmpl $op1, $op2\t# unsigned" %}
11610 opcode(0x3B); /* Opcode 3B /r */
11611 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11612 ins_pipe(ialu_cr_reg_mem);
11613 %}
11614
11615 // // // Cisc-spilled version of cmpU_rReg
11616 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11617 // //%{
11618 // // match(Set cr (CmpU (LoadI op1) op2));
11619 // //
11620 // // format %{ "CMPu $op1,$op2" %}
11621 // // ins_cost(500);
11622 // // opcode(0x39); /* Opcode 39 /r */
11623 // // ins_encode( OpcP, reg_mem( op1, op2) );
11624 // //%}
11625
11626 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11627 %{
11628 match(Set cr (CmpU src zero));
11629
11630 format %{ "testl $src, $src\t# unsigned" %}
11631 opcode(0x85);
11632 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11633 ins_pipe(ialu_cr_reg_imm);
11634 %}
11635
11636 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11637 %{
11638 match(Set cr (CmpP op1 op2));
11639
11640 format %{ "cmpq $op1, $op2\t# ptr" %}
11641 opcode(0x3B); /* Opcode 3B /r */
11642 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11643 ins_pipe(ialu_cr_reg_reg);
11644 %}
11645
11646 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11944 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11945 %{
11946 match(Set cr (CmpUL src zero));
11947
11948 format %{ "testq $src, $src\t# unsigned" %}
11949 opcode(0x85);
11950 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11951 ins_pipe(ialu_cr_reg_imm);
11952 %}
11953
11954 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
11955 %{
11956 match(Set cr (CmpI (LoadB mem) imm));
11957
11958 ins_cost(125);
11959 format %{ "cmpb $mem, $imm" %}
11960 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
11961 ins_pipe(ialu_cr_reg_mem);
11962 %}
11963
11964 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
11965 %{
11966 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
11967
11968 ins_cost(125);
11969 format %{ "testb $mem, $imm\t# ubyte" %}
11970 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11971 ins_pipe(ialu_cr_reg_mem);
11972 %}
11973
11974 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
11975 %{
11976 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
11977
11978 ins_cost(125);
11979 format %{ "testb $mem, $imm\t# byte" %}
11980 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11981 ins_pipe(ialu_cr_reg_mem);
11982 %}
11983
11984 //----------Max and Min--------------------------------------------------------
11985 // Min Instructions
11986
11987 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11988 %{
11989 effect(USE_DEF dst, USE src, USE cr);
11990
11991 format %{ "cmovlgt $dst, $src\t# min" %}
11992 opcode(0x0F, 0x4F);
11993 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11994 ins_pipe(pipe_cmov_reg);
12677 // Each peephole rule is given an identifying number starting with zero and
12678 // increasing by one in the order seen by the parser. An individual peephole
12679 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12680 // on the command-line.
12681 //
12682 // ---------CURRENT LIMITATIONS----------------------------------------------
12683 //
12684 // Only match adjacent instructions in same basic block
12685 // Only equality constraints
12686 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12687 // Only one replacement instruction
12688 //
12689 // ---------EXAMPLE----------------------------------------------------------
12690 //
12691 // // pertinent parts of existing instructions in architecture description
12692 // instruct movI(rRegI dst, rRegI src)
12693 // %{
12694 // match(Set dst (CopyI src));
12695 // %}
12696 //
12697 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12698 // %{
12699 // match(Set dst (AddI dst src));
12700 // effect(KILL cr);
12701 // %}
12702 //
12703 // // Change (inc mov) to lea
12704 // peephole %{
12705 // // increment preceeded by register-register move
12706 // peepmatch ( incI_rReg movI );
12707 // // require that the destination register of the increment
12708 // // match the destination register of the move
12709 // peepconstraint ( 0.dst == 1.dst );
12710 // // construct a replacement instruction that sets
12711 // // the destination to ( move's source register + one )
12712 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12713 // %}
12714 //
12715
12716 // Implementation no longer uses movX instructions since
12717 // machine-independent system no longer uses CopyX nodes.
|
2858 // provided for the instruction
2859
2860 //----------OPERANDS-----------------------------------------------------------
2861 // Operand definitions must precede instruction definitions for correct parsing
2862 // in the ADLC because operands constitute user defined types which are used in
2863 // instruction definitions.
2864
2865 //----------Simple Operands----------------------------------------------------
2866 // Immediate Operands
2867 // Integer Immediate
2868 operand immI()
2869 %{
2870 match(ConI);
2871
2872 op_cost(10);
2873 format %{ %}
2874 interface(CONST_INTER);
2875 %}
2876
2877 // Constant for test vs zero
2878 operand immI_0()
2879 %{
2880 predicate(n->get_int() == 0);
2881 match(ConI);
2882
2883 op_cost(0);
2884 format %{ %}
2885 interface(CONST_INTER);
2886 %}
2887
2888 // Constant for increment
2889 operand immI_1()
2890 %{
2891 predicate(n->get_int() == 1);
2892 match(ConI);
2893
2894 op_cost(0);
2895 format %{ %}
2896 interface(CONST_INTER);
2897 %}
2898
2899 // Constant for decrement
2900 operand immI_M1()
2901 %{
2902 predicate(n->get_int() == -1);
2903 match(ConI);
2904
2905 op_cost(0);
2906 format %{ %}
2907 interface(CONST_INTER);
2908 %}
2909
2910 operand immI_2()
2911 %{
2912 predicate(n->get_int() == 2);
2913 match(ConI);
2914
2915 op_cost(0);
2916 format %{ %}
2917 interface(CONST_INTER);
2918 %}
2919
2920 operand immI_4()
2921 %{
2922 predicate(n->get_int() == 4);
2923 match(ConI);
2924
2925 op_cost(0);
2926 format %{ %}
2927 interface(CONST_INTER);
2928 %}
2929
2930 operand immI_8()
2931 %{
2932 predicate(n->get_int() == 8);
2933 match(ConI);
2934
2935 op_cost(0);
2936 format %{ %}
2937 interface(CONST_INTER);
2938 %}
2939
2940 // Valid scale values for addressing modes
2941 operand immI2()
2942 %{
2943 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2944 match(ConI);
2945
2946 format %{ %}
2947 interface(CONST_INTER);
2948 %}
2949
2950 operand immI8()
2951 %{
2952 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2953 match(ConI);
2954
2955 op_cost(5);
2956 format %{ %}
2957 interface(CONST_INTER);
2958 %}
2959
5277 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5278 ins_encode %{
5279 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5280 %}
5281 ins_pipe( fpu_reg_reg );
5282 %}
5283
5284 // Following pseudo code describes the algorithm for max[FD]:
5285 // Min algorithm is on similar lines
5286 // btmp = (b < +0.0) ? a : b
5287 // atmp = (b < +0.0) ? b : a
5288 // Tmp = Max_Float(atmp , btmp)
5289 // Res = (atmp == NaN) ? atmp : Tmp
5290
5291 // max = java.lang.Math.max(float a, float b)
5292 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5293 predicate(UseAVX > 0 && !n->is_reduction());
5294 match(Set dst (MaxF a b));
5295 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5296 format %{
5297 "vblendvps $btmp,$b,$a,$b \n\t"
5298 "vblendvps $atmp,$a,$b,$b \n\t"
5299 "vmaxss $tmp,$atmp,$btmp \n\t"
5300 "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
5301 "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
5302 %}
5303 ins_encode %{
5304 int vector_len = Assembler::AVX_128bit;
5305 __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5306 __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5307 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5308 __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5309 __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5310 %}
5311 ins_pipe( pipe_slow );
5312 %}
5313
5314 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5315 predicate(UseAVX > 0 && n->is_reduction());
5316 match(Set dst (MaxF a b));
5317 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5318
5319 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5320 ins_encode %{
5321 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5322 false /*min*/, true /*single*/);
5323 %}
5324 ins_pipe( pipe_slow );
5325 %}
5326
5327 // max = java.lang.Math.max(double a, double b)
5328 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5329 predicate(UseAVX > 0 && !n->is_reduction());
5330 match(Set dst (MaxD a b));
5331 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5332 format %{
5333 "vblendvpd $btmp,$b,$a,$b \n\t"
5334 "vblendvpd $atmp,$a,$b,$b \n\t"
5335 "vmaxsd $tmp,$atmp,$btmp \n\t"
5336 "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
5337 "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
5338 %}
5339 ins_encode %{
5340 int vector_len = Assembler::AVX_128bit;
5341 __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5342 __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5343 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5344 __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5345 __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5346 %}
5347 ins_pipe( pipe_slow );
5348 %}
5349
5350 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5351 predicate(UseAVX > 0 && n->is_reduction());
5352 match(Set dst (MaxD a b));
5353 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5354
5355 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5356 ins_encode %{
5357 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5358 false /*min*/, false /*single*/);
5359 %}
5360 ins_pipe( pipe_slow );
5361 %}
5362
5363 // min = java.lang.Math.min(float a, float b)
5364 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5365 predicate(UseAVX > 0 && !n->is_reduction());
5366 match(Set dst (MinF a b));
5367 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5368 format %{
5369 "vblendvps $atmp,$a,$b,$a \n\t"
5370 "vblendvps $btmp,$b,$a,$a \n\t"
5371 "vminss $tmp,$atmp,$btmp \n\t"
5372 "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
5373 "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
5374 %}
5375 ins_encode %{
5376 int vector_len = Assembler::AVX_128bit;
5377 __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5378 __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5379 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5380 __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5381 __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5382 %}
5383 ins_pipe( pipe_slow );
5384 %}
5385
5386 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5387 predicate(UseAVX > 0 && n->is_reduction());
5388 match(Set dst (MinF a b));
5389 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5390
5391 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5392 ins_encode %{
5393 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5394 true /*min*/, true /*single*/);
5395 %}
5396 ins_pipe( pipe_slow );
5397 %}
5398
5399 // min = java.lang.Math.min(double a, double b)
5400 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5401 predicate(UseAVX > 0 && !n->is_reduction());
5402 match(Set dst (MinD a b));
5403 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5404 format %{
5405 "vblendvpd $atmp,$a,$b,$a \n\t"
5406 "vblendvpd $btmp,$b,$a,$a \n\t"
5407 "vminsd $tmp,$atmp,$btmp \n\t"
5408 "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
5409 "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
5410 %}
5411 ins_encode %{
5412 int vector_len = Assembler::AVX_128bit;
5413 __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5414 __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5415 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5416 __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5417 __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5418 %}
5419 ins_pipe( pipe_slow );
5420 %}
5421
5422 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5423 predicate(UseAVX > 0 && n->is_reduction());
5424 match(Set dst (MinD a b));
5425 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5426
5427 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5428 ins_encode %{
5429 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5430 true /*min*/, false /*single*/);
5431 %}
5432 ins_pipe( pipe_slow );
5433 %}
5434
5435 // Load Effective Address
5436 instruct leaP8(rRegP dst, indOffset8 mem)
5437 %{
5621 %{
5622 predicate(CompressedOops::shift() == 0);
5623 match(Set dst mem);
5624
5625 ins_cost(110);
5626 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5627 opcode(0x8D);
5628 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5629 ins_pipe(ialu_reg_reg_fat);
5630 %}
5631
5632 instruct loadConI(rRegI dst, immI src)
5633 %{
5634 match(Set dst src);
5635
5636 format %{ "movl $dst, $src\t# int" %}
5637 ins_encode(load_immI(dst, src));
5638 ins_pipe(ialu_reg_fat); // XXX
5639 %}
5640
5641 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
5642 %{
5643 match(Set dst src);
5644 effect(KILL cr);
5645
5646 ins_cost(50);
5647 format %{ "xorl $dst, $dst\t# int" %}
5648 opcode(0x33); /* + rd */
5649 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5650 ins_pipe(ialu_reg);
5651 %}
5652
5653 instruct loadConL(rRegL dst, immL src)
5654 %{
5655 match(Set dst src);
5656
5657 ins_cost(150);
5658 format %{ "movq $dst, $src\t# long" %}
5659 ins_encode(load_immL(dst, src));
5660 ins_pipe(ialu_reg);
5661 %}
6057 } else {
6058 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6059 }
6060 %}
6061 ins_pipe(ialu_mem_imm);
6062 %}
6063
6064 instruct storeImmNKlass(memory mem, immNKlass src)
6065 %{
6066 match(Set mem (StoreNKlass mem src));
6067
6068 ins_cost(150); // XXX
6069 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6070 ins_encode %{
6071 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6072 %}
6073 ins_pipe(ialu_mem_imm);
6074 %}
6075
6076 // Store Integer Immediate
6077 instruct storeImmI0(memory mem, immI_0 zero)
6078 %{
6079 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6080 match(Set mem (StoreI mem zero));
6081
6082 ins_cost(125); // XXX
6083 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6084 ins_encode %{
6085 __ movl($mem$$Address, r12);
6086 %}
6087 ins_pipe(ialu_mem_reg);
6088 %}
6089
6090 instruct storeImmI(memory mem, immI src)
6091 %{
6092 match(Set mem (StoreI mem src));
6093
6094 ins_cost(150);
6095 format %{ "movl $mem, $src\t# int" %}
6096 opcode(0xC7); /* C7 /0 */
6097 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6107 ins_cost(125); // XXX
6108 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6109 ins_encode %{
6110 __ movq($mem$$Address, r12);
6111 %}
6112 ins_pipe(ialu_mem_reg);
6113 %}
6114
6115 instruct storeImmL(memory mem, immL32 src)
6116 %{
6117 match(Set mem (StoreL mem src));
6118
6119 ins_cost(150);
6120 format %{ "movq $mem, $src\t# long" %}
6121 opcode(0xC7); /* C7 /0 */
6122 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6123 ins_pipe(ialu_mem_imm);
6124 %}
6125
6126 // Store Short/Char Immediate
6127 instruct storeImmC0(memory mem, immI_0 zero)
6128 %{
6129 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6130 match(Set mem (StoreC mem zero));
6131
6132 ins_cost(125); // XXX
6133 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6134 ins_encode %{
6135 __ movw($mem$$Address, r12);
6136 %}
6137 ins_pipe(ialu_mem_reg);
6138 %}
6139
6140 instruct storeImmI16(memory mem, immI16 src)
6141 %{
6142 predicate(UseStoreImmI16);
6143 match(Set mem (StoreC mem src));
6144
6145 ins_cost(150);
6146 format %{ "movw $mem, $src\t# short/char" %}
6147 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6148 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6149 ins_pipe(ialu_mem_imm);
6150 %}
6151
6152 // Store Byte Immediate
6153 instruct storeImmB0(memory mem, immI_0 zero)
6154 %{
6155 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6156 match(Set mem (StoreB mem zero));
6157
6158 ins_cost(125); // XXX
6159 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6160 ins_encode %{
6161 __ movb($mem$$Address, r12);
6162 %}
6163 ins_pipe(ialu_mem_reg);
6164 %}
6165
6166 instruct storeImmB(memory mem, immI8 src)
6167 %{
6168 match(Set mem (StoreB mem src));
6169
6170 ins_cost(150); // XXX
6171 format %{ "movb $mem, $src\t# byte" %}
6172 opcode(0xC6); /* C6 /0 */
6173 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6174 ins_pipe(ialu_mem_imm);
6175 %}
6176
6177 // Store CMS card-mark Immediate
6178 instruct storeImmCM0_reg(memory mem, immI_0 zero)
6179 %{
6180 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6181 match(Set mem (StoreCM mem zero));
6182
6183 ins_cost(125); // XXX
6184 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6185 ins_encode %{
6186 __ movb($mem$$Address, r12);
6187 %}
6188 ins_pipe(ialu_mem_reg);
6189 %}
6190
6191 instruct storeImmCM0(memory mem, immI_0 src)
6192 %{
6193 match(Set mem (StoreCM mem src));
6194
6195 ins_cost(150); // XXX
6196 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6197 opcode(0xC6); /* C6 /0 */
6198 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6199 ins_pipe(ialu_mem_imm);
6200 %}
6201
6202 // Store Float
6203 instruct storeF(memory mem, regF src)
6204 %{
6205 match(Set mem (StoreF mem src));
6206
6207 ins_cost(95); // XXX
6208 format %{ "movss $mem, $src\t# float" %}
6209 ins_encode %{
6210 __ movflt($mem$$Address, $src$$XMMRegister);
6211 %}
7256
7257 ins_cost(150); // XXX
7258 format %{ "addl $dst, $src\t# int" %}
7259 opcode(0x01); /* Opcode 01 /r */
7260 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7261 ins_pipe(ialu_mem_reg);
7262 %}
7263
7264 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7265 %{
7266 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7267 effect(KILL cr);
7268
7269 ins_cost(125); // XXX
7270 format %{ "addl $dst, $src\t# int" %}
7271 opcode(0x81); /* Opcode 81 /0 id */
7272 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7273 ins_pipe(ialu_mem_imm);
7274 %}
7275
7276 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
7277 %{
7278 predicate(UseIncDec);
7279 match(Set dst (AddI dst src));
7280 effect(KILL cr);
7281
7282 format %{ "incl $dst\t# int" %}
7283 opcode(0xFF, 0x00); // FF /0
7284 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7285 ins_pipe(ialu_reg);
7286 %}
7287
7288 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
7289 %{
7290 predicate(UseIncDec);
7291 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7292 effect(KILL cr);
7293
7294 ins_cost(125); // XXX
7295 format %{ "incl $dst\t# int" %}
7296 opcode(0xFF); /* Opcode FF /0 */
7297 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7298 ins_pipe(ialu_mem_imm);
7299 %}
7300
7301 // XXX why does that use AddI
7302 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7303 %{
7304 predicate(UseIncDec);
7305 match(Set dst (AddI dst src));
7306 effect(KILL cr);
7307
7308 format %{ "decl $dst\t# int" %}
8151 opcode(0x29); /* Opcode 29 /r */
8152 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8153 ins_pipe(ialu_mem_reg);
8154 %}
8155
8156 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8157 %{
8158 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8159 effect(KILL cr);
8160
8161 ins_cost(125); // XXX
8162 format %{ "subq $dst, $src\t# long" %}
8163 opcode(0x81); /* Opcode 81 /5 id */
8164 ins_encode(REX_mem_wide(dst),
8165 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8166 ins_pipe(ialu_mem_imm);
8167 %}
8168
8169 // Subtract from a pointer
8170 // XXX hmpf???
8171 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
8172 %{
8173 match(Set dst (AddP dst (SubI zero src)));
8174 effect(KILL cr);
8175
8176 format %{ "subq $dst, $src\t# ptr - int" %}
8177 opcode(0x2B);
8178 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8179 ins_pipe(ialu_reg_reg);
8180 %}
8181
8182 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
8183 %{
8184 match(Set dst (SubI zero dst));
8185 effect(KILL cr);
8186
8187 format %{ "negl $dst\t# int" %}
8188 opcode(0xF7, 0x03); // Opcode F7 /3
8189 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8190 ins_pipe(ialu_reg);
8191 %}
8192
8193 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
8194 %{
8195 match(Set dst (NegI dst));
8196 effect(KILL cr);
8197
8198 format %{ "negl $dst\t# int" %}
8199 ins_encode %{
8200 __ negl($dst$$Register);
8201 %}
8202 ins_pipe(ialu_reg);
8203 %}
8204
8205 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
8206 %{
8207 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8208 effect(KILL cr);
8209
8210 format %{ "negl $dst\t# int" %}
8211 opcode(0xF7, 0x03); // Opcode F7 /3
8212 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8213 ins_pipe(ialu_reg);
8214 %}
8215
8216 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8217 %{
8218 match(Set dst (SubL zero dst));
8219 effect(KILL cr);
8220
8221 format %{ "negq $dst\t# long" %}
8222 opcode(0xF7, 0x03); // Opcode F7 /3
8223 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8224 ins_pipe(ialu_reg);
8225 %}
8226
8227 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
8228 %{
8229 match(Set dst (NegL dst));
8230 effect(KILL cr);
8231
8232 format %{ "negq $dst\t# int" %}
8233 ins_encode %{
8234 __ negq($dst$$Register);
8235 %}
8236 ins_pipe(ialu_reg);
8237 %}
8238
8239 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8240 %{
8241 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8242 effect(KILL cr);
8243
8244 format %{ "negq $dst\t# long" %}
8245 opcode(0xF7, 0x03); // Opcode F7 /3
8246 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8247 ins_pipe(ialu_reg);
8248 %}
8249
8250 //----------Multiplication/Division Instructions-------------------------------
8251 // Integer Multiplication Instructions
8252 // Multiply Register
8253
8254 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8255 %{
8256 match(Set dst (MulI dst src));
8257 effect(KILL cr);
8258
8544 match(Set rdx (ModL rax div));
8545 effect(KILL rax, KILL cr);
8546
8547 ins_cost(300); // XXX
8548 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8549 "cmpq rax, rdx\n\t"
8550 "jne,s normal\n\t"
8551 "xorl rdx, rdx\n\t"
8552 "cmpq $div, -1\n\t"
8553 "je,s done\n"
8554 "normal: cdqq\n\t"
8555 "idivq $div\n"
8556 "done:" %}
8557 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8558 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8559 ins_pipe(ialu_reg_reg_alu0);
8560 %}
8561
8562 // Integer Shift Instructions
8563 // Shift Left by one
8564 instruct salI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8565 %{
8566 match(Set dst (LShiftI dst shift));
8567 effect(KILL cr);
8568
8569 format %{ "sall $dst, $shift" %}
8570 opcode(0xD1, 0x4); /* D1 /4 */
8571 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8572 ins_pipe(ialu_reg);
8573 %}
8574
8575 // Shift Left by one
8576 instruct salI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8577 %{
8578 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8579 effect(KILL cr);
8580
8581 format %{ "sall $dst, $shift\t" %}
8582 opcode(0xD1, 0x4); /* D1 /4 */
8583 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8584 ins_pipe(ialu_mem_imm);
8585 %}
8586
8587 // Shift Left by 8-bit immediate
8588 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8589 %{
8590 match(Set dst (LShiftI dst shift));
8591 effect(KILL cr);
8592
8593 format %{ "sall $dst, $shift" %}
8594 opcode(0xC1, 0x4); /* C1 /4 ib */
8595 ins_encode(reg_opc_imm(dst, shift));
8596 ins_pipe(ialu_reg);
8616
8617 format %{ "sall $dst, $shift" %}
8618 opcode(0xD3, 0x4); /* D3 /4 */
8619 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8620 ins_pipe(ialu_reg_reg);
8621 %}
8622
8623 // Shift Left by variable
8624 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8625 %{
8626 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8627 effect(KILL cr);
8628
8629 format %{ "sall $dst, $shift" %}
8630 opcode(0xD3, 0x4); /* D3 /4 */
8631 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8632 ins_pipe(ialu_mem_reg);
8633 %}
8634
8635 // Arithmetic shift right by one
8636 instruct sarI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8637 %{
8638 match(Set dst (RShiftI dst shift));
8639 effect(KILL cr);
8640
8641 format %{ "sarl $dst, $shift" %}
8642 opcode(0xD1, 0x7); /* D1 /7 */
8643 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8644 ins_pipe(ialu_reg);
8645 %}
8646
8647 // Arithmetic shift right by one
8648 instruct sarI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8649 %{
8650 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8651 effect(KILL cr);
8652
8653 format %{ "sarl $dst, $shift" %}
8654 opcode(0xD1, 0x7); /* D1 /7 */
8655 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8656 ins_pipe(ialu_mem_imm);
8657 %}
8658
8659 // Arithmetic Shift Right by 8-bit immediate
8660 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8661 %{
8662 match(Set dst (RShiftI dst shift));
8663 effect(KILL cr);
8664
8665 format %{ "sarl $dst, $shift" %}
8666 opcode(0xC1, 0x7); /* C1 /7 ib */
8667 ins_encode(reg_opc_imm(dst, shift));
8668 ins_pipe(ialu_mem_imm);
8688
8689 format %{ "sarl $dst, $shift" %}
8690 opcode(0xD3, 0x7); /* D3 /7 */
8691 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8692 ins_pipe(ialu_reg_reg);
8693 %}
8694
8695 // Arithmetic Shift Right by variable
8696 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8697 %{
8698 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8699 effect(KILL cr);
8700
8701 format %{ "sarl $dst, $shift" %}
8702 opcode(0xD3, 0x7); /* D3 /7 */
8703 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8704 ins_pipe(ialu_mem_reg);
8705 %}
8706
8707 // Logical shift right by one
8708 instruct shrI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8709 %{
8710 match(Set dst (URShiftI dst shift));
8711 effect(KILL cr);
8712
8713 format %{ "shrl $dst, $shift" %}
8714 opcode(0xD1, 0x5); /* D1 /5 */
8715 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8716 ins_pipe(ialu_reg);
8717 %}
8718
8719 // Logical shift right by one
8720 instruct shrI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8721 %{
8722 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8723 effect(KILL cr);
8724
8725 format %{ "shrl $dst, $shift" %}
8726 opcode(0xD1, 0x5); /* D1 /5 */
8727 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8728 ins_pipe(ialu_mem_imm);
8729 %}
8730
8731 // Logical Shift Right by 8-bit immediate
8732 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8733 %{
8734 match(Set dst (URShiftI dst shift));
8735 effect(KILL cr);
8736
8737 format %{ "shrl $dst, $shift" %}
8738 opcode(0xC1, 0x5); /* C1 /5 ib */
8739 ins_encode(reg_opc_imm(dst, shift));
8740 ins_pipe(ialu_reg);
8761 format %{ "shrl $dst, $shift" %}
8762 opcode(0xD3, 0x5); /* D3 /5 */
8763 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8764 ins_pipe(ialu_reg_reg);
8765 %}
8766
8767 // Logical Shift Right by variable
8768 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8769 %{
8770 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8771 effect(KILL cr);
8772
8773 format %{ "shrl $dst, $shift" %}
8774 opcode(0xD3, 0x5); /* D3 /5 */
8775 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8776 ins_pipe(ialu_mem_reg);
8777 %}
8778
8779 // Long Shift Instructions
8780 // Shift Left by one
8781 instruct salL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8782 %{
8783 match(Set dst (LShiftL dst shift));
8784 effect(KILL cr);
8785
8786 format %{ "salq $dst, $shift" %}
8787 opcode(0xD1, 0x4); /* D1 /4 */
8788 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8789 ins_pipe(ialu_reg);
8790 %}
8791
8792 // Shift Left by one
8793 instruct salL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8794 %{
8795 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8796 effect(KILL cr);
8797
8798 format %{ "salq $dst, $shift" %}
8799 opcode(0xD1, 0x4); /* D1 /4 */
8800 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8801 ins_pipe(ialu_mem_imm);
8802 %}
8803
8804 // Shift Left by 8-bit immediate
8805 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8806 %{
8807 match(Set dst (LShiftL dst shift));
8808 effect(KILL cr);
8809
8810 format %{ "salq $dst, $shift" %}
8811 opcode(0xC1, 0x4); /* C1 /4 ib */
8812 ins_encode(reg_opc_imm_wide(dst, shift));
8813 ins_pipe(ialu_reg);
8834
8835 format %{ "salq $dst, $shift" %}
8836 opcode(0xD3, 0x4); /* D3 /4 */
8837 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8838 ins_pipe(ialu_reg_reg);
8839 %}
8840
8841 // Shift Left by variable
8842 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8843 %{
8844 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8845 effect(KILL cr);
8846
8847 format %{ "salq $dst, $shift" %}
8848 opcode(0xD3, 0x4); /* D3 /4 */
8849 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8850 ins_pipe(ialu_mem_reg);
8851 %}
8852
8853 // Arithmetic shift right by one
8854 instruct sarL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8855 %{
8856 match(Set dst (RShiftL dst shift));
8857 effect(KILL cr);
8858
8859 format %{ "sarq $dst, $shift" %}
8860 opcode(0xD1, 0x7); /* D1 /7 */
8861 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8862 ins_pipe(ialu_reg);
8863 %}
8864
8865 // Arithmetic shift right by one
8866 instruct sarL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8867 %{
8868 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8869 effect(KILL cr);
8870
8871 format %{ "sarq $dst, $shift" %}
8872 opcode(0xD1, 0x7); /* D1 /7 */
8873 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8874 ins_pipe(ialu_mem_imm);
8875 %}
8876
8877 // Arithmetic Shift Right by 8-bit immediate
8878 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8879 %{
8880 match(Set dst (RShiftL dst shift));
8881 effect(KILL cr);
8882
8883 format %{ "sarq $dst, $shift" %}
8884 opcode(0xC1, 0x7); /* C1 /7 ib */
8885 ins_encode(reg_opc_imm_wide(dst, shift));
8886 ins_pipe(ialu_mem_imm);
8907
8908 format %{ "sarq $dst, $shift" %}
8909 opcode(0xD3, 0x7); /* D3 /7 */
8910 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8911 ins_pipe(ialu_reg_reg);
8912 %}
8913
8914 // Arithmetic Shift Right by variable
8915 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8916 %{
8917 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8918 effect(KILL cr);
8919
8920 format %{ "sarq $dst, $shift" %}
8921 opcode(0xD3, 0x7); /* D3 /7 */
8922 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8923 ins_pipe(ialu_mem_reg);
8924 %}
8925
8926 // Logical shift right by one
8927 instruct shrL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8928 %{
8929 match(Set dst (URShiftL dst shift));
8930 effect(KILL cr);
8931
8932 format %{ "shrq $dst, $shift" %}
8933 opcode(0xD1, 0x5); /* D1 /5 */
8934 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8935 ins_pipe(ialu_reg);
8936 %}
8937
8938 // Logical shift right by one
8939 instruct shrL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8940 %{
8941 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8942 effect(KILL cr);
8943
8944 format %{ "shrq $dst, $shift" %}
8945 opcode(0xD1, 0x5); /* D1 /5 */
8946 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8947 ins_pipe(ialu_mem_imm);
8948 %}
8949
8950 // Logical Shift Right by 8-bit immediate
8951 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8952 %{
8953 match(Set dst (URShiftL dst shift));
8954 effect(KILL cr);
8955
8956 format %{ "shrq $dst, $shift" %}
8957 opcode(0xC1, 0x5); /* C1 /5 ib */
8958 ins_encode(reg_opc_imm_wide(dst, shift));
8959 ins_pipe(ialu_reg);
9037 effect(USE_DEF dst, USE shift, KILL cr);
9038
9039 format %{ "roll $dst, $shift" %}
9040 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9041 ins_encode( reg_opc_imm(dst, shift) );
9042 ins_pipe(ialu_reg);
9043 %}
9044
9045 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9046 %{
9047 effect(USE_DEF dst, USE shift, KILL cr);
9048
9049 format %{ "roll $dst, $shift" %}
9050 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9051 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9052 ins_pipe(ialu_reg_reg);
9053 %}
9054 // end of ROL expand
9055
9056 // Rotate Left by one
9057 instruct rolI_rReg_i1(rRegI dst, immI_1 lshift, immI_M1 rshift, rFlagsReg cr)
9058 %{
9059 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9060
9061 expand %{
9062 rolI_rReg_imm1(dst, cr);
9063 %}
9064 %}
9065
9066 // Rotate Left by 8-bit immediate
9067 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9068 %{
9069 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9070 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9071
9072 expand %{
9073 rolI_rReg_imm8(dst, lshift, cr);
9074 %}
9075 %}
9076
9077 // Rotate Left by variable
9078 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9079 %{
9080 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9081
9082 expand %{
9083 rolI_rReg_CL(dst, shift, cr);
9084 %}
9085 %}
9086
9087 // Rotate Left by variable
9088 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9089 %{
9090 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9091
9092 expand %{
9093 rolI_rReg_CL(dst, shift, cr);
9094 %}
9095 %}
9096
9097 // ROR expand
9098 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9110 effect(USE_DEF dst, USE shift, KILL cr);
9111
9112 format %{ "rorl $dst, $shift" %}
9113 opcode(0xC1, 0x1); /* C1 /1 ib */
9114 ins_encode(reg_opc_imm(dst, shift));
9115 ins_pipe(ialu_reg);
9116 %}
9117
9118 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9119 %{
9120 effect(USE_DEF dst, USE shift, KILL cr);
9121
9122 format %{ "rorl $dst, $shift" %}
9123 opcode(0xD3, 0x1); /* D3 /1 */
9124 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9125 ins_pipe(ialu_reg_reg);
9126 %}
9127 // end of ROR expand
9128
9129 // Rotate Right by one
9130 instruct rorI_rReg_i1(rRegI dst, immI_1 rshift, immI_M1 lshift, rFlagsReg cr)
9131 %{
9132 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9133
9134 expand %{
9135 rorI_rReg_imm1(dst, cr);
9136 %}
9137 %}
9138
9139 // Rotate Right by 8-bit immediate
9140 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9141 %{
9142 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9143 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9144
9145 expand %{
9146 rorI_rReg_imm8(dst, rshift, cr);
9147 %}
9148 %}
9149
9150 // Rotate Right by variable
9151 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9152 %{
9153 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9154
9155 expand %{
9156 rorI_rReg_CL(dst, shift, cr);
9157 %}
9158 %}
9159
9160 // Rotate Right by variable
9161 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9162 %{
9163 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9164
9165 expand %{
9166 rorI_rReg_CL(dst, shift, cr);
9167 %}
9168 %}
9169
9170 // for long rotate
9171 // ROL expand
9182 effect(USE_DEF dst, USE shift, KILL cr);
9183
9184 format %{ "rolq $dst, $shift" %}
9185 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9186 ins_encode( reg_opc_imm_wide(dst, shift) );
9187 ins_pipe(ialu_reg);
9188 %}
9189
9190 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9191 %{
9192 effect(USE_DEF dst, USE shift, KILL cr);
9193
9194 format %{ "rolq $dst, $shift" %}
9195 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9196 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9197 ins_pipe(ialu_reg_reg);
9198 %}
9199 // end of ROL expand
9200
9201 // Rotate Left by one
9202 instruct rolL_rReg_i1(rRegL dst, immI_1 lshift, immI_M1 rshift, rFlagsReg cr)
9203 %{
9204 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9205
9206 expand %{
9207 rolL_rReg_imm1(dst, cr);
9208 %}
9209 %}
9210
9211 // Rotate Left by 8-bit immediate
9212 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9213 %{
9214 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9215 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9216
9217 expand %{
9218 rolL_rReg_imm8(dst, lshift, cr);
9219 %}
9220 %}
9221
9222 // Rotate Left by variable
9223 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9224 %{
9225 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9226
9227 expand %{
9228 rolL_rReg_CL(dst, shift, cr);
9229 %}
9230 %}
9231
9232 // Rotate Left by variable
9233 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9234 %{
9235 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9236
9237 expand %{
9238 rolL_rReg_CL(dst, shift, cr);
9239 %}
9240 %}
9241
9242 // ROR expand
9243 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9255 effect(USE_DEF dst, USE shift, KILL cr);
9256
9257 format %{ "rorq $dst, $shift" %}
9258 opcode(0xC1, 0x1); /* C1 /1 ib */
9259 ins_encode(reg_opc_imm_wide(dst, shift));
9260 ins_pipe(ialu_reg);
9261 %}
9262
9263 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9264 %{
9265 effect(USE_DEF dst, USE shift, KILL cr);
9266
9267 format %{ "rorq $dst, $shift" %}
9268 opcode(0xD3, 0x1); /* D3 /1 */
9269 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9270 ins_pipe(ialu_reg_reg);
9271 %}
9272 // end of ROR expand
9273
9274 // Rotate Right by one
9275 instruct rorL_rReg_i1(rRegL dst, immI_1 rshift, immI_M1 lshift, rFlagsReg cr)
9276 %{
9277 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9278
9279 expand %{
9280 rorL_rReg_imm1(dst, cr);
9281 %}
9282 %}
9283
9284 // Rotate Right by 8-bit immediate
9285 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9286 %{
9287 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9288 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9289
9290 expand %{
9291 rorL_rReg_imm8(dst, rshift, cr);
9292 %}
9293 %}
9294
9295 // Rotate Right by variable
9296 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9297 %{
9298 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9299
9300 expand %{
9301 rorL_rReg_CL(dst, shift, cr);
9302 %}
9303 %}
9304
9305 // Rotate Right by variable
9306 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9307 %{
9308 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9309
9310 expand %{
9311 rorL_rReg_CL(dst, shift, cr);
9312 %}
9313 %}
9314
9315 // Logical Instructions
9316
9448
9449 ins_encode %{
9450 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9451 %}
9452 ins_pipe(ialu_reg_mem);
9453 %}
9454
9455 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9456 match(Set dst (AndI (XorI src1 minus_1) src2));
9457 predicate(UseBMI1Instructions);
9458 effect(KILL cr);
9459
9460 format %{ "andnl $dst, $src1, $src2" %}
9461
9462 ins_encode %{
9463 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9464 %}
9465 ins_pipe(ialu_reg);
9466 %}
9467
9468 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
9469 match(Set dst (AndI (SubI imm_zero src) src));
9470 predicate(UseBMI1Instructions);
9471 effect(KILL cr);
9472
9473 format %{ "blsil $dst, $src" %}
9474
9475 ins_encode %{
9476 __ blsil($dst$$Register, $src$$Register);
9477 %}
9478 ins_pipe(ialu_reg);
9479 %}
9480
9481 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
9482 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9483 predicate(UseBMI1Instructions);
9484 effect(KILL cr);
9485
9486 ins_cost(125);
9487 format %{ "blsil $dst, $src" %}
9488
9489 ins_encode %{
9490 __ blsil($dst$$Register, $src$$Address);
9491 %}
9492 ins_pipe(ialu_reg_mem);
9493 %}
9494
9495 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9496 %{
9497 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9498 predicate(UseBMI1Instructions);
9499 effect(KILL cr);
9500
9501 ins_cost(125);
10144 %}
10145
10146 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10147 %{
10148 match(Set dst (CmpLTMask p q));
10149 effect(KILL cr);
10150
10151 ins_cost(400);
10152 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10153 "setlt $dst\n\t"
10154 "movzbl $dst, $dst\n\t"
10155 "negl $dst" %}
10156 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10157 setLT_reg(dst),
10158 REX_reg_breg(dst, dst), // movzbl
10159 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10160 neg_reg(dst));
10161 ins_pipe(pipe_slow);
10162 %}
10163
10164 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
10165 %{
10166 match(Set dst (CmpLTMask dst zero));
10167 effect(KILL cr);
10168
10169 ins_cost(100);
10170 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10171 ins_encode %{
10172 __ sarl($dst$$Register, 31);
10173 %}
10174 ins_pipe(ialu_reg);
10175 %}
10176
10177 /* Better to save a register than avoid a branch */
10178 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10179 %{
10180 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10181 effect(KILL cr);
10182 ins_cost(300);
10183 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10184 "jge done\n\t"
11477 match(Set cr (OverflowSubL op1 op2));
11478
11479 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11480 ins_encode %{
11481 __ cmpq($op1$$Register, $op2$$Register);
11482 %}
11483 ins_pipe(ialu_reg_reg);
11484 %}
11485
11486 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11487 %{
11488 match(Set cr (OverflowSubL op1 op2));
11489
11490 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11491 ins_encode %{
11492 __ cmpq($op1$$Register, $op2$$constant);
11493 %}
11494 ins_pipe(ialu_reg_reg);
11495 %}
11496
11497 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
11498 %{
11499 match(Set cr (OverflowSubI zero op2));
11500 effect(DEF cr, USE_KILL op2);
11501
11502 format %{ "negl $op2\t# overflow check int" %}
11503 ins_encode %{
11504 __ negl($op2$$Register);
11505 %}
11506 ins_pipe(ialu_reg_reg);
11507 %}
11508
11509 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11510 %{
11511 match(Set cr (OverflowSubL zero op2));
11512 effect(DEF cr, USE_KILL op2);
11513
11514 format %{ "negq $op2\t# overflow check long" %}
11515 ins_encode %{
11516 __ negq($op2$$Register);
11517 %}
11586 %{
11587 match(Set cr (CmpI op1 op2));
11588
11589 format %{ "cmpl $op1, $op2" %}
11590 opcode(0x81, 0x07); /* Opcode 81 /7 */
11591 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11592 ins_pipe(ialu_cr_reg_imm);
11593 %}
11594
11595 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11596 %{
11597 match(Set cr (CmpI op1 (LoadI op2)));
11598
11599 ins_cost(500); // XXX
11600 format %{ "cmpl $op1, $op2" %}
11601 opcode(0x3B); /* Opcode 3B /r */
11602 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11603 ins_pipe(ialu_cr_reg_mem);
11604 %}
11605
11606 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
11607 %{
11608 match(Set cr (CmpI src zero));
11609
11610 format %{ "testl $src, $src" %}
11611 opcode(0x85);
11612 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11613 ins_pipe(ialu_cr_reg_imm);
11614 %}
11615
11616 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
11617 %{
11618 match(Set cr (CmpI (AndI src con) zero));
11619
11620 format %{ "testl $src, $con" %}
11621 opcode(0xF7, 0x00);
11622 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11623 ins_pipe(ialu_cr_reg_imm);
11624 %}
11625
11626 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
11627 %{
11628 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11629
11630 format %{ "testl $src, $mem" %}
11631 opcode(0x85);
11632 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11633 ins_pipe(ialu_cr_reg_mem);
11634 %}
11635
11636 // Unsigned compare Instructions; really, same as signed except they
11637 // produce an rFlagsRegU instead of rFlagsReg.
11638 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11639 %{
11640 match(Set cr (CmpU op1 op2));
11641
11642 format %{ "cmpl $op1, $op2\t# unsigned" %}
11643 opcode(0x3B); /* Opcode 3B /r */
11644 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11645 ins_pipe(ialu_cr_reg_reg);
11646 %}
11660 match(Set cr (CmpU op1 (LoadI op2)));
11661
11662 ins_cost(500); // XXX
11663 format %{ "cmpl $op1, $op2\t# unsigned" %}
11664 opcode(0x3B); /* Opcode 3B /r */
11665 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11666 ins_pipe(ialu_cr_reg_mem);
11667 %}
11668
11669 // // // Cisc-spilled version of cmpU_rReg
11670 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11671 // //%{
11672 // // match(Set cr (CmpU (LoadI op1) op2));
11673 // //
11674 // // format %{ "CMPu $op1,$op2" %}
11675 // // ins_cost(500);
11676 // // opcode(0x39); /* Opcode 39 /r */
11677 // // ins_encode( OpcP, reg_mem( op1, op2) );
11678 // //%}
11679
11680 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
11681 %{
11682 match(Set cr (CmpU src zero));
11683
11684 format %{ "testl $src, $src\t# unsigned" %}
11685 opcode(0x85);
11686 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11687 ins_pipe(ialu_cr_reg_imm);
11688 %}
11689
11690 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11691 %{
11692 match(Set cr (CmpP op1 op2));
11693
11694 format %{ "cmpq $op1, $op2\t# ptr" %}
11695 opcode(0x3B); /* Opcode 3B /r */
11696 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11697 ins_pipe(ialu_cr_reg_reg);
11698 %}
11699
11700 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11998 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11999 %{
12000 match(Set cr (CmpUL src zero));
12001
12002 format %{ "testq $src, $src\t# unsigned" %}
12003 opcode(0x85);
12004 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12005 ins_pipe(ialu_cr_reg_imm);
12006 %}
12007
12008 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12009 %{
12010 match(Set cr (CmpI (LoadB mem) imm));
12011
12012 ins_cost(125);
12013 format %{ "cmpb $mem, $imm" %}
12014 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12015 ins_pipe(ialu_cr_reg_mem);
12016 %}
12017
12018 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI_0 zero)
12019 %{
12020 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12021
12022 ins_cost(125);
12023 format %{ "testb $mem, $imm\t# ubyte" %}
12024 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12025 ins_pipe(ialu_cr_reg_mem);
12026 %}
12027
12028 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
12029 %{
12030 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12031
12032 ins_cost(125);
12033 format %{ "testb $mem, $imm\t# byte" %}
12034 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12035 ins_pipe(ialu_cr_reg_mem);
12036 %}
12037
12038 //----------Max and Min--------------------------------------------------------
12039 // Min Instructions
12040
12041 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12042 %{
12043 effect(USE_DEF dst, USE src, USE cr);
12044
12045 format %{ "cmovlgt $dst, $src\t# min" %}
12046 opcode(0x0F, 0x4F);
12047 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12048 ins_pipe(pipe_cmov_reg);
12731 // Each peephole rule is given an identifying number starting with zero and
12732 // increasing by one in the order seen by the parser. An individual peephole
12733 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12734 // on the command-line.
12735 //
12736 // ---------CURRENT LIMITATIONS----------------------------------------------
12737 //
12738 // Only match adjacent instructions in same basic block
12739 // Only equality constraints
12740 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12741 // Only one replacement instruction
12742 //
12743 // ---------EXAMPLE----------------------------------------------------------
12744 //
12745 // // pertinent parts of existing instructions in architecture description
12746 // instruct movI(rRegI dst, rRegI src)
12747 // %{
12748 // match(Set dst (CopyI src));
12749 // %}
12750 //
12751 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
12752 // %{
12753 // match(Set dst (AddI dst src));
12754 // effect(KILL cr);
12755 // %}
12756 //
12757 // // Change (inc mov) to lea
12758 // peephole %{
12759 // // increment preceeded by register-register move
12760 // peepmatch ( incI_rReg movI );
12761 // // require that the destination register of the increment
12762 // // match the destination register of the move
12763 // peepconstraint ( 0.dst == 1.dst );
12764 // // construct a replacement instruction that sets
12765 // // the destination to ( move's source register + one )
12766 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12767 // %}
12768 //
12769
12770 // Implementation no longer uses movX instructions since
12771 // machine-independent system no longer uses CopyX nodes.
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