519
520 enum ExexPrefix {
521 EVEX_F = 0x04,
522 EVEX_V = 0x08,
523 EVEX_Rb = 0x10,
524 EVEX_X = 0x40,
525 EVEX_Z = 0x80
526 };
527
528 enum VexSimdPrefix {
529 VEX_SIMD_NONE = 0x0,
530 VEX_SIMD_66 = 0x1,
531 VEX_SIMD_F3 = 0x2,
532 VEX_SIMD_F2 = 0x3
533 };
534
535 enum VexOpcode {
536 VEX_OPCODE_NONE = 0x0,
537 VEX_OPCODE_0F = 0x1,
538 VEX_OPCODE_0F_38 = 0x2,
539 VEX_OPCODE_0F_3A = 0x3
540 };
541
542 enum AvxVectorLen {
543 AVX_128bit = 0x0,
544 AVX_256bit = 0x1,
545 AVX_512bit = 0x2,
546 AVX_NoVec = 0x4
547 };
548
549 enum EvexTupleType {
550 EVEX_FV = 0,
551 EVEX_HV = 4,
552 EVEX_FVM = 6,
553 EVEX_T1S = 7,
554 EVEX_T1F = 11,
555 EVEX_T2 = 13,
556 EVEX_T4 = 15,
557 EVEX_T8 = 17,
558 EVEX_HVM = 18,
559 EVEX_QVM = 19,
595 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
596 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
597
598 private:
599
600 int _evex_encoding;
601 int _input_size_in_bits;
602 int _avx_vector_len;
603 int _tuple_type;
604 bool _is_evex_instruction;
605 bool _legacy_mode_bw;
606 bool _legacy_mode_dq;
607 bool _legacy_mode_vl;
608 bool _legacy_mode_vlbw;
609 bool _instruction_uses_vl;
610
611 // 64bit prefixes
612 int prefix_and_encode(int reg_enc, bool byteinst = false);
613 int prefixq_and_encode(int reg_enc);
614
615 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
616 int prefixq_and_encode(int dst_enc, int src_enc);
617
618 void prefix(Register reg);
619 void prefix(Register dst, Register src, Prefix p);
620 void prefix(Register dst, Address adr, Prefix p);
621 void prefix(Address adr);
622 void prefixq(Address adr);
623
624 void prefix(Address adr, Register reg, bool byteinst = false);
625 void prefix(Address adr, XMMRegister reg);
626 void prefixq(Address adr, Register reg);
627 void prefixq(Address adr, XMMRegister reg);
628
629 void prefetch_prefix(Address src);
630
631 void rex_prefix(Address adr, XMMRegister xreg,
632 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
633 int rex_prefix_and_encode(int dst_enc, int src_enc,
634 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
635
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519
520 enum ExexPrefix {
521 EVEX_F = 0x04,
522 EVEX_V = 0x08,
523 EVEX_Rb = 0x10,
524 EVEX_X = 0x40,
525 EVEX_Z = 0x80
526 };
527
528 enum VexSimdPrefix {
529 VEX_SIMD_NONE = 0x0,
530 VEX_SIMD_66 = 0x1,
531 VEX_SIMD_F3 = 0x2,
532 VEX_SIMD_F2 = 0x3
533 };
534
535 enum VexOpcode {
536 VEX_OPCODE_NONE = 0x0,
537 VEX_OPCODE_0F = 0x1,
538 VEX_OPCODE_0F_38 = 0x2,
539 VEX_OPCODE_0F_3A = 0x3,
540 VEX_OPCODE_MASK = 0x1F
541 };
542
543 enum AvxVectorLen {
544 AVX_128bit = 0x0,
545 AVX_256bit = 0x1,
546 AVX_512bit = 0x2,
547 AVX_NoVec = 0x4
548 };
549
550 enum EvexTupleType {
551 EVEX_FV = 0,
552 EVEX_HV = 4,
553 EVEX_FVM = 6,
554 EVEX_T1S = 7,
555 EVEX_T1F = 11,
556 EVEX_T2 = 13,
557 EVEX_T4 = 15,
558 EVEX_T8 = 17,
559 EVEX_HVM = 18,
560 EVEX_QVM = 19,
596 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
597 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
598
599 private:
600
601 int _evex_encoding;
602 int _input_size_in_bits;
603 int _avx_vector_len;
604 int _tuple_type;
605 bool _is_evex_instruction;
606 bool _legacy_mode_bw;
607 bool _legacy_mode_dq;
608 bool _legacy_mode_vl;
609 bool _legacy_mode_vlbw;
610 bool _instruction_uses_vl;
611
612 // 64bit prefixes
613 int prefix_and_encode(int reg_enc, bool byteinst = false);
614 int prefixq_and_encode(int reg_enc);
615
616 int prefix_and_encode(int dst_enc, int src_enc) {
617 return prefix_and_encode(dst_enc, false, src_enc, false);
618 }
619 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
620 int prefixq_and_encode(int dst_enc, int src_enc);
621
622 void prefix(Register reg);
623 void prefix(Register dst, Register src, Prefix p);
624 void prefix(Register dst, Address adr, Prefix p);
625 void prefix(Address adr);
626 void prefixq(Address adr);
627
628 void prefix(Address adr, Register reg, bool byteinst = false);
629 void prefix(Address adr, XMMRegister reg);
630 void prefixq(Address adr, Register reg);
631 void prefixq(Address adr, XMMRegister reg);
632
633 void prefetch_prefix(Address src);
634
635 void rex_prefix(Address adr, XMMRegister xreg,
636 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
637 int rex_prefix_and_encode(int dst_enc, int src_enc,
638 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
639
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